13554 results about "Surface roughness" patented technology

To prevent both slips caused by damage from projections, and slips caused by adhesive force occurring due to excessive smoothing.The heat treating apparatus includes a processing chamber for heat treating wafers and a boat for supporting the wafers in the processing chamber. The boat further includes a wafer holder in contact with the wafer and a main body for supporting the wafer holder. The wafer holder diameter is 63 to 73 percent of the wafer diameter, and the surface roughness Ra of the portion of the wafer holder in contact with the wafer is set from 1 μm to 1,000 μm. The wafer can be supported so that the amount of wafer displacement is minimal and both slips due to damage from projections on the wafer holder surface, and slips due to the adhesive force occurring because of excessive smoothing can be prevented in that state.

A heat treatment jig for supporting silicon semiconductor substrates by contacting, being loaded onto a heat treatment boat in a vertical heat treatment furnace, comprises; the configuration of a ring or a disc structure with the wall thickness between 1.5 and 6.0 mm; the deflection displacement of 100 μm or less at contact region in loaded condition; the outer diameter which is 65% or more of the diameter of said substrate; and the surface roughness (Ra) of between 1.0 and 100 μm at the contact region. The use of said jig enables to effectively retard the slip generation and to avoid the growth hindrance of thermally oxidized film at the back surface of said substrate, diminishing the surface steps causing the defocus in photolithography step in device fabrication process, thereby enabling to maintain high quality of silicon semiconductor substrates and to substantially enhance the device yield.

A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process the method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and / or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.

Methods for transferring a useful layer of silicon carbide to a receiving substrate are described. In an embodiment, the invention relates to a method for recycling of a silicon carbide source substrate by removal of the excess zone followed by a finishing step to prepare the source substrate for recycling and reuse. Preferably, the excess zone is removed by a thermal budget where the temperature and time of such treatment causes exfoliation of the excess zone. The finishing step is performed in a manner to provide the desired surface roughness for the substrate so that it can be recycled for re-use. The technique includes implanting at least H+ ions through a front face of a source substrate of silicon carbide with an implantation energy E greater than or equal to 95 keV and an implantation dose D chosen to form an optimal weakened zone near a mean implantation depth, the optimal weakened zone defining the useful layer and a remainder portion of the source substrate. The method also includes bonding the front face of the source substrate to a contact face of the receiving substrate, and detaching the useful layer from the remainder portion of the source substrate along the weakened zone while minimizing or avoiding forming an excess zone of silicon carbide material at the periphery of the useful layer that was not transferred to the receiving substrate during detachment.

An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the n-type layer of material. The confinement structure is generally aligned with the contact on the top and primary emission surface of the LED and substantially prevents the emission of light from the area of the active region that is coincident with the area of the confinement structure and the top-surface contact. The LED may include a roughened emitting-side surface to further enhance light extraction.

An electrode for a lithium battery having a thin film composed of active material capable of lithium storage and release, e.g., a microcrystalline or amorphous silicon thin film, provided on a current collector, the electrode being characterized in that the current collector has a surface roughness Ra of 0.01 μm or greater.