Non-contact etch annealing of strained layers

Abstract

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

Description

RELATED APPLICATIONS [0001] This application claims the benefit of U.S. Provisional Application No. 60 / 484,181; filed Jun. 30, 2003, and is a continuation-in-part of U.S. application Ser. No. 10 / 264,393, filed Oct. 4, 2002.FIELD OF THE INVENTION [0002] Embodiments of the present invention relate to controlling the growth and morphology of surface roughness during an annealing and relaxation process of strained films, and more particularly to decreasing surface crystalline dislocations during a relaxation process. BACKGROUND OF THE INVENTION [0003] In the conventional art, many semiconductor device fabrication processes utilize planar surfaces. Furthermore, as semiconductor fabrication technology progresses, increasing carrier mobility and decreasing lattice dislocation density become increasingly critical. Improving device yields by reducing dislocations provides for improved manufacturing efficiencies and cost. [0004] In the conventional art, a silicon layer is used as the active d...

AI Technical Summary

Benefits of technology

[0019] A method for etch annealing a semiconductor layer is disclosed. In addition to its significant effect in controlling the roughness increases during the relaxation process, the method has the unexpected benefit of substantially reducing dislocations. The reduced dislocation density is advantageous in that carrier mobility and yield are increased.

[0020] In one embodiment, a method of forming a strained semiconductor layer is provided. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the now relaxed second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the added benefit of reducing dislocations in the semiconductor layers.

Problems solved by technology

Furthermore, as semiconductor fabrication technology progresses, increasing carrier mobility and decreasing lattice dislocation density become increasingly critical.

A fundamental complication of this mobility enhancement approach is the requirement of a relaxed SiGe film.

Dislocations present on the device layer can tend to short-circuit p-n junctions and also scatter electrons in a uniform n-type crystal, impeding their motion and reducing their mobility.

Dislocations also cause highly localized distortion of the crystal lattice leading to the formation of “trapping” sites where the recombination of positive (holes) and negative (electrons) carriers is enhanced.

Many of the relaxation approaches are therefore tuned to minimize the defect density of the type that can be translated to the device layer and cause device performance degradation, failure and yield losses.

This shallow gradient approach is lower in productivity due to its relatively thick SiGe layer composition and may require numerous growth / anneal cycles to achieve roughness and dislocation goals.

However, CMP is relatively costly as a result of the slurry and the amount of time it takes to perform the process.

Furthermore, the CMP process does not generally reduce the dislocation density in the wafer.

Finally, this linear growth / anneal / CMP sequence is costly as it requires numerous sequential process and wafer handling steps.

Although the base substrate miscut can improve the relaxed defect density to some extent, the improvements are generally considered insufficient for leading edge applications.

The use of an epitaxial step such as CVD (Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) followed by a planarization step such as CMP significantly complicates the film relaxation preparation process since multiple equipment, cleans, and wafer handling are required.

This in turn would increase the manufacturing cost of the relaxed film fabrication process.

Thus, the conventional art is disadvantageous in that planarizing processes are relatively costly and time-consuming processes.

The conventional art also suffers from relatively high levels of dislocations.

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