2109results about "After-treatment details" patented technology

A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates.

A thermal treatment apparatus 1 includes a reaction tube 2 for containing wafers 10 contaminated with organic substances having a heater 12 capable of heating the reaction tube; a first gas supply pipe 13 for carrying oxygen gas into the reaction tube 2; and a second gas supply pipe 14 for carrying hydrogen gas into the reaction tube 2. Oxygen gas and hydrogen gas are supplied through the first gas supply pipe 13 and the second gas supply pipe 14, respectively, into the reaction tube 2, and the heater 12 heats the reaction tube 2 at a temperature capable of activating oxygen gas and hydrogen gas. A combustion reaction occurs in the reaction tube 2 and thereby the organic substances adhering to the wafers 10 are oxidized, decomposed and removed.

Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed.

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

A method of making a virtual substrate includes providing a donor substrate comprising a single crystal donor layer of a first material over a support substrate, wherein the first material comprises a ternary, quaternary or penternary semiconductor material or a material which is not available in bulk form, bonding the donor substrate to a handle substrate, and separating the donor substrate from the handle substrate such that a single crystal film of the first material remains bonded to the handle substrate.

Al_xGa_yIn_zN, wherein 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μm² area. The Al_xGa_yIn_zN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality Al_xGa_yIn_zN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an Al_xGa_yIn_zN wafer.

A method of controllably aligning carbon nanotubes to a template structure to fabricate a variety of carbon nanotube containing structures and devices having desired characteristics is provided. The method allows simultaneous, selective growth of both vertically and horizontally controllably aligned nanotubes on the template structure but not on a substrate in a single process step.

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10<5>, nitrogen source material partial pressure in a range of from about 1 to about 10<3 >torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 10<2 >microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

The present invention is related to a process for obtaining a larger area substrate of mono-crystalline gallium-containing nitride by making selective crystallization of gallium containing nitride on a smaller seed under a crystallization temperature and/or pressure from a supercritical ammonia-containing solution made by dissolution of gallium-containing feedstock in a supercritical ammonia-containing solvent with alkali metal ions, comprising: providing two or more elementary seeds, and making selective crystallization on the two or more separate elementary seeds to get a merged larger compound seed. The merged larger compound seed is used for a seed in a new growth process and then to get a larger substrate of mono-crystal gallium-containing nitride.

A method of smoothing a silicon surface formed on a substrate. According to the present invention a substrate having a silicon surface is placed into a chamber and heated to a temperature of between 1000°-1300° C. While the substrate is heated to a temperature between 1000°-1300° C., the silicon surface is exposed to a gas mix comprising H2 and HCl in the chamber to smooth the silicon surface.

A method for removing defects at high pressure and high temperature (HP/HT) or for relieving strain in a non-diamond crystal commences by providing a crystal, which contains defects, and a pressure medium. The crystal and the pressure medium are disposed in a high pressure cell and placed in a high pressure apparatus, for processing under reaction conditions of sufficiently high pressure and high temperature for a time adequate for one or more of removing defects or relieving strain in the single crystal.

A nanoparticle including an inorganic core comprising at least one metal and/or at least one semi-conductor compound comprising at least one metal includes a coating or shell disposed over at least a portion of a surface of the core. The coating can include one or more layers. Each layer of the coating can comprise a metal and/or at least one semiconductor compound. The nanoparticle further includes a ligand attached to a surface of the coating. The ligand is represented by the formula: X-Sp-Z, wherein X represents, e.g., a primary amine group, a secondary amine group, a urea, a thiourea, an imidizole group, an amide group, a phosphonic or arsonic acid group, a phosphinic or arsinic acid group, a phosphate or arsenate group, a phosphine or arsine oxide group; Sp represents a spacer group, such as a group capable of allowing a transfer of charge or an insulating group; and Z represents: (i) reactive group capable of communicating specific chemical properties to the nanocrystal as well as provide specific chemical reactivity to the surface of the nanocrystal, and/or (ii) a group that is cyclic, halogenated, or polar a-protic. In certain embodiments, at least two chemically distinct ligands are attached to an surface of the coating, wherein the at least two ligands (I and II) are represented by the formula: X-Sp-Z. In ligand (I) X represents a phosphonic, phosphinic, or phosphategroup and in ligand (II) X represents a primary or secondary amine, or an imidizole, or an amide; In both ligands (I) and (II) Sp, which can be the same or different in the two compounds, represents a spacer group, such as a group capable of allowing a transfer of charge or an insulating group; Z, which can be the same or different in the two compounds, is a group chosen from among groups capable of communicating specific chemical properties to the nanoparticle as well as provide specific chemical reactivity to the surface of the nanoparticle. In preferred embodiments, the nanoparticle includes a core comprising a semiconductor material.

A method of creating thin wafers of single crystal silicon wherein an ingot of single-crystal silicon with a (111) axis is flattened and polished at one end normal to the axis, and a notch with a vertex in the (111) plane is produced on a side or edge of the ingot, such that the distance between this vertex and said end is the desired thickness of a wafer to be cleaved from the ingot and such this vertex is in the desired plane of cleavage. Light of a wavelength able to penetrate into the silicon crystal without significant absorption, when the intensity of the beam is low, but is efficiently absorbed and converted to heat when the intensity of the beam is high, is focused to an elongated volume with an axis of elongation in the desired cleavage plane, parallel to and a short distance from said notch edge. Heating and the resulting transient local expansion of the silicon in this illuminated volume causes tensile stress at the vertex of said notch, substantially normal to the desired cleavage plane, thereby causing fracture of the crystal in the chosen cleavage plane. Movement of the illuminated volume relative to the ingot allows the fracture to propagate across the desired cleavage plane, thereby completely severing the wafer from the rest of the ingot.

A method is disclosed for fabricating monocrystal material with the bandgap width exceeding 1.8 eV. The method comprises the steps of processing a monocrystal semiconductor wafer to develop a porous layer through electrolytic treatment of the wafer at direct current under UV-illumination, and epitaxially growing a monocrystal layer on said porous layer. Growth on porous layer produces semiconductor material with reduced stress and better characteristics than with the same material grown on non-porous layers and substrates. Also, semiconductor device structure comprising at least one layer of porous group III material is included.

Provided is a method of producing a semiconductor thin film wherein while a semiconductor thin film formed on a substrate is supported on a curved surface of a support member having the curved surface, the support member is rotated, thereby peeling the semiconductor thin film away from the substrate. Also provided is a method of producing a semiconductor thin film having the step of peeling a semiconductor thin film formed on a substrate away from the substrate, wherein the peeling step is carried out after the substrate is secured on a substrate support member without an adhesive. These provide the method of peeling the semiconductor thin film away from the substrate without damage and the method of holding the substrate without contamination.

In designing a precision monolithic structure having all discrete components with different Coefficient of Thermal Expansion (CTE) permanently bonded together, to avoid internal stress caused by changing of temperature: The Coefficient of Thermal Expansion (CTE) Adaptor must be bonded between two components having different Coefficient of Thermal Expansion (CTE); the Bonding Interfaces must be parallel; the Coefficient of Thermal Expansion (CTE) Adaptor is made of material having varied CTE, the variation must be gradual and in only one direction, which is perpendicular to the said Bonding Interfaces; at each Bonding Interface, the CTE of the CTE Adaptor must match the CTE of bonding component in certain degree.

The influence of surface geometry on metal properties is studied within the limit of the quantum theory of free electrons. It is shown that a metal surface can be modified with patterned indents to increase the Fermi energy level inside the metal, leading to decrease in electron work function. This effect would exist in any quantum system comprising fermions inside a potential energy box. Also disclosed is a method for making nanostructured surfaces having perpendicular features with sharp edges.

A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.

Fluidic nanotube devices are described in which a hydrophilic, non-carbon nanotube, has its ends fluidly coupled to reservoirs. Source and drain contacts are connected to opposing ends of the nanotube, or within each reservoir near the opening of the nanotube. The passage of molecular species can be sensed by measuring current flow (source-drain, ionic, or combination). The tube interior can be functionalized by joining binding molecules so that different molecular species can be sensed by detecting current changes. The nanotube may be a semiconductor, wherein a tubular transistor is formed. A gate electrode can be attached between source and drain to control current flow and ionic flow. By way of example an electrophoretic array embodiment is described, integrating MEMs switches. A variety of applications are described, such as: nanopores, nanocapillary devices, nanoelectrophoretic, DNA sequence detectors, immunosensors, thermoelectric devices, photonic devices, nanoscale fluidic bioseparators, imaging devices, and so forth.

The invention relates to an ingot casting method for quasi-monocrystalline silicon, which comprises the following steps of: (1) laying seed crystals at the bottom of a quartz crucible and adding a silicon material and a doping agent on the seed crystals; (2) vacuumizing and heating the crucible with the materials, raising the temperature in sections to melt the silicon material on the upper part, when the seed crystals begin to melt at the later stage of melting, controlling the temperatures and heating rates of a heater and the bottom of the crucible to partially melt the seed crystals and then entering a crystal growing stage; (3) cooling the heater in sections at the stage of crystal growing to make silicon crystals grow along the direction of unmelted seed crystals, and annealing and cooling after the silicon crystals grows to obtain large-gain silicon ingots; and (4) performing subsequent treatment on the large-grain silicon ingots to obtain the quasi-monocrystalline silicon. In the method, melting and crystal growing and the like are finished in the same equipment and in the same crucible, and the seed crystals are melted by controlling the temperature of the bottom of the crucible and the heating rate of the heater, so that the method has the advantages of low cost, easy operation and suitability for mass production; and the prepared quasi-monocrystalline silicon has high conversion efficiency, and the seed crystals can be recycled.

An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

A method for stabilizing colloidal suspensions of nanocrystals or nanoparticles in a solvent or solid matrix is provided by coating the nanocrystals with bulky organic molecules, specifically dendrons. By coating nanocrystals with a dense organic dendron coat and further cross-linking the dendron ligands, oxidation of the nanocrystals and dissociation of the ligands are avoided. This invention allows nanocrystals to undergo rigorous purification and processing. It may regularly be applied to a variety of nanocrystals.

An antenna structure includes a coil unit formed by etching a conductive film in a non-display area of a display and a set of electrodes for transmitting signals connected to terminals of the coil unit. The antenna structure can be a near field communication antenna or a radio frequency identification antenna to transmit and receive signals with the coil unit formed in the non-display area of the display to save the occupation space in a portable communication device. Therefore, the antenna structure can effectively reduce the size of the portable communication device.

Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased.

A method of fabricating free-standing (Al, In, Ga)N substrates, by in situ separation of thick epitaxially grown nitride films from their foreign substrates. A suitable substrate for (Al, In, Ga)N film growth is selected, and foreign ions are implanted in the substrate to form a comparatively sharp concentration profile. An (Al, In Ga)N film is deposited on the substrate, and the deposited film is cooled to introduce thermal expansion mismatch-related strain, so that the film spontaneously separates from the substrate.

This method of removal of irregularities and highly defected regions of the surface of crystals and epitaxial layers of GaN and Ga1-x-yAlxInyN characterized by mechano-chemical polishing on the soft polishing pad under pressure in presence of chemical etching agent of water solution of bases of the total concentration above 0.01N in time longer than 10 seconds after which the agent is replaced by the pure water without interruption of the polishing and polishing by at least 1 minute aid subsequent diminution of the load and stopping of the machine and then the polished GaN crystal or GaAlInN epitaxial layer is removed of the polishing machine and dried in the stream of dry nitrogen.

A liquid crystal display device is manufactured by first forming a crystalline semiconductor film 2103, of silicon for example, over an insulating substrate 2101, such as glass. The substrate is warped in the process. The warpage is corrected by suction against a stage 2201. The film crystallinity is enhanced by scanning with a linear laser beam.

It is an object of the present invention to provide a manufacturing method of a single crystal substrate and to provide an internal modified layer-forming single crystal member, each of which is capable of easily manufacturing a relatively large and thin single crystal substrate. The manufacturing method of a single crystal substrate includes: the step of arranging a condensing lens (15), which emits laser beams (B) and corrects aberration caused by a refractive index of a single crystal member (10), contactlessly on the single crystal member (10); the step of irradiating the laser beams onto a surface (10t) of the single crystal member (10), and condensing the laser beams into an inside of the single crystal member; the step of moving the condensing lens (15) and the single crystal member (10) relatively to each other, and forming a two-dimensional modified layer (12) in the inside of the single crystal member (10); and the step of exfoliating a single crystal layer, which is formed by being divided by the modified layer (12), from the modified layer (12), thereby forming a single crystal substrate.

A synthetic diamond material comprising one or more spin defects having a full width half maximum intrinsic inhomogeneous zero phonon line width of no more than 100 MHz. The method for obtain such a material involves a multi-stage annealing process.