20results about How to "Avoid etching" patented technology

The invention discloses an automatic control etching system and method for a printed circuit board, and relates to the technical field of circuit boards, and the method comprises the following steps: 1, an operator puts a to-be-etched PCB into an etching groove, and inputs target etching parameters through a human-computer interaction interface; 2, the multi-dimensional sensor module continuously monitors key parameters in the etching tank, and data is transmitted to the central controller; 3, according to the data provided by the sensor, the central controller calculates a real-time etching rate by using a nonlinear kinetic model; 4, when the real-time etching rate deviates from the target rate, the system starts an adaptive control algorithm for adjustment; 5, when the system detects that the set etching depth or width reaches a target value, the etching process is automatically stopped, and key data are recorded; and step 6, the system analyzes based on the stored historical data, provides optimal etching parameters and adjustment strategies for different types of PCBs, and displays the data in real time through a human-computer interaction interface module.

The invention relates to the technical field of photovoltaic cells, and provides copper electrode slurry, a metal electrode, a preparation method of the metal electrode and a photovoltaic cell. The copper electrode slurry comprises a metal composition, a dispersion reducing agent, a composite curing agent and an optional solvent, the metal composition at least comprises copper powder and optional gold powder and / or silver powder; the composite curing agent comprises thermosetting resin and a latent curing agent; wherein the mass ratio of the metal composition to the composite curing agent is (7-30): 1. The copper electrode paste provided by the invention replaces expensive silver paste, so that the manufacturing cost of a solar cell energy electrode is greatly reduced. According to the method for preparing the metal electrode, the position of the copper electrode can be precisely machined, damage to the amorphous silicon layer is avoided, remelting and solidification of the copper electrode are achieved through multiple times of laser scanning, and the problem that the adhesive force between the copper electrode and the substrate is poor is effectively solved.

The invention belongs to the field of batteries, and particularly relates to a phosphoryl isocyanate additive, a preparation method of the phosphoryl isocyanate additive, an electrolyte, the additive and a lithium ion battery. The structure of the phosphoryl isocyanate additive is shown as the following formula (A): # imgabs0 #, R1 is one of alkyl, alkoxy, phenoxyl, alkenyl, alkynyl, phenyl and substitutes thereof with the carbon atom number of 1-6, and R2 is one of isocyanate, alkyl, alkenyl, alkynyl, phenyl and substitutes thereof with the carbon atom number of 1-6. By adding a small amount of phosphoryl isocyanate additive into the electrolyte, a CEI structure which is relatively low in resistance and stable under a high-voltage condition is formed on the surface of a positive electrode, so that the rate capability and the high-voltage cycle stability of the battery can be improved.

The utility model provides a wire structure. The wire structure comprises a first dielectric layer; the seed layer is arranged on the first dielectric layer; the conductive trace is arranged on the upper surface, deviating from the first dielectric layer, of the seed layer; and the second dielectric layer covers the conductive trace and is in contact with the upper surface of the seed layer. In the prior art, in the wet etching process of a seed layer, an etching solution etches a conductive trace at the same time, so that the conductive trace is thinned, and the bending strength of the conductive trace is easily reduced and even broken, the photoresist is used as a protective layer before etching, the conductive trace is separated from the etching solution, and the conductive trace is prevented from being damaged. Therefore, when the seed layer is etched, the conductive traces are not etched, the conductive traces are prevented from being thinned, the bending strength of the conductive traces is ensured, the normal work of the whole lead structure is ensured, and the problems of open circuit and the like are avoided.

This invention discloses a β-Ga₂O₃ nanowire / diamond heterostructure, its preparation method, and its applications. The method includes the following steps: dropping Ga metal droplets onto an auxiliary substrate; placing the diamond substrate and the auxiliary substrate in the same temperature zone of a tube furnace; introducing a mixed gas of H₂ and Ar into the tube furnace under negative pressure, using O₂ entering from the outside and residual O₂ in the tube furnace as the O source, and growing β-Ga₂O₃ nanowires on the diamond surface without catalysis. The method of this invention eliminates the need for additional annealing treatment and pre-laying of metal catalysts on the diamond substrate, and avoids the phenomenon of O₂ etching of the diamond substrate under high-temperature conditions. β-Ga₂O₃ nanowires are epitaxially grown on the diamond surface through the vapor deposition of Ga. This method is simple and low-cost.

The invention provides a method for growing and stripping polycrystalline diamond with low stress, the principle of the method is that the characteristic that a substrate and a transition layer are low in mismatch with the polycrystalline diamond is utilized, and meanwhile, the substrate is etched by hydrogen after the polycrystalline diamond grows by utilizing the strong etching capability of the hydrogen, so that the intervention of extra stress is avoided, and the polycrystalline fracture is reduced. Compared with the prior art, the scheme can effectively reduce the breakage of the polycrystalline diamond during stripping, and can be applied to solve the problem of low yield caused by breakage of the industrial MPCVD polycrystalline diamond.

The invention discloses a method for reducing epitaxial surface defects of silicon carbide. The aim of reducing the number of epitaxial surface defects is achieved by modifying a graphite piece of a reaction chamber of a silicon carbide epitaxial furnace. According to the method, an air flotation channel is additionally arranged on a graphite piece at the lower part of a reaction chamber, and a pressure balance hole is formed in a protective cover plate above the graphite piece at the lower part of the reaction chamber; in the SiC epitaxial growth process, the carrier gas flows to generate negative pressure near the pressure balance hole, so that the air floating gas leaves the growth area of the SiC epitaxial wafer along the air floating channel under the action of the negative pressure, and the probability that particles carried by the air floating gas fall onto the surface of the epitaxial wafer to form surface defects is reduced. And the method is compatible with a mainstream SiC epitaxial furnace and an epitaxial process, is suitable for industrial production, and has great popularization value.

The application discloses a deep-groove polysilicon etching solution, which comprises an oxidizing agent, an inorganic acid, a pH regulator and a surfactant. The deep-groove polysilicon etching solution can efficiently etch polysilicon while ensuring the uniformity and smoothness of the etching surface, and can maximize the consistency of the etching of the upper and lower grooves and the smoothness of the surface. In the etching process, the inorganic acid ensures that the etching solution system is in an acidic environment, and the polysilicon is etched; the pH regulator avoids the large fluctuation of the pH of the etching solution, thereby ensuring the stability of the polysilicon etching process; and the surfactant reduces the surface tension of the etching solution, improves the wettability of the etching solution, ensures the consistency of the etching rate of the upper and lower grooves, and ensures the consistency of the groove aperture.

The invention discloses a process method for eliminating an antenna effect of a power device with an ESD (Electro-Static Discharge) structure, which comprises the following steps of: after etching a polycrystalline silicon grid of the power device, depositing to form a silicon nitride layer; forming an ESD (Electro-Static Discharge) oxide layer on the silicon nitride layer, and depositing a polycrystalline silicon layer on the ESD oxide layer; performing ion implantation of the ESD structure; carrying out photoetching and etching on the polycrystalline silicon layer of the ESD structure, completing pattern formation of the polycrystalline silicon structure in the ESD structure, and then carrying out thermal annealing; carrying out a wet etching process of the ESD oxide layer, and removing the redundant ESD oxide layer; removing the silicon nitride layer by a wet etching process; and performing body region injection of the power device. SiN is introduced to serve as a barrier layer for wet etching of the ESD oxide layer, the antenna effect caused by ESD OX local over-etching can be effectively prevented, the convergence of BV voltage resistance and IDSS electric leakage is improved, and the occurrence probability of low product yield can be remarkably reduced.

The application discloses a fluorine-containing silicon nitride etching solution, which comprises phosphoric acid, a fluorine-containing compound, an aluminum oxide etching inhibitor, a tungsten etching inhibitor, a silicon oxide etching inhibitor and deionized water. The etching solution can realize selective etching of silicon nitride to silicon oxide, aluminum oxide and tungsten in hot phosphoric acid, while inhibiting etching of the silicon oxide, and the etching rate of the silicon nitride is more stable at high temperature than that of a phosphoric acid / hydrofluoric acid system due to the complexing and slow-release effect of the fluorine-containing compound.

The application relates to the field of optical communication technology, and particularly discloses a one-way coupling vertical grating coupler implementation method based on topological photonics; the method is based on an SOI platform, first, the size parameters of a uniform grating coupler are modeled and optimized; a single-etching rectangle in the grating is replaced by double-adjacent-rectangle etching to form a stepped structure, the up-down symmetry of the grating is destroyed, and the downward radiation is inhibited and the upward coupling is strengthened relying on the topological one-way coupling resonance principle; a super-Gaussian chirp function is introduced to modulate the etching width, the central period index, the envelope width and the super-Gaussian order are optimized, and the fiber mode field is matched; meanwhile, a waveguide and grating differential height design is adopted to expand the optimization space. The application does not need a DBR mirror and can be prepared only by surface etching, so the process is simplified; the grating to single-mode fiber coupling efficiency reaches 83.7%, the 3dB bandwidth is more than 79nm, and the application has the advantages of high coupling efficiency, wide bandwidth and high process fault tolerance.

The invention relates to a polycrystalline silicon etching solution, which is prepared from the following components in percentage by mass: 0.1 to 2.38 percent of quaternary ammonium salt compounds, 1 to 40 percent of alcohol amine compounds, 1 to 40 percent of polyhydric alcohol compounds, 0.1 to 2 percent of etching accelerant and the balance of deionized water. The sum of the parts by weight of the components is 100%. The alcohol amine compound and the polyhydric alcohol compound have a synergistic effect, so that the etching rate of SiO2 can be effectively reduced; the etching accelerator can improve the etching rate of the polycrystalline silicon, improve the etching uniformity and improve the surface roughness of the polycrystalline silicon.

The invention discloses a fluorine-containing silicon nitride etching solution. The etching solution comprises phosphoric acid, a fluorine-containing compound, an aluminum oxide etching inhibitor, a tungsten etching inhibitor, a silicon oxide etching inhibitor and deionized water. The etching solution can realize selective etching of silicon nitride, silicon oxide, aluminum oxide and tungsten in hot phosphoric acid and inhibit etching of silicon oxide at the same time, and the etching rate of silicon nitride is more stable than that of a phosphoric acid / hydrofluoric acid system at a high temperature due to the complexing slow-release effect of the fluorine-containing compound.

The invention provides an MZ type electro-optical modulator and a preparation method thereof. The MZ type electro-optical modulator comprises a substrate layer, a silicon waveguide layer, a first isolation layer, a silicon nitride waveguide layer, a second isolation layer, a lithium niobate film layer, a third isolation layer and a metal layer from bottom to top. The surface of the substrate layer is an insulating material layer; the silicon waveguide layer comprises a beam splitter and a beam combiner which are positioned on two opposite sides, and more than two modulation arms which are respectively connected with the beam splitter and the beam combiner and oppositely extend to corresponding coupling areas; a mixed waveguide formed by a silicon nitride strip-shaped waveguide of the silicon nitride waveguide layer and a lithium niobate thin film layer located on the upper layer of the silicon nitride strip-shaped waveguide serves as an active modulation arm, and the thickness of a second isolation layer located between the silicon nitride waveguide layer and the lithium niobate thin film layer is smaller than 50 nm. According to the invention, the performance of the modulator is improved, the transmission loss is reduced, the preparation process is simplified, the preparation cost is reduced, and large-scale popularization and application of the modulator are facilitated.

The present invention provides a p-GaN HEMT device and a preparation method, a substrate layer; a buffer layer arranged on the substrate layer, a side of the buffer layer away from the substrate layer is provided with a P-type doping region; a channel layer arranged on the buffer layer, the channel layer is in contact with the P-type doping region; a barrier layer, a source electrode and a drain electrode arranged on the channel layer, the source electrode and the drain electrode are arranged on both sides of the barrier layer; a heat dissipation layer arranged on the barrier layer; a cap layer arranged on the barrier layer and on the heat dissipation layer; a passivation layer arranged on the heat dissipation layer, the passivation layer is arranged between the source electrode and the cap layer and between the drain electrode and the cap layer; a gate electrode arranged on the cap layer. The beneficial effects of the present invention are that the number of defects and the interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, the influence of interface reaction and defects on the working performance of the device can be reduced, the electric field at the 2DEG channel can be effectively modulated, the thermal management capability of the device itself can be improved, and the stability and reliability of the device operation can be improved.

The invention relates to the technical field of sulfur-doped iron-aluminum bimetallic materials, in particular to a defect-rich S-FeAl LDHet catalyst and a preparation method and application thereof. A non-noble metal electrocatalyst S-FeAl LDH growing on a foamed nickel substrate in situ is synthesized through a hydrothermal method, then CV selective etching of Al sites is conducted on the catalyst S-FeAl LDH under the alkaline condition, the morphology and the electronic structure of the catalyst are regulated and controlled, and the defect-rich S-FeAl LDHet catalyst is formed. According to the invention, Al etching is carried out on the electrochemical window of the OER, so that the morphology of the catalyst does not change, and the mechanical strength of the catalyst is also retained. According to the method for constructing the defect by electrochemical in-situ etching of Al, the catalytic performance can be intuitively obtained through a CV curve. The optimal etching amount is determined according to the number of CV etching turns, and complete exposure of active sites is ensured. Meanwhile, the conductivity of the catalyst can also be optimized.

The application relates to a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate; forming a plurality of first passivation layers arranged at intervals on the surface of the substrate; forming a plurality of ridges in the substrate, each ridge comprising part of the substrate, and each ridge having two sidewalls in the form of grooves formed in the substrate; wherein the first passivation layer is located on the ridge, and the total height of the first passivation layer and the ridge is greater than a height threshold; forming a second passivation layer on the surface of the substrate and the surface of each first passivation layer; forming a first photoresist layer on the surface of the second passivation layer; performing a patterning process on the first photoresist layer to expose the second passivation layer away from the first passivation layer and the second passivation layer on the ridge; and using a reflow process to make the first photoresist layer in each groove reflow along the sidewall of the ridge to cover the second passivation layer on the two sidewalls of the ridge. The application increases the height of the first passivation layer to improve the success rate of the reflow process, so that the reflow process is suitable for semiconductor devices with different ridge heights.

The invention discloses an electro-optical modulator and a preparation method thereof. The electro-optical modulator comprises an electro-optical material film wafer; the covering belt is arranged on the upper surface of the electro-optical material film wafer and is used for restraining a transverse electric mode; the traveling wave electrodes are arranged on the upper surface of the electro-optical material film wafer and located on the two sides of the covering belt. According to the invention, the preparation of the high-performance electro-optical modulator on the non-etching electro-optical material film is realized.

A display device and a method of manufacturing the same are provided. The display device includes a substrate including an emission area and a non-emission area, a pixel electrode positioned on the emission area of the substrate, a pixel defining layer positioned on the pixel electrode, overlapping the non-emission area, and having a first opening defined therein, a bank structure positioned on the pixel defining layer, an auxiliary electrode positioned on the non-emission area, and a common electrode positioned on the non-emission area and having a second opening defined therein, a bank structure positioned on the pixel defining layer and having a second opening defined therein, an auxiliary electrode positioned on the bank structure and including a conductive material, a common electrode positioned on the pixel electrode and contacting the auxiliary electrode in the second opening, and wherein the bank structure includes a first bank layer and a second bank layer including conductive materials different from each other, the second bank layer includes a tip protruding from a side surface of the first bank layer toward the first opening, and the auxiliary electrode completely covers the tip of the second bank layer.

The invention belongs to the technical field of photon detection, and relates to a silicon oxide microsphere array enhanced germanium detector and a preparation method thereof. The method specifically comprises the following steps: carrying out chemical cleaning on a Si single crystal wafer; monodispersing silicon oxide powder in water to prepare a microsphere solution; coating the silicon single crystal wafer with the microsphere solution to prepare a silicon oxide microsphere array; transferring the silicon oxide microsphere array to a polydimethylsiloxane adhesive tape, and then transferring the silicon oxide microsphere array to the surface of the germanium detector body to obtain a silicon oxide microsphere array enhanced germanium detector structure; the preparation cost is low, and the obtained silicon oxide microsphere array enhanced germanium detector is high in performance.