40results about How to "Avoid etching" patented technology

The invention discloses an automatic control etching system and method for a printed circuit board, and relates to the technical field of circuit boards, and the method comprises the following steps: 1, an operator puts a to-be-etched PCB into an etching groove, and inputs target etching parameters through a human-computer interaction interface; 2, the multi-dimensional sensor module continuously monitors key parameters in the etching tank, and data is transmitted to the central controller; 3, according to the data provided by the sensor, the central controller calculates a real-time etching rate by using a nonlinear kinetic model; 4, when the real-time etching rate deviates from the target rate, the system starts an adaptive control algorithm for adjustment; 5, when the system detects that the set etching depth or width reaches a target value, the etching process is automatically stopped, and key data are recorded; and step 6, the system analyzes based on the stored historical data, provides optimal etching parameters and adjustment strategies for different types of PCBs, and displays the data in real time through a human-computer interaction interface module.

The invention discloses a manufacturing method of a resonator and the resonator. The manufacturing method comprises the step of sequentially manufacturing a first electrode layer, a piezoelectric layer and a second electrode layer in a stacked mode. A supporting layer is manufactured on the surface of the side, away from the piezoelectric layer, of the second electrode layer, the supporting layer comprises a plurality of first protruding blocks arranged at intervals, and a first concave part is formed between every two adjacent first protruding blocks. And manufacturing a cut-off boundary layer covering the surface of one side, far away from the piezoelectric layer, of the first bump and the wall surface of the first concave part. And manufacturing a plurality of second gaps penetrating through the first electrode layer on the first electrode layer, wherein the second gaps divide the first electrode layer into a plurality of first electrodes. A plurality of grooves penetrating through the piezoelectric layer are manufactured in the piezoelectric layer, the piezoelectric layer is divided into a plurality of piezoelectric bodies through the grooves, and the second electrodes are exposed out of the grooves; manufacturing a barrier layer, wherein the barrier layer at least covers the bottom of each groove; and removing the at least two first bumps to enable the second electrode and the cut-off boundary layer to form at least two cavities.

The invention relates to the technical field of photovoltaic cells, and provides copper electrode slurry, a metal electrode, a preparation method of the metal electrode and a photovoltaic cell. The copper electrode slurry comprises a metal composition, a dispersion reducing agent, a composite curing agent and an optional solvent, the metal composition at least comprises copper powder and optional gold powder and / or silver powder; the composite curing agent comprises thermosetting resin and a latent curing agent; wherein the mass ratio of the metal composition to the composite curing agent is (7-30): 1. The copper electrode paste provided by the invention replaces expensive silver paste, so that the manufacturing cost of a solar cell energy electrode is greatly reduced. According to the method for preparing the metal electrode, the position of the copper electrode can be precisely machined, damage to the amorphous silicon layer is avoided, remelting and solidification of the copper electrode are achieved through multiple times of laser scanning, and the problem that the adhesive force between the copper electrode and the substrate is poor is effectively solved.

The invention provides a tungsten and titanium nitride / titanium selective etching solution which comprises the following components in percentage by mass: 5%-30% of an oxidizing agent, 0.5%-10% of an alkaline etching agent, 0.1%-1% of a tungsten corrosion inhibitor, 0.01%-0.05% of a surfactant and the balance of deionized water. According to the etching solution disclosed by the invention, the etching on W can be reduced while the high etching rate of TiN / Ti is maintained.

The invention relates to the technical field of semiconductor devices, and particularly discloses a film bulk acoustic resonator and a preparation method thereof, and the film bulk acoustic resonator comprises a substrate, and a lower electrode, a piezoelectric layer, an upper electrode and a passivation layer which are stacked on the substrate; the overlapped part of the projections of the lower electrode, the piezoelectric layer and the upper electrode on the substrate is an active area; a compensation layer is further formed on the piezoelectric layer, a hollow groove is formed in the compensation layer, and the hollow groove is formed along the projection edge of the active area, so that the passivation layer collapses at the position covering the hollow groove to form a groove. Through the hollow design of the compensation layer, a groove is naturally formed in the surface of the passivation layer above the compensation layer, and the manufacturing yield is effectively improved.

The invention belongs to the field of batteries, and particularly relates to a phosphoryl isocyanate additive, a preparation method of the phosphoryl isocyanate additive, an electrolyte, the additive and a lithium ion battery. The structure of the phosphoryl isocyanate additive is shown as the following formula (A): # imgabs0 #, R1 is one of alkyl, alkoxy, phenoxyl, alkenyl, alkynyl, phenyl and substitutes thereof with the carbon atom number of 1-6, and R2 is one of isocyanate, alkyl, alkenyl, alkynyl, phenyl and substitutes thereof with the carbon atom number of 1-6. By adding a small amount of phosphoryl isocyanate additive into the electrolyte, a CEI structure which is relatively low in resistance and stable under a high-voltage condition is formed on the surface of a positive electrode, so that the rate capability and the high-voltage cycle stability of the battery can be improved.

The utility model provides a wire structure. The wire structure comprises a first dielectric layer; the seed layer is arranged on the first dielectric layer; the conductive trace is arranged on the upper surface, deviating from the first dielectric layer, of the seed layer; and the second dielectric layer covers the conductive trace and is in contact with the upper surface of the seed layer. In the prior art, in the wet etching process of a seed layer, an etching solution etches a conductive trace at the same time, so that the conductive trace is thinned, and the bending strength of the conductive trace is easily reduced and even broken, the photoresist is used as a protective layer before etching, the conductive trace is separated from the etching solution, and the conductive trace is prevented from being damaged. Therefore, when the seed layer is etched, the conductive traces are not etched, the conductive traces are prevented from being thinned, the bending strength of the conductive traces is ensured, the normal work of the whole lead structure is ensured, and the problems of open circuit and the like are avoided.

The present invention relates to a thin film bulk acoustic wave resonator and a manufacturing method thereof, wherein the thin film bulk acoustic wave resonator comprises: a first substrate provided with a first cavity; a piezoelectric laminate structure, comprising a first electrode, a piezoelectric layer and a second electrode stacked in sequence from bottom to top, the piezoelectric layer covers the first cavity, the edges of the first electrode and the second electrode are both located within the boundary of the area enclosed by the first cavity, and the effective resonance area comprises an area where the first electrode, the piezoelectric layer and the second electrode overlap each other in a direction perpendicular to the surface of the piezoelectric layer; a first electrode lead-out structure, connecting the edge of the first electrode and extending to the invalid resonance area as a first signal connection end, and enclosing a first gap with the piezoelectric laminate structure at the edge of the effective resonance area; a second electrode lead-out structure, connecting the edge of the second electrode and extending to the invalid resonance area as a second signal connection end, and enclosing a second gap with the piezoelectric laminate structure at the edge of the effective resonance area. The present invention improves the Q value by eliminating the boundary clutter of the effective resonance area.

This invention discloses a β-Ga₂O₃ nanowire / diamond heterostructure, its preparation method, and its applications. The method includes the following steps: dropping Ga metal droplets onto an auxiliary substrate; placing the diamond substrate and the auxiliary substrate in the same temperature zone of a tube furnace; introducing a mixed gas of H₂ and Ar into the tube furnace under negative pressure, using O₂ entering from the outside and residual O₂ in the tube furnace as the O source, and growing β-Ga₂O₃ nanowires on the diamond surface without catalysis. The method of this invention eliminates the need for additional annealing treatment and pre-laying of metal catalysts on the diamond substrate, and avoids the phenomenon of O₂ etching of the diamond substrate under high-temperature conditions. β-Ga₂O₃ nanowires are epitaxially grown on the diamond surface through the vapor deposition of Ga. This method is simple and low-cost.

The invention provides a method for growing and stripping polycrystalline diamond with low stress, the principle of the method is that the characteristic that a substrate and a transition layer are low in mismatch with the polycrystalline diamond is utilized, and meanwhile, the substrate is etched by hydrogen after the polycrystalline diamond grows by utilizing the strong etching capability of the hydrogen, so that the intervention of extra stress is avoided, and the polycrystalline fracture is reduced. Compared with the prior art, the scheme can effectively reduce the breakage of the polycrystalline diamond during stripping, and can be applied to solve the problem of low yield caused by breakage of the industrial MPCVD polycrystalline diamond.

The invention discloses a method for reducing epitaxial surface defects of silicon carbide. The aim of reducing the number of epitaxial surface defects is achieved by modifying a graphite piece of a reaction chamber of a silicon carbide epitaxial furnace. According to the method, an air flotation channel is additionally arranged on a graphite piece at the lower part of a reaction chamber, and a pressure balance hole is formed in a protective cover plate above the graphite piece at the lower part of the reaction chamber; in the SiC epitaxial growth process, the carrier gas flows to generate negative pressure near the pressure balance hole, so that the air floating gas leaves the growth area of the SiC epitaxial wafer along the air floating channel under the action of the negative pressure, and the probability that particles carried by the air floating gas fall onto the surface of the epitaxial wafer to form surface defects is reduced. And the method is compatible with a mainstream SiC epitaxial furnace and an epitaxial process, is suitable for industrial production, and has great popularization value.

The purpose of the present invention is to provide a technique capable of etching at least a film containing Si and N while suppressing etching of the film containing at least Si and O in a substrate having a film containing at least Si and O and a film containing at least Si and N. The present invention is an etching method for etching a film containing Si and N by bringing a substrate having a film containing at least Si and O and a film containing at least Si and N into contact with (I) HF gas and (II) at least one compound selected from the group consisting of sulfonyl compounds, carbonyl compounds, sulfonyl isocyanate compounds, and isocyanate compounds.

A 3D memory and a manufacturing method thereof, and an electronic device, the manufacturing method of the 3D memory comprising: forming a barrier layer on the inner wall of a trench by using an atomic deposition process, at least part of the barrier layer covering the exposed side walls of a plurality of branches; forming an insulating dielectric film on the barrier layer, adopting an oxidation process to enable the insulating dielectric film to form an oxidized insulating dielectric layer and enable the barrier layer to be oxidized to form an oxidized barrier layer, and enabling the oxidized insulating dielectric layer and the oxidized barrier layer to form an insulating dielectric layer; removing the insulating dielectric layer on one side, far away from the bit line, of the plurality of branches by adopting an etching process to form a first groove extending along the direction vertical to the substrate; depositing a supporting material film filling the first groove; respectively etching the support material film and the insulating dielectric layer by adopting different patterning etching processes, so that the support material film on one side, far away from the bit line, of each branch forms a support structure; the supporting structure is prevented from being etched, and the strength of the supporting structure is ensured.

The invention discloses a preparation method of an electronic device and the electronic device, relates to the technical field of microelectronics, and can improve the reliability of the electronic device. The preparation method of the electronic device comprises the following steps: sequentially arranging a first dielectric layer and a second dielectric layer on one side of a silicon wafer; arranging photoresist on one side, far away from the silicon wafer, of the second dielectric layer, and performing graphical processing on the photoresist by utilizing a photoetching process so as to form a first via hole in the photoresist; the second dielectric layer is etched through the first via hole, so that a second via hole is formed in the second dielectric layer, and the first via hole is communicated with the second via hole; removing the photoresist to obtain a transition substrate; performing ozone cleaning on the transition substrate at least once to remove organic matters on the surface of the transition substrate and in the second via hole; and / or carrying out at least one time of acid cleaning on the transition substrate to remove organic matters on the surface of the transition substrate and in the second via hole; and carrying out deionized water cleaning on the transition substrate at least once.

The purpose of the present invention is to provide a detergent which is capable of suppressing etching of copper and removing organic substances or copper oxides adhering to the surface of copper wiring. The cleaning agent comprises water-soluble carboxylic acid and hydrogen peroxide, the concentration of the hydrogen peroxide is less than 0.75 wt%, and the pH value of the cleaning agent is less than 2.5. Copper oxide can be removed from the surface of the copper wiring by the water-soluble carboxylic acid. Organic matter adhering to the surface of the copper wiring can be removed by the hydrogen peroxide. The reason for this is that hydrogen peroxide reacts with a water-soluble carboxylic acid in the cleaning agent, thereby generating a peroxycarboxylic acid. Etching of copper wiring can also be suppressed. The reason is that the water-soluble carboxylic acid is adsorbed on the copper surface. In addition, etching can be further suppressed due to less than 0.75 wt%. And the pH value does not reach 2.5, so that the copper oxide can be further removed.

The application discloses a deep-groove polysilicon etching solution, which comprises an oxidizing agent, an inorganic acid, a pH regulator and a surfactant. The deep-groove polysilicon etching solution can efficiently etch polysilicon while ensuring the uniformity and smoothness of the etching surface, and can maximize the consistency of the etching of the upper and lower grooves and the smoothness of the surface. In the etching process, the inorganic acid ensures that the etching solution system is in an acidic environment, and the polysilicon is etched; the pH regulator avoids the large fluctuation of the pH of the etching solution, thereby ensuring the stability of the polysilicon etching process; and the surfactant reduces the surface tension of the etching solution, improves the wettability of the etching solution, ensures the consistency of the etching rate of the upper and lower grooves, and ensures the consistency of the groove aperture.

The invention discloses a process method for eliminating an antenna effect of a power device with an ESD (Electro-Static Discharge) structure, which comprises the following steps of: after etching a polycrystalline silicon grid of the power device, depositing to form a silicon nitride layer; forming an ESD (Electro-Static Discharge) oxide layer on the silicon nitride layer, and depositing a polycrystalline silicon layer on the ESD oxide layer; performing ion implantation of the ESD structure; carrying out photoetching and etching on the polycrystalline silicon layer of the ESD structure, completing pattern formation of the polycrystalline silicon structure in the ESD structure, and then carrying out thermal annealing; carrying out a wet etching process of the ESD oxide layer, and removing the redundant ESD oxide layer; removing the silicon nitride layer by a wet etching process; and performing body region injection of the power device. SiN is introduced to serve as a barrier layer for wet etching of the ESD oxide layer, the antenna effect caused by ESD OX local over-etching can be effectively prevented, the convergence of BV voltage resistance and IDSS electric leakage is improved, and the occurrence probability of low product yield can be remarkably reduced.

The application discloses a fluorine-containing silicon nitride etching solution, which comprises phosphoric acid, a fluorine-containing compound, an aluminum oxide etching inhibitor, a tungsten etching inhibitor, a silicon oxide etching inhibitor and deionized water. The etching solution can realize selective etching of silicon nitride to silicon oxide, aluminum oxide and tungsten in hot phosphoric acid, while inhibiting etching of the silicon oxide, and the etching rate of the silicon nitride is more stable at high temperature than that of a phosphoric acid / hydrofluoric acid system due to the complexing and slow-release effect of the fluorine-containing compound.

The present invention provides a method for manufacturing a semiconductor structure, which is applied to the technical field of manufacturing capacitor contact nodes of a memory, and the method at least includes: forming a plurality of bit line structures on a substrate; forming a plurality of dielectric walls on the substrate, wherein the upper surface of the dielectric walls is higher than the upper surface of the bit line structures, and the dielectric walls extend to cover the portions overlapping with the bit line structures; manufacturing an insulating structure in a capacitor storage node window surrounded by the bit line structures and the dielectric walls to form a separated capacitor storage node window; depositing a conductive material layer in the separated capacitor storage node window; etching back the conductive material layer to form a capacitor contact node structure on both sides of the insulating structure. And a semiconductor structure is provided. By applying the embodiments of the present invention, the yield of the capacitor contact node structure is improved, thereby avoiding the problem in the prior art that a thicker polysilicon layer between storage nodes is etched, resulting in the easy deviation of the etched pattern, thereby affecting the conductive characteristics of the circuit.

The application relates to the field of optical communication technology, and particularly discloses a one-way coupling vertical grating coupler implementation method based on topological photonics; the method is based on an SOI platform, first, the size parameters of a uniform grating coupler are modeled and optimized; a single-etching rectangle in the grating is replaced by double-adjacent-rectangle etching to form a stepped structure, the up-down symmetry of the grating is destroyed, and the downward radiation is inhibited and the upward coupling is strengthened relying on the topological one-way coupling resonance principle; a super-Gaussian chirp function is introduced to modulate the etching width, the central period index, the envelope width and the super-Gaussian order are optimized, and the fiber mode field is matched; meanwhile, a waveguide and grating differential height design is adopted to expand the optimization space. The application does not need a DBR mirror and can be prepared only by surface etching, so the process is simplified; the grating to single-mode fiber coupling efficiency reaches 83.7%, the 3dB bandwidth is more than 79nm, and the application has the advantages of high coupling efficiency, wide bandwidth and high process fault tolerance.

The present application provides a three-dimensional memory and a method for preparing the same. The method includes: providing a semiconductor structure, including a substrate, a conductive gate layer stacking structure, a top selection gate layer stacking structure, and a dielectric layer stacked in sequence; wherein a channel structure is formed in the core region of the semiconductor structure, and the top selection gate layer and the plug at one end of the channel structure away from the substrate are made of the same type of material; using a first mask plate to form a first through hole in the dielectric layer that stops at the plug of the channel structure by etching, and forming a second through hole of the top selection gate layer that stops at the top selection gate step in the dielectric layer corresponding to the top selection gate step; using a second mask plate to form a third through hole of the conductive gate layer that stops at the conductive gate step in the dielectric layer corresponding to the conductive gate step by etching. The method uses a mask plate to form the first through hole and the second through hole through a single etching process, which can reduce the manufacturing process and save production costs.

The invention discloses a BOE etching solution with a high silicon oxide / silicon nitride selection ratio, and the BOE etching solution comprises the following components in percentage by mass: 2%-20% of hydrofluoric acid, 17%-20% of ammonium fluoride, 0.01%-0.5% of an additive, 0.003%-0.3% of a defoaming agent and the balance of ultrapure water. The additive is aromatic aldehyde, so that the selection ratio of silicon oxide to silicon nitride can be effectively improved; the defoaming agent is used for improving foam and uniformly dispersing aromatic aldehyde in the BOE etching solution, so that the uniformity of the solution is ensured. The BOE etching solution in the invention can ensure that the silicon nitride layer is less etched, and plays a role in improving the selection ratio of silicon oxide / silicon nitride.

The present invention provides a semiconductor device and a method for forming the same. The semiconductor device includes a semiconductor substrate, a first dielectric layer is arranged on the semiconductor substrate, the first dielectric layer includes a first region, a groove is arranged in the first dielectric layer, a MIM capacitor is formed on the inner wall of the groove, the MIM capacitor covers the first dielectric layer of the first region, a second dielectric layer is arranged on the first dielectric layer, and the second dielectric layer covers the MIM capacitor. Compared with a planar MIM capacitor formed only on the surface of the first dielectric layer, a MIM capacitor with a larger specific surface area can be obtained by the groove in the same region. If an insulating layer of the same material is used, a larger specific capacitance density per unit area can be obtained or the area occupied by the MIM capacitor can be reduced to match the device requirements and improve the integration; if a groove-shaped structure is used, the capacitance density per unit area can be significantly increased, avoiding the use of additional special equipment for deposition and etching of high dielectric materials, and reducing the process cost.

The present invention discloses a method for manufacturing a resonator and a resonator, wherein the manufacturing method comprises: sequentially stacking a first electrode layer, a piezoelectric layer, and a second electrode layer. A support layer is manufactured on the surface of the second electrode layer on the side away from the piezoelectric layer, the support layer comprising a plurality of first protrusions arranged at intervals, and a first recessed portion is formed between adjacent first protrusions. A cutoff boundary layer is manufactured to cover the surface of the first protrusion on the side away from the piezoelectric layer and the wall surface of the first recessed portion. A plurality of second notches penetrating the first electrode layer are manufactured on the first electrode layer, and the second notches divide the first electrode layer into a plurality of first electrodes. A plurality of grooves penetrating the piezoelectric layer are manufactured on the piezoelectric layer, and the plurality of grooves divide the piezoelectric layer into a plurality of piezoelectric bodies, and the second electrode is exposed in the grooves; a barrier layer is manufactured, and the barrier layer at least covers the bottom of each groove; and at least two first protrusions are removed so that the second electrode and the cutoff boundary layer form at least two cavities.

The invention relates to a polycrystalline silicon etching solution, which is prepared from the following components in percentage by mass: 0.1 to 2.38 percent of quaternary ammonium salt compounds, 1 to 40 percent of alcohol amine compounds, 1 to 40 percent of polyhydric alcohol compounds, 0.1 to 2 percent of etching accelerant and the balance of deionized water. The sum of the parts by weight of the components is 100%. The alcohol amine compound and the polyhydric alcohol compound have a synergistic effect, so that the etching rate of SiO2 can be effectively reduced; the etching accelerator can improve the etching rate of the polycrystalline silicon, improve the etching uniformity and improve the surface roughness of the polycrystalline silicon.

The invention discloses a fluorine-containing silicon nitride etching solution. The etching solution comprises phosphoric acid, a fluorine-containing compound, an aluminum oxide etching inhibitor, a tungsten etching inhibitor, a silicon oxide etching inhibitor and deionized water. The etching solution can realize selective etching of silicon nitride, silicon oxide, aluminum oxide and tungsten in hot phosphoric acid and inhibit etching of silicon oxide at the same time, and the etching rate of silicon nitride is more stable than that of a phosphoric acid / hydrofluoric acid system at a high temperature due to the complexing slow-release effect of the fluorine-containing compound.

The invention provides an MZ type electro-optical modulator and a preparation method thereof. The MZ type electro-optical modulator comprises a substrate layer, a silicon waveguide layer, a first isolation layer, a silicon nitride waveguide layer, a second isolation layer, a lithium niobate film layer, a third isolation layer and a metal layer from bottom to top. The surface of the substrate layer is an insulating material layer; the silicon waveguide layer comprises a beam splitter and a beam combiner which are positioned on two opposite sides, and more than two modulation arms which are respectively connected with the beam splitter and the beam combiner and oppositely extend to corresponding coupling areas; a mixed waveguide formed by a silicon nitride strip-shaped waveguide of the silicon nitride waveguide layer and a lithium niobate thin film layer located on the upper layer of the silicon nitride strip-shaped waveguide serves as an active modulation arm, and the thickness of a second isolation layer located between the silicon nitride waveguide layer and the lithium niobate thin film layer is smaller than 50 nm. According to the invention, the performance of the modulator is improved, the transmission loss is reduced, the preparation process is simplified, the preparation cost is reduced, and large-scale popularization and application of the modulator are facilitated.

The present invention provides a p-GaN HEMT device and a preparation method, a substrate layer; a buffer layer arranged on the substrate layer, a side of the buffer layer away from the substrate layer is provided with a P-type doping region; a channel layer arranged on the buffer layer, the channel layer is in contact with the P-type doping region; a barrier layer, a source electrode and a drain electrode arranged on the channel layer, the source electrode and the drain electrode are arranged on both sides of the barrier layer; a heat dissipation layer arranged on the barrier layer; a cap layer arranged on the barrier layer and on the heat dissipation layer; a passivation layer arranged on the heat dissipation layer, the passivation layer is arranged between the source electrode and the cap layer and between the drain electrode and the cap layer; a gate electrode arranged on the cap layer. The beneficial effects of the present invention are that the number of defects and the interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, the influence of interface reaction and defects on the working performance of the device can be reduced, the electric field at the 2DEG channel can be effectively modulated, the thermal management capability of the device itself can be improved, and the stability and reliability of the device operation can be improved.

The present invention relates to a method for preventing undercut etching of the sidewall of a three-dimensional microstructure in a microelectronic mechanical manufacturing process, belonging to the field of microelectronic mechanical system manufacturing technology, comprising firstly, depositing a conformal film layer as a protective layer on the surface of a wafer substrate having generated a three-dimensional microstructure by an LPCVD process; then, removing the conformal film layer at the area not requiring protection by dry etching, and performing subsequent wet / vapor phase etching, wherein the conformal film layer can form a dense and uniformly covered protective layer on the surface, sidewall, bottom and any narrow corner of the etched three-dimensional microstructure to prevent the invasion of corrosive substances; finally, after the subsequent wet / vapor phase etching is completed, the conformal film layer is removed by ordinary dry etching technology. The present invention has strong protectiveness and reliable effect, can effectively prevent the occurrence of undercut etching in subsequent hydrofluoric acid wet etching or vapor phase etching, and improve the performance of waveguide devices.

The present invention relates to a modified aminosilane copolymer, a silicon nitride etching solution, a preparation method and an application. The copolymer has three alkoxy groups connected to Si atoms and easily hydrolyzed, and the groups can be hydrolyzed under acidic conditions to generate Si-OH bonds, and the Si-OH bonds can be tightly combined with a silicon dioxide layer through van der Waals forces to adhere to and wrap the silicon dioxide layer. The silicon nitride etching solution components include a modified aminosilane copolymer, concentrated phosphoric acid and ultrapure water. The silicon nitride etching solution of the present invention can maintain a high etching selectivity ratio for both silicon dioxide and polysilicon, and can be applied in the field of silicon nitride etching of 3D flash memory chips.