Horizontal gate all around nanowire transistor bottom isolation

Abstract

A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.

Description

TECHNICAL FIELD[0001]The present invention relates to semiconductor devices and methods of fabricating the same. More specifically, the invention relates to various methods of forming nanowire channels in gate-all-around (GAA) MOSFETs.BACKGROUND[0002]With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, conventional planar metal-oxide-semiconductor field effect transistors (MOSFETs) face increasing challenges with such issues as scaling of gate oxide thickness and electrostatic control of the gate electrode over the channel region. Fin field effect transistors (FinFETs) have exhibited improved control over a planar gate MOSFET design by wrapping the gate electrode over three sides of a fin-shaped channel.[0003]GAA MOSFETs are similar to FinFETs but have the potential of even greater electrostatic control over the channel because the gate electrode completely surrounds the channel. In a GAA MOSFET,...

AI Technical Summary

Benefits of technology

[0008]The present invention offers advantages and alternatives over the prior art by providing a GAA MOSFET and methods of making the same, wherein the MOSFET includes an etch stop-electric well (ESEW) layer disposed over a substrate. The ESEW layer functions as an etch stop barrier to prevent etching of trenches in the substrate during an etching removal process of any sacrificial layers when making the MOSFET. The ESEW layer additionally provides an electric barrier against potential shorts across the gate dielectric by providing an additional p-n or n-p barrier at the common boundary between ESEW layer and substrate.

[0009]A method of making a GAA MOSFET in accordance with one or more aspects of the present invention includes providing a substrate having source, drain and channel regions for a GAA MOSFET, the substrate being doped with one of a p-type and an n-type dopant. An etch stop-electric well (ESEW) layer is then disposed over the substrate, the ESEW layer is doped with the other of the p-type and the n-type dopant. A sacrificial layer is disposed over the ESEW layer, the sacrificial layer is doped with the same type dopant as the substrate. A channel layer is disposed over the sacrificial layer. The method further includes patterning a fin out of the ESEW layer, sacrificial layer, and channel layer in the channel region. Additionally the method includes selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.

Problems solved by technology

With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, conventional planar metal-oxide-semiconductor field effect transistors (MOSFETs) face increasing challenges with such issues as scaling of gate oxide thickness and electrostatic control of the gate electrode over the channel region.

Problematically however, it is difficult to control the inadvertent etching of the recessed trenches under the nanowire channels.

This uncontrolled etch introduces trench to trench variations and an undesired roughness at the bottoms of the trenches, which can detrimentally affect device performance.

Additionally, the thin gate dielectric deposition does not always sufficiently isolate the metal gate from the substrate, which can lead to shorts across the gate dielectric from electrode to substrate.

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