9 results about "Nanowire transistors" patented technology

Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

A semiconductor device includes a plurality of nanostructured transistor layers in a stacked or vertical configuration. Each nanostructure transistor layer comprises at least one n-type metal oxide semiconductor nanostructure transistor and at least one p-type metal oxide semiconductor nanostructure transistor. Nanostructure transistor layers may be fabricated such that n-type metal oxide semiconductor nanostructure transistors and p-type metal oxide semiconductor nanostructure transistors of two or more nanostructure transistor layers have one or more different characteristics, such as the number of nanostructure channels. This can optimize the performance of n-type metal oxide semiconductor nanostructured transistors and p-type nanostructured transistors of different nanostructured transistor layers for different performance parameters.

A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and / or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Semiconductor devices and methods of forming semiconductor devices are disclosed herein, and more particularly to semiconductor devices including wrap-around gate transistor structures and methods of manufacturing the same. Methods described herein can etch a complex shape (e.g., L-shaped) into a multi-layer stack to form a fin for an active region of a wrap-around gate nanowire transistor structure. In some embodiments, the active region can have a first source / drain region with a first channel width and a first width, and a second source / drain region with a second channel width and a second width that is less than the first width.

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

The application provides a preparation method of a stretchable polymer nanowire transistor and photoelectric application thereof, and belongs to the field of stretchable electronic devices. The transistor adopts a bottom gate top contact or bottom gate bottom contact structure, is composed of a stretchable substrate, a gate, an insulating layer, a semiconductor layer and source-drain electrodes, and the semiconductor layer is a polymer nanowire prepared by coaxial fluid jet printing of a conjugated polymer and elastomer polymer blended solution. The method realizes preparation of nanowires with high stretchability and high orientation, so that the semiconductor layer has excellent stretchability and electrical properties. Through horizontal and vertical integration, a stretchable complementary inverter and a visual self-adaptive device are constructed, and the advantages of multifunctional integration are exhibited. The application has wide application prospects in the development of miniaturized, highly integrated wearable electronic devices and multifunctional neural interfaces.