35 results about "Nanowire transistors" patented technology

The invention belongs to the technical field of semiconductor devices, and particularly relates to a high-heat-dissipation GaN nanowire radio frequency device and a preparation method thereof.The radio frequency device comprises a heterogeneous bonding substrate, a bonding middle layer, an AlGaN / GaN nanowire (a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a GaN cap layer), a passivation layer and an electrode layer, and the electrode layer comprises a source electrode, a gate electrode and a drain electrode; the passivation layer covers the gaps between the nanowires through front deposition, so that the preparation of the high-heat-dissipation nanowire transistor is realized, and the problem that the linearity of the device is reduced due to a self-heating effect is solved; holes are formed in the grid electrode, the thickness of the passivation layer on each nanowire is controlled, equal difference distribution is achieved, the linearity of the device is improved through the transconductance compensation effect, the grid voltage swing of the radio frequency device can be effectively improved, and therefore the available range of the device is greatly widened.

A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

Structures with staggered backside interconnections are described. In one example, an integrated circuit structure includes a frontside structure including a device layer having a plurality of nanowire-based transistors or a plurality of fin-based transistors, and a plurality of metallization layers above the plurality of nanowire-based transistors or the plurality of fin-based transistors of the device layer. A backside structure is located below the plurality of nanowire-based transistors or the plurality of fin-based transistors of the device layer. The backside structure includes a metallization layer with staggered backside interconnections.

A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

Structures having staggered backside interconnects are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of nanowire-based transistors or a plurality of fin-based transistors, and a plurality of metallization layers above the plurality of nanowire-based transistors or the plurality of fin-based transistor of the device layer. A backside structure is below the plurality of nanowire-based transistors or the plurality of fin-based transistor of the device layer. The backside structure includes a metallization layer having staggered backside interconnects.

Structures having bidirectional backside interconnects are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of nanowire-based transistors or a plurality of fin-based transistors, and a plurality of metallization layers above the plurality of nanowire-based transistors or the plurality of fin-based transistor of the device layer. A backside structure is below the plurality of nanowire-based transistors or the plurality of fin-based transistor of the device layer. The backside structure includes a metallization layer having bidirectional backside interconnects, the bidirectional backside interconnects including a first set of conductive lines along a first direction and a second set of conductive lines along a second direction orthogonal to the first direction.

Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.

Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

A semiconductor device includes a plurality of nanostructured transistor layers in a stacked or vertical configuration. Each nanostructure transistor layer comprises at least one n-type metal oxide semiconductor nanostructure transistor and at least one p-type metal oxide semiconductor nanostructure transistor. Nanostructure transistor layers may be fabricated such that n-type metal oxide semiconductor nanostructure transistors and p-type metal oxide semiconductor nanostructure transistors of two or more nanostructure transistor layers have one or more different characteristics, such as the number of nanostructure channels. This can optimize the performance of n-type metal oxide semiconductor nanostructured transistors and p-type nanostructured transistors of different nanostructured transistor layers for different performance parameters.

A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

A semiconductor device may include a substrate and spaced apart gate stacks on the substrate, the gate stacks defining respective trenches therebetween. Each gate stack may include alternating layers of a first semiconductor material and a second semiconductor material, wherein the layers of the second semiconductor material define a nanostructure. The semiconductor device may also include respective source / drain regions within the trenches, respective insulating regions adjacent lateral ends of the layer of first semiconductor material, and respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outward from adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include a plurality of stacked sets of layers, wherein each set of layers includes a stacked base semiconductor monolayer defining a base semiconductor portion and at least one non-semiconductor monolayer confined within a lattice of an adjacent base semiconductor portion.

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and / or claimed.

The invention discloses a semiconductor device and a forming method thereof. A source / drain region of a nanostructured transistor of a semiconductor device is formed such that a cavity extends from a top of the source / drain region into the source / drain region. In some implementations, the cavity extends completely through a depth of the source / drain region. The cavity is created by a partial epitaxial growth of one or more epitaxial layers of the source / drain region. A metal core of a source / drain region is formed in the cavity, and the metal core is electrically coupled to a source / drain contact of the nanostructured transistor such that the conductive material is recessed within the source / drain region. This provides a greater amount of surface area for the source / drain contact to contact the source / drain region than if the source / drain region is completely filled with an epitaxially grown semiconductor material.

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and / or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and / or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

The invention relates to a semiconductor device and a forming method thereof. Source / drain contacts of the nanostructured transistor are formed such that the source / drain contacts are recessed within an underlying source / drain region of the nanostructured transistor using a multi-step etch process. Recessing the source / drain contact within the source / drain region provides a greater amount of surface area for the source / drain contact to contact the source / drain region. This provides an increased contact surface area between the source / drain contact and the source / drain region, and due to a less limited current flow path between the source / drain region and the source / drain contact, the increased contact surface area provides a reduced contact resistance between the source / drain region and the source / drain contact. In this manner, a reduced contact resistance between the source / drain region and the source / drain contact enables greater power efficiency for nanostructured transistors.

Semiconductor devices and methods of forming semiconductor devices are disclosed herein, and more particularly to semiconductor devices including wrap-around gate transistor structures and methods of manufacturing the same. Methods described herein can etch a complex shape (e.g., L-shaped) into a multi-layer stack to form a fin for an active region of a wrap-around gate nanowire transistor structure. In some embodiments, the active region can have a first source / drain region with a first channel width and a first width, and a second source / drain region with a second channel width and a second width that is less than the first width.

A method includes patterning stacked layers to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures located alternatingly. The second multi-layer stack is wider than the first multi-layer stack. A nanosheet transistor is formed based on the first multi-layer stack. The nanosheet transistor includes first channel regions having a first width, and a first gate stack on the first channel regions. A nanowire transistor is formed based on the second multi-layer stack. The nanowire transistor includes second channel regions narrower than the first channel regions, and a second gate stack on the second channel regions.

A method includes patterning stacked layers to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures located alternatingly. The second multi-layer stack is wider than the first multi-layer stack. A nanosheet transistor is formed based on the first multi-layer stack. The nanosheet transistor includes first channel regions having a first width, and a first gate stack on the first channel regions. A nanowire transistor is formed based on the second multi-layer stack. The nanowire transistor includes second channel regions narrower than the first channel regions, and a second gate stack on the second channel regions.

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

A nanowire transistor and a method for fabricating the same are disclosed. The method for fabricating the nanowire transistor includes forming a channel structure on a substrate, wherein the channel structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a gate structure on the channel structure, and forming a source / drain structure beside the gate structure, wherein the source / drain structure includes graphene.

A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source / drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source / drain structure. Preferably, the source / drain structure includes graphene and the contact plug further includes a silicide layer on the source / drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

This invention discloses an integration method for asymmetric stress-distributed vertical-channel nanowire transistors, belonging to the field of very large-scale integrated circuit manufacturing technology. This invention designs the source / drain materials and channel materials separately, effectively applying uniaxial stress in the channel. By adjusting the magnitude and distribution of this stress, complementary drive currents are achieved for N / P type devices. Simultaneously, this invention effectively improves the hole mobility and on-state current of P-type MOSFETs. The vertical nanowire devices can achieve discrete source / drain fabrication in the manufacturing process, providing greater flexibility for adjusting device characteristics.

A semiconductor device may include a substrate and spaced apart gate stacks on the substrate, the gate stacks defining respective trenches therebetween. Each gate stack may include alternating layers of a first semiconductor material and a second semiconductor material, wherein the layers of the second semiconductor material define a nanostructure. The semiconductor device may also include respective source / drain regions within the trenches, respective insulating regions adjacent lateral ends of the layer of first semiconductor material, and respective dopant blocking superlattices adjacent lateral ends of the nanostructures and flush with adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include stacked sets of layers, wherein each set of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer confined within a lattice of an adjacent base semiconductor portion.

The application belongs to the technical field of semiconductor devices, and particularly relates to a high-heat-dissipation GaN nanowire radio frequency device and a preparation method thereof. The radio frequency device comprises a heterojunction bonding substrate, a bonding intermediate layer, an AlGaN / GaN nanowire (a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a GaN cap layer), a passivation layer and an electrode layer. The electrode layer comprises a source electrode, a gate electrode and a drain electrode. The passivation layer is prepared by front deposition and covers the nanowires and the gaps between the nanowires, so that the preparation of the high-heat-dissipation nanowire transistor is realized, and the linearity reduction of the device caused by the self-heating effect is solved. The gate is opened, the thickness of the passivation layer on each nanowire is controlled, the equal-difference distribution is realized, the linearity of the device is improved by using the transconductance compensation effect, the gate voltage swing of the radio frequency device can be effectively improved, and the usable range of the device is greatly enhanced.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

The application provides a preparation method of a stretchable polymer nanowire transistor and photoelectric application thereof, and belongs to the field of stretchable electronic devices. The transistor adopts a bottom gate top contact or bottom gate bottom contact structure, is composed of a stretchable substrate, a gate, an insulating layer, a semiconductor layer and source-drain electrodes, and the semiconductor layer is a polymer nanowire prepared by coaxial fluid jet printing of a conjugated polymer and elastomer polymer blended solution. The method realizes preparation of nanowires with high stretchability and high orientation, so that the semiconductor layer has excellent stretchability and electrical properties. Through horizontal and vertical integration, a stretchable complementary inverter and a visual self-adaptive device are constructed, and the advantages of multifunctional integration are exhibited. The application has wide application prospects in the development of miniaturized, highly integrated wearable electronic devices and multifunctional neural interfaces.

The invention provides a memory cell with a back coupled ferroelectric capacitor. The memory cell comprises a substrate, a vertical nanowire transistor and a ferroelectric capacitor. Wherein the drain electrode of the vertical nanowire transistor and the nanowire channel are formed on the first side of the substrate, a grid electrode with an annular grid structure is formed around the nanowire channel, and the source electrode of the vertical nanowire transistor extends from the nanowire channel to the second side of the substrate; and the ferroelectric capacitor is formed on the second side of the substrate, and a first pole plate of the ferroelectric capacitor is electrically connected with the source electrode, so that nonvolatile data storage is realized by changing the polarization state of a ferroelectric layer of the ferroelectric capacitor under the condition that the nanowire channels are communicated.