Nanowire transistor and forming method thereof

Abstract

The invention provides a nanowire transistor and a forming method thereof, wherein the forming method comprises the following steps of: providing a substrate; Forming a composite structure on the substrate, the composite structure comprising one or more laminated composite layers, the composite layers comprising a sacrificial layer on the substrate and a channel layer on the sacrificial layer, thechannel layer and the sacrificial layer being different in material; Etching a sacrificial layer of the side wall of the composite structure to form a depression on the surface of the side wall of the composite structure; Forming an isolation layer on the surface of the sacrificial layer exposed by the recess; Forming a source-drain doping layer on a substrate on both sides of the composite structure after forming the isolation layer, wherein the isolation layer is provided between the source-drain doping layer and the sacrificial layer; Removing the remaining sacrificial layer after the source-drain doping layer is formed; Forming a gate structure surrounding the channel layer. The resulting transistor reduces parasitic capacitance and improves transistor performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a nanowire transistor and a forming method thereof. Background technique [0002] With the development of semiconductor technology, the feature size of semiconductor devices is not much reduced. After the device size enters the deep submicron size, the short channel effect becomes an obstacle to the continuous miniaturization of traditional planar transistors. This stems from a decrease in gate control capability coupled with an increasing influence of the drain on the bulk potential. [0003] Nanowire transistors (NWFETs) promise to solve this problem. On the one hand, the small channel thickness and width make the gate of the nanowire transistor closer to each part of the channel, which helps to enhance the gate capability of the transistor, and most of the nanowire transistors adopt a gate-enclosed structure, and the gate is viewed from all directions. M...

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Problems solved by technology

[0004] However, the distance between the gate and the source-drain doped layer of the nanowire transistor formed in the prior art is small, resulting in a large parasitic capacitance between the gate and the source-drain doped layer, which makes the performance of the nanowire transistor relatively low. Difference

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