781 results about "Isolation layer" patented technology

The invention relates to a current sensor chip packaging structure and a packaging method. The current sensor chip packaging structure comprises a bus frame and a chip which are packaged through a plastic package body, the side, provided with the chip bonding pad, of the chip is defined as the front face of the chip, only one side of the front face is configured to be opposite to the back face of the bus frame, the chip bonding pad is arranged on the other side, extending out of the bus frame, of the front face, and a sensor element is arranged on the side, right opposite to the bus frame, of the front face of the chip. A gap between the chip and the bus frame is provided with an isolation layer, and the front surface is connected to the back surface of the bus frame through the isolation layer. According to the current sensor chip packaging structure and the packaging method, the front surface of the chip is connected to the back surface of the bus frame through the isolation layer, and the sensor element is arranged at the position opposite to the front surface of the chip, so that the distance between the sensor element and the bus frame is minimized, and the reliability of the current sensor chip is improved by minimizing the distance between the sensor element and the bus frame. Sensitivity and measurement precision of the sensor are remarkably improved, and the problems of reduction of isolation voltage endurance capability and process fluctuation are avoided.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

Acoustic sensor systems with different heights, as well as methods for configuring and operating such sensor systems are disclosed. In some embodiments, a sensor system described herein may include an acoustic transmitter element; and an acoustic receiver element; wherein the first portion of the piezoelectric material of the acoustic transmitter element comprises a first thickness, and the second portion of the piezoelectric material of the acoustic receiver element comprises a second thickness different from the first thickness; and wherein the isolation layer is structured to create a gap that physically separates the first portion of the second electrode layer from the second portion of the second electrode layer.

The invention provides a back contact solar cell and a photovoltaic module, the back contact solar cell comprises a substrate, the substrate is provided with a backlight surface, and the backlight surface comprises a first polarity area, a second polarity area and an isolation area arranged between the first polarity area and the second polarity area; a first doped layer and a second doped layer, the first doped layer is arranged in the first polarity region, the second doped layer is arranged in the second polarity region, and the doping types of the first doped layer and the second doped layer are opposite; the isolation layer is arranged in the isolation region, the isolation layer comprises an intrinsic polycrystalline silicon layer, a first passivation layer and a third doping layer which are sequentially stacked in the direction away from the substrate, and the doping type of the third doping layer is the same as that of the first doping layer or the second doping layer. The main isolation effect is achieved through the intrinsic polycrystalline silicon layer, the composite passivation effect can be achieved through combination of the first passivation layer and the third doping layer, composite passivation with chemical passivation and field passivation is achieved in the isolation area, and the surface recombination rate is greatly reduced.

The invention discloses an anti-embrittlement flexible armored cable in an extremely cold environment. The anti-embrittlement flexible armored cable comprises a conductor, an insulating layer, a buffer isolation layer, a flexible armored layer and an outer sheath layer which are sequentially arranged from inside to outside. According to the armored cable, the structure of an existing cable is improved, the material formula of the insulating layer and the material formula of the outer sheath layer are optimized, the requirements for embrittlement resistance and high flexibility can be met, the protection performance of the armored cable can be enhanced, and aging tests show that the cable has good flexibility. The cable can meet the use requirement of long-term stable operation under the extremely cold severe condition with the temperature of-60 DEG C, has important practical significance and economic value, is reasonable in design, and is worthy of popularization and use.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a source / drain opening extending through of a fin-shaped active region that comprises a plurality of channel layers interleaved by a plurality of sacrificial layers, replacing the plurality of sacrificial layers with a plurality of dielectric layers, recessing the plurality of dielectric layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, where a bottommost inner spacer feature of the inner spacer features is thicker than one inner spacer feature of the inner spacer features disposed over the bottommost inner spacer feature, forming an isolation layer in the source / drain opening, and forming a source / drain feature in the source / drain opening and over the isolation layer, wherein the source / drain feature is spaced apart from the isolation layer by an air gap.

The invention discloses a self-calibration flexible pressure sensing device, which comprises a first conductor and a second conductor which are in a strip-shaped, strip-shaped or linear structure and both have a piezoresistive effect. The isolating layer is arranged between the first conductor and the second conductor, and through holes or long grooves with continuous through holes are distributed in the surface of the isolating layer; and an encapsulation layer covering the first conductor and the second conductor. According to the embodiment of the invention, a dual-core layer piezoresistive structure and a through hole type isolation layer design are adopted, the dual-core layer design covers a range from small pressure to large pressure, the range limitation of a single material is broken through, and a dynamic self-calibration technology is combined, so that multi-parameter integrated detection of pressure magnitude, position and width is realized; the sensor array has the advantages of self-adaption to environment change, wide-range detection, multi-scene applicability and the like, the sensor for realizing the functions only needs four wires, complex wiring of the sensor array is avoided, miniaturization and flexibility are facilitated, a narrow strip-shaped flexible structure is adopted as a whole, and flexible arrangement of sensor tracks and garment integration are facilitated.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

Acoustic sensor systems with different heights, as well as methods for configuring and operating such sensor systems are disclosed. In some embodiments, a sensor system described herein may include an acoustic receiver element; and an acoustic transmitter element; wherein the first portion of the piezoelectric material of the acoustic receiver element comprises a first thickness, and the second portion of the piezoelectric material of the acoustic transmitter element comprises a second thickness different from the first thickness; and wherein the isolation layer is structured to create a gap that physically separates the first portion of the second electrode layer from the second portion of the second electrode layer.

The invention discloses an air inlet structure, a reaction device and semiconductor thin film deposition equipment, the air inlet structure comprises a spraying plate, a temperature adjusting part and a control part, the temperature adjusting part is arranged opposite to a spraying area of the spraying plate, and the temperature adjusting part comprises a heating layer, an isolation layer and a feedback layer; the heating layer is arranged on the side, close to the spraying plate, of the isolation layer, the feedback layer is arranged on the side, away from the spraying plate, of the isolation layer, the heating layer comprises a plurality of heating units arranged in an array mode, the feedback layer comprises a plurality of temperature measuring units arranged in an array mode, and the temperature measuring units and the heating units are correspondingly arranged; and the heating layer and the feedback layer are electrically connected with the control part. Each temperature measuring unit can accurately detect the heating temperature of the corresponding heating unit, so that the control part can more accurately control the heating power of the heating units, the uniformity of temperature distribution of the spraying plate is improved, the deposition rates of a thin film in different areas of the surface of a substrate are consistent, and the uniformity of thin film deposition is improved.

The invention relates to the field of sealant materials, in particular to a rubber sleeve cable and a preparation method thereof. The rubber sleeve cable structurally comprises an inner conductor, an insulating layer, a belting layer, an isolating layer, a shielding layer and an outer sheath from inside to outside in sequence. The insulating layer comprises the following raw materials: an insulating layer matrix, a polymeric composition, a flame retardant, a reinforcing filler, a cross-linking agent, an assistant cross-linking agent and the like. The finally prepared rubber sleeve cable not only can keep excellent flexibility and mechanical strength, but also can obtain good high and low temperature resistance, effectively weakens raw material contradiction among oil resistance, weather resistance, moisture resistance, aging resistance and other characteristics, keeps a good comprehensive performance, and is suitable for popularization and application. And therefore, a good application effect can be kept in multiple application environments, and the existing higher application requirements can be met.

A semiconductor device structure is provided. The structure includes at least one sloped via formed in a via isolation layer, and at least one anti-reflection element formed on the at least one sloped via.

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure at least comprises a bottom conducting layer and a blocking part, the plane where the blocking part is located is located above the plane where the bottom conducting layer is located, and the projection of the blocking part and the projection of the bottom conducting layer in the vertical direction have an overlapping area; the three-dimensional structure comprises a first part and a second part, the top surface of the blocking part is higher than the bottom surface of the second part and lower than or flush with the bottom surface of the first part, and at least part of the first part is located over the overlapping area; the plane where the first conducting layer is located is higher than the top face of the three-dimensional structure, the contact hole is directly connected with the first conducting layer, the bottom conducting layer is electrically connected with the first conducting layer through the contact hole, and the contact hole is located in the side, away from the second part, of the first part; and the first isolation layer is used for filling areas between the contact holes and the three-dimensional structure and areas among different contact holes.

The application belongs to the technical field of photovoltaics, and provides a back contact cell, a cell module and a photovoltaic system. The back contact cell comprises a silicon substrate, a first doped layer and a second doped layer arranged on the back surface of the silicon substrate, and the doping type of the second doped layer is opposite to that of the first doped layer. The first doped layer comprises a first lightly doped part, and the second doped layer comprises a second lightly doped part. The first lightly doped part is arranged adjacent to the second lightly doped part, and the doping concentration of the first lightly doped part and the second lightly doped part is less than or equal to 1E19 / cm 3 3. A first tunneling layer arranged between the silicon substrate and the first doped layer, and a second tunneling layer arranged between the silicon substrate and the second doped layer. An isolation layer is arranged between the first lightly doped part and the second lightly doped part. The back contact cell of the application does not need to arrange a groove on the silicon substrate to isolate the first doped layer and the second doped layer, thereby avoiding the serious recombination loss caused by the groove, and being beneficial to improving the cell conversion efficiency.

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

The application discloses a transistor and a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of poor compatibility between a ring-gate transistor and another transistor with a thicker gate dielectric layer and / or gate, and to reduce the integration difficulty of the two transistors. The manufacturing method of the transistor comprises the following steps: providing a semiconductor substrate; forming an active structure and an isolation layer on the semiconductor substrate; the active structure comprises a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; the adjacent two channel layers have a first gap; the isolation layer comprises at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer form a first fin structure; and a gate stack structure is formed across the first fin structure.

Methods, devices, systems, and techniques are provided for managing contact structures in semiconductor devices. In one aspect, a semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other in a first direction. The first stack includes one or more first conductive layers and one or more first isolation layers that alternate with each other, and second conductive layers and second isolation layers that alternate with each other. The one or more first conductive layers and the one or more first isolation layers are stacked together with the second conductive layer and the second isolation layer along the first direction. The semiconductor device further includes at least one connection structure extending in the first direction through at least one of the one or more first conductive layers and connected with the at least one of the one or more first conductive layers.

This invention relates to the field of cable technology and discloses a safety early warning cable with temperature sensing. The cable includes a wrapping layer containing multiple insulated power wire cores, a protective layer outside the wrapping layer, a first vibration sensing element within the protective layer, and an isolation layer between the wrapping layer and the protective layer. By incorporating a spiral metal sheath within each conductor, with thermally conductive silicone grease filling the space between the sheath's inner wall and the temperature-sensing optical fiber, rapid and direct monitoring of the conductor's core temperature is achieved. Simultaneously, heat is transferred through the conductor's copper wires in the spiral microgrooves, the thermally conductive metal strip on the surface of the insulation layer, and the thermally conductive material in the filling layer to the multimode optical fiber core in the multi-core sensing cable, forming redundant temperature measurement channels. When the temperature of a conductor is abnormal, the corresponding temperature-sensing optical fiber and the multimode optical fiber core can be cross-verified, effectively avoiding false alarms caused by single-point faults or poor local contact, significantly improving temperature measurement reliability and response speed.

The utility model provides a small-divergence-angle anti-reflection laser. The small-divergence-angle anti-reflection laser comprises a substrate; the active region is formed on the substrate; the etching region is positioned on the light emitting end surface of the active region and comprises a divergence angle improving layer; the cladding extends along the light emitting direction of the active region; the metal contact layer covers the cladding layer above the active region; the isolation layer covers the cladding layer above the etching region; and an N-metal layer and a P-metal layer, the N-metal layer covers the back surface of the substrate, and the P-metal layer covers the metal contact layer and the isolation layer. Through the arrangement of the isolation layer, current injection into the end face can be limited, the light emitting power density of the end face can be reduced, the non-radiative recombination process can be inhibited, the temperature of the end face is reduced in the area, optical catastrophe damage can be reduced, and the service life of the laser can be prolonged.

The invention provides a thermal resistance model construction method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which is characterized in that a plurality of N-type doped isolation layers are formed on a substrate, an LDMOS structure is formed on each N-type doped isolation layer, all LDMOS structures are divided into different test groups according to different key sizes, and the key sizes at least comprise a total channel width and a cross index; measuring the thermal resistance of the LDMOS structure in each test group so as to respectively extract a thermal resistance value array of each group, and performing data fitting on the thermal resistance value array of each group so as to obtain a thermal resistance model of the relationship between the thermal resistance value of the LDMOS structure and the critical dimension; according to the method, the thermal resistance model of the full-size LDMOS device can be constructed by only utilizing a limited number of LDMOS structures in a primary tape, so that the thermal resistance of the LDMOS devices with different sizes can be predicted, the self-heating effect of the device can be accurately evaluated in the design stage, the device design is optimized, the development cost of the device is reduced, and the research and development period is shortened.

Apparatus and methods are disclosed, including interconnection pathways, vias, memory cells, semiconductor devices and systems. Example semiconductor devices and methods include a conducting via passing between a top level of a stack and a bottom level of the stack. One or more isolation layers surround sides and a bottom of the conducting via. A lateral connection is shown between a location along the conducting via and a selected conductor layer from the stack, the lateral connection passing through the isolation layer.

Embodiments of the invention include a transistor comprising a gate region and a source / drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.

The utility model relates to a composite board with high-strength and impact-resistant effects, and belongs to the field of boards. Comprising a base layer, a damping core layer fixedly connected to the top of the base layer, a multifunctional isolation layer fixedly connected to the top of the damping core layer, a high-strength supporting layer fixedly connected to the top of the multifunctional isolation layer, a buffering energy absorption layer fixedly connected to the top of the high-strength supporting layer and a surface protection layer fixedly connected to the top of the buffering energy absorption layer. According to the composite board with the high-strength and impact-resistant effects, various high-strength material layers are reasonably stacked and combined, the composite board can effectively absorb and disperse external impact force and slow down transmission of impact energy, the high-strength supporting layer is of a honeycomb aluminum alloy structure, and the honeycomb structure is designed to be gradually reduced in aperture, so that the impact resistance of the composite board is improved. The material can gradually disperse loads under impact of different strengths, the overall impact resistance is improved, and it is ensured that the composite board cannot be structurally damaged under extreme conditions.

To provide a thermoelectric device for easy positioning and bonding processes and a thermoelectric stack for such device. A representative embodiment of the present invention is a thermoelectric stack comprising a thermoelectric material layer having a first surface and a second surface opposite each other and an isolation layer stacked on the first surface of the thermoelectric material layer, wherein the thermoelectric material layer has a magnetization component perpendicular to the first surface and the second surface, and the isolation layer comprises, when a second thermoelectric stack is stacked on the surface opposite to the surface on which the thermoelectric material layer is to be stacked, an insulation region that electrically insulates the thermoelectric material layer and an electrode region that electrically conducts the thermoelectric material layer. Also, a representative embodiment of the present invention is a thermoelectric device in which such thermoelectric stacks are stacked, wherein a plurality of first thermoelectric stacks in which thermoelectric material layers have positive transverse thermoelectric power and a plurality of second thermoelectric stacks in which thermoelectric material layers have negative transverse thermoelectric power are alternately brought into close contact with each other due to the magnetic force of their magnetized components, interposing their respective isolation layers, and are electrically connected by electrode regions of the isolation layers.

The invention provides a two-stage correction device which can be applied to the technical field of mask deformation correction. The device comprises a first movable assembly and a second movable assembly, wherein one end of the first movable assembly can move in a first direction; the second movable assembly comprises a thermal isolation layer and an amplification assembly, the amplification assembly is arranged on the first movable assembly through the thermal isolation layer, the clamping assembly comprises an elastic compensation ring and a clamping part, the clamping part is connected with the second movable assembly through the elastic compensation ring, and the clamping part is used for clamping a mask; the second movable assembly can adjust the clamping part to move in the first direction through the amplification assembly.

The invention provides a display panel and electronic equipment, the display panel comprises a plurality of light-emitting devices, the plurality of light-emitting devices are arranged in an array, each light-emitting device comprises a light-emitting layer, the light-emitting layer comprises a sensitization layer, an isolation layer and a doping layer which are stacked in sequence, the sensitization layer comprises a main body material and a sensitization material, the mass of the main body material of the sensitization layer accounts for more than or equal to 50% of the mass of the sensitization layer, the doping layer comprises the main body material and a luminescent material, the mass of the main body material of the doping layer accounts for more than or equal to 50% of the mass of the doping layer, and the isolation layer comprises the main body material. The mass of the main body material of the isolation layer accounts for more than or equal to 80% of the mass of the isolation layer. According to the embodiment of the invention, triplet excitons in the sensitizer can be prevented from being transferred to the doping layer through energy, so that the service life of a fluorescent material in the doping layer is not influenced.

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate; the active regions are arranged in the substrate and are arranged in an array; the isolation layer is arranged between the active regions; the word line structure penetrates through the active region and divides the active region into a node region and a bit line region; a part of the expansion slot is arranged in the node area, and a part of the expansion slot is arranged in the isolation layer; the expansion pad is arranged in the expansion slot; wherein the expansion groove is filled and leveled up by the expansion pad.

The application is suitable for the technical field of structure engineering, and provides a structure adaptive limiting protection device.The device comprises: a support fixed on a lower end surface of a structure; a yoke with a vertical slot with an upper opening, one side of the yoke being fixed on an upper end surface of the structure through a connecting rod; the upper end surface of the structure is a lower side surface of a bridge beam body, and the lower end surface of the structure is an upper side surface of a bridge pier; or, the upper end surface of the structure and the lower end surface of the structure are upper and lower side surfaces of a structure for limiting in cooperation with an isolation layer in a building structure; a locking structure fixed on the upper end surface of the structure; a rotating disc and a disc shell, the top of the disc shell being provided with an opening corresponding to the position of the locking structure, the rotating disc being provided with a radial slot; an inner sliding block and an outer sliding block, the inner sliding block being connected with the radial slot through an extensible mechanism and being capable of sliding in the radial slot, the outer sliding block being rotatably connected with the inner sliding block and being capable of sliding in the vertical slot.The application can realize the dual functions of small displacement isolation without interference and large earthquake adaptive self-locking.

A Deep Trench Isolation (DTI) structure is disclosed. A DTI structure formed in a semiconductor substrate. The DIT structure includes an isolation layer and filling material. The isolation layer is formed from a p-type semiconductor material. Sidewall portions of the isolation layer are in contact with the semiconductor substrate. A bottom portion of the isolation layer is in contact with a connection feature, which is connected to an interconnect structure and configured to apply a bias to the isolation layer of the DTI structure to achieve a controllable passivation in the semiconductor substrate.