2203 results about "Isolation layer" patented technology

A display panel manufacturing method, a display panel and an electronic device, the display panel manufacturing method comprises: sequentially forming a pixel definition layer and an isolation layer on a driving backboard along a first direction, the pixel definition layer comprising a plurality of pixel definition structures arranged at intervals along a second direction, the isolation layer comprising a plurality of isolation columns, the isolation columns being in one-to-one correspondence with the plurality of pixel definition structures, the isolation columns being in one-to-one correspondence with the plurality of pixel definition structures, and the isolation columns being in one-to-one correspondence with the plurality of pixel definition structures; the isolation column comprises a first surface and a second surface which are oppositely arranged in the first direction, the first surface faces the pixel definition structure, and in the orthographic projection of the first direction, the second surface is located in the first surface; a first light-emitting structure is formed, the first light-emitting structure comprises a first light-emitting part and a first residual part which are spaced, the first light-emitting part is formed on the driving backboard and located between every two adjacent pixel definition structures, and the first residual part is formed on the second surface; and separating the isolation layer from the pixel definition layer. According to the preparation method of the display panel, the display effect of the display panel can be improved, and the manufacturing difficulty is reduced.

The invention discloses a wafer composite film and a preparation method thereof, and belongs to the technical field of semiconductor preparation. The method comprises the following steps: (1) performing hydrogen ion or hydrogen-helium mixed ion implantation on a piezoelectric wafer to obtain an implanted wafer, wherein the implanted wafer sequentially comprises a thin film layer, an implanted layer and a residual layer; (2) sequentially forming a defect layer and an isolation layer on the supporting substrate; (3) bonding the isolation layer and the thin film layer of the injected wafer to obtain a bonding body; and (4) laser is adopted to heat the injection layer, then annealing heat treatment is carried out on the bonding body to achieve complete stripping, polishing and cleaning of the film, then the wafer composite film is obtained, the wavelength of the laser is 100-700 nm, the power of the laser is 50 mw to 100 w, and the scanning speed of the laser is 10-50 mm / s. According to the method, complete stripping of the composite film and combination of laser and thermal annealing processes can be effectively achieved, the method has high process stability, the yield of the composite film can be greatly improved, and the processing time cost of the composite film is shortened.

The invention provides an intelligent sorting method and system for radioactive substances. The method comprises the following steps: synchronously detecting surface element composition and radiation intensity of a radioactive substance through an X-ray fluorescence spectrometer, and constructing a spatial difference matrix of element abundance distribution and a radiation gradient topological graph; the three-dimensional coordinates, the pressure threshold value and the shape adaptation parameters of the target grabbing position are determined on the basis, the curvature radius of the clamping jaw deformation contour is dynamically adjusted, and the error of the dynamic geometric envelope and the contour template is converged to be within the threshold value; finally, when the clamping jaw reaches a target position, the area of the heat shrinkage material is activated to be heated according to the radiation intensity abrupt change boundary coordinates, a sealed isolation layer synchronously expanded with the dynamic geometric envelope is generated, and safe grabbing and sealed isolation of radioactive substances are achieved. According to the technical scheme, accurate grabbing of radioactive substances, error self-adaptive compensation and synchronous isolation of radiation leakage can be achieved, and the sorting safety and efficiency are improved.

The embodiment of the invention provides a display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate, a pixel definition layer, a process structure layer, an isolation structure and a display function layer comprising a plurality of light-emitting devices, the pixel definition layer comprises a pixel limiting part, the process structure layer is located on the side, away from the substrate, of the pixel limiting part, and the orthographic projection of the process structure layer on the substrate is located in the orthographic projection of the pixel limiting part on the substrate. The isolation structure is located on the side, away from the substrate, of the technological structure layer and comprises a first isolation layer, a second isolation layer and a third isolation layer which are sequentially arranged in a stacked mode, and the orthographic projection of the second isolation layer on the substrate is located in the orthographic projection of the first isolation layer on the substrate. The light-emitting device comprises a first electrode, a light-emitting function layer and a second electrode which are arranged in a stacked mode, and the second electrode is electrically connected with the first isolation layer. According to the embodiment of the invention, the flatness of the pixel limiting part can be improved, and the film formation of the electrode layer is facilitated, so that the display effect of the display panel is ensured.

Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source / drain features on opposing sides of sacrificial gate structure, wherein the first source / drain feature is disposed below the second source / drain feature, and the first and second source / drain features are in contact with the isolation layer, first semiconductor layers, and third semiconductor layers.

The invention relates to a current sensor chip packaging structure and a packaging method. The current sensor chip packaging structure comprises a bus frame and a chip which are packaged through a plastic package body, the side, provided with the chip bonding pad, of the chip is defined as the front face of the chip, only one side of the front face is configured to be opposite to the back face of the bus frame, the chip bonding pad is arranged on the other side, extending out of the bus frame, of the front face, and a sensor element is arranged on the side, right opposite to the bus frame, of the front face of the chip. A gap between the chip and the bus frame is provided with an isolation layer, and the front surface is connected to the back surface of the bus frame through the isolation layer. According to the current sensor chip packaging structure and the packaging method, the front surface of the chip is connected to the back surface of the bus frame through the isolation layer, and the sensor element is arranged at the position opposite to the front surface of the chip, so that the distance between the sensor element and the bus frame is minimized, and the reliability of the current sensor chip is improved by minimizing the distance between the sensor element and the bus frame. Sensitivity and measurement precision of the sensor are remarkably improved, and the problems of reduction of isolation voltage endurance capability and process fluctuation are avoided.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; forming a protective layer on the natural oxide layer; a mask layer is formed on the protective layer, the protective layer and the natural oxide layer are etched downwards with the mask layer as a mask, and a reserved overlapping structure position is formed; forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position under a preset condition; and forming a second metal layer on the subsequent oxide layer, etching the second metal layer to form an overlapping structure, and taking the protection layer as an etching stop layer to protect the first metal structure layer when the second metal layer is etched. According to the invention, the first metal structure layer at the non-overlapping structure can be effectively prevented from being damaged when the second metal layer is etched, and the reliability problem is avoided.

A semiconductor device and methods for forming the semiconductor device are described. The semiconductor device can include a top transistor and a bottom transistor arranged in a stack configuration, and an isolation layer situated between the top transistor and the bottom transistor. The top transistor can be encompassed by a high-k gate dielectric. The bottom transistor can be encompassed by a metal-doped high-k gate dielectric. A first portion of the isolation layer can be encompassed by the high-k gate dielectric. A second portion of the isolation layer can be encompassed by the metal-doped high-k gate dielectric. The metal-doped high-k gate dielectric can encompass the bottom transistor and the second portion of the isolation layer can be encompassed by a layer of first work function material (WFM). The first WFM can be encompassed by a second WFM.

The utility model discloses an intelligent early warning cable, which comprises a power line insulation wire core arranged in a first belting layer, the power line insulation wire core comprises a conductor and an insulation layer coated outside the conductor, and a temperature measuring element is arranged in the conductor; an armor layer is arranged outside the first belting layer, and a vibration measuring element is arranged in the armor layer; and an isolating layer is arranged between the first belting layer and the armor layer. The temperature measuring element with the temperature measuring function is arranged on the outermost layer of the conductor, so that the temperature of the cable conductor can be monitored more accurately; the vibration measurement element with the vibration measurement function is arranged in the armor layer, and the isolation layer is arranged between the first belting layer and the armor layer, so that an electromagnetic field generated by the cable in the first belting layer under the conditions of high voltage and large current can be isolated, and the problem that the electromagnetic field interferes optical signal transmission in the vibration optical fiber is avoided; the vibration signal can be accurately detected, and the detection accuracy is prevented from being influenced by deviation.

The invention relates to the technical field of ceramic materials, in particular to a method for reducing the surface roughness of a silicon nitride instant-fired sheet, which comprises the following steps: S1, mixing alpha-silicon nitride, beta-silicon nitride, absolute ethyl alcohol and herring fish oil, grinding and dispersing to obtain basic mixed powder; s2, mixing, grinding and dispersing the filling mixed powder, absolute ethyl alcohol and herring fish oil, then carrying out filter pressing and drying, calcining and regrinding to obtain ground filling mixed powder; s3, mixing and ball-milling the basic mixed powder, the ground filling mixed powder, a solvent, an adhesive, a plasticizer and a dispersing agent to obtain slurry; s4, casting the slurry into a film; s5, attaching the thin film to the surface of the silicon nitride green body, and pressing the silicon nitride green body into a whole piece through an isostatic press to obtain a pressed green body; s6, a boron nitride isolation layer is printed on the surface of the pressed green body, and the green body with the isolation layer is obtained; and S7, stacking the green bodies with the isolating layers, and then carrying out adhesive removal and sintering reaction to obtain the silicon nitride ceramic chip.

An integrated circuit includes active regions on an upper surface of a semiconductor substrate and having no electrical connection on the semiconductor substrate, an isolation layer on the upper surface of the semiconductor substrate and defining the active regions, and polysilicon resistors on the active regions and the isolation layer. The polysilicon resistors extend in a second direction that is perpendicular to a first direction in which the active regions extend, and are configured such that the number of active regions overlapping each of the polysilicon resistors in a vertical direction is identical.

The invention discloses a back contact battery, a manufacturing method thereof and a photovoltaic module, relates to the technical field of photovoltaic, and aims to reduce the electric leakage risk of the edge part, close to a groove, of a first doped semiconductor part and facilitate the improvement of the conversion efficiency of the back contact battery. The back contact battery comprises a semiconductor substrate, a first doped semiconductor part, an isolation layer and a second doped semiconductor part. The bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first region and the second region, respectively, to form a groove. The surface height of the second area is smaller than the surface height of the first area in the direction from the second face to the first face. The first doped semiconductor portion is disposed in the first region. The isolation layer is at least arranged on the portion, close to the notch of the groove, of the first side face. The second doped semiconductor portion is disposed on the second region and a side of the isolation layer facing away from the semiconductor substrate. And the doping types of the second doped semiconductor part and the first doped semiconductor part are opposite.

The invention discloses a crystal growth device and a crystal growth method for gallium oxide crystal downward growth, and belongs to the technical field of gallium oxide single crystal preparation. The device comprises a crucible, an upper shaft, a heating mechanism and a heat preservation mechanism, the crucible is composed of a metal layer and an isolation layer arranged on the inner side wall of the metal layer, an opening is formed in the top of the metal layer, the thermal expansion coefficient of the side, away from the metal layer, of the isolation layer ranges from 0.5 * 10 <-6 > k <-1 > to 2.5 * 10 <-6 > k <-1 >, and the thermal expansion coefficient of the isolation layer is gradually increased outwards from the side, away from the metal layer, of the isolation layer. The rising rate is 2 * 10 <-6 >-3 * 10 <-6 > k <-1 > / mm; the upper shaft is arranged above an opening of the crucible and can lift and rotate relative to the crucible, a seed crystal support is arranged below the upper shaft, a first cooling pipeline is arranged in the upper shaft, and a second cooling pipeline is arranged in the seed crystal support. The crystal growth device breaks through the limitation of a traditional Czochralski method, a casting method and a Bridgman method, realizes downward growth of crystals, and can reduce the influence of crucible metal impurities on the crystals, so that gallium oxide single crystals with high quality, large size and high yield are obtained.

Various embodiments of the utility model relate to a semiconductor device, the semiconductor device comprises a plurality of photodiode doped regions formed in a substrate and a deep trench isolation (DTI) structure formed in the substrate, the DTI structure separates the photodiode doped regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material comprises a top, a side wall and a bottom. The semiconductor device also includes a first isolation layer surrounding and contacting the top, sidewalls, and bottom of the first fill material.

Integrated circuit structures having void-free internal spacers, and methods of fabricating integrated circuit structures having void-free internal spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent nanowires of the stack of horizontal nanowires and laterally adjacent to the gate structure. An epitaxial source or drain structure is coupled to an end of the stack of horizontal nanowires and in contact with the internal gate spacer. A dielectric structure is beneath and in contact with the epitaxial source or drain structure, the dielectric structure including a same material as the internal gate spacer, and the dielectric structure not including a seam therein.

The present invention relates to the field of semiconductors. Provided are a semiconductor structure and a preparation method therefor, and an electronic device, which are used for simplifying semiconductor structures and preparation methods therefor. The preparation method for the semiconductor structure comprises: forming 2n stacked material layer groups (2101) on a first substrate (100), wherein each stacked material layer group (2101) comprises a first material film layer (2111) and a second material film layer (2121); forming n first openings (10) with different depths, and among the first openings (10) from shallow to deep, forming first isolation layers (310) at ends of the first (i-1) first material film layers (2111) penetrated by the ith first opening (10); forming a second opening (20) below each first opening (10), and forming second isolation layers (320) at ends of the first (n-1) first material film layers (2111) penetrated by each second opening (20); and below each second opening (20), forming a third opening (30) extending to the first substrate (100), and forming third isolation layers (330) at ends of the first material film layers (2111) penetrated by each third opening (30).

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming first isolation layers and second isolation layers, which are alternately stacked, on the substrate; the first isolation layer and the second isolation layer are etched, a capacitor hole group is formed, and the capacitor hole group comprises at least two capacitor sub-holes which are arranged at intervals in the first direction and extend to the substrate; performing lateral etching on the second isolation layer from the capacitance sub-hole to form a first surrounding groove surrounding the capacitance sub-hole; forming a first capacitor electrode which extends along the first direction and fills the first surrounding groove; and forming a capacitor dielectric layer on the side wall and the bottom of the capacitor sub-hole, and forming a second capacitor electrode on the surface of the capacitor dielectric layer. The embodiment of the invention can effectively improve the performance of the device.

The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; and a liner layer positioned between the contact layer and the substrate, between the contact layer and the plurality of bit line structures, and between the contact layer and the plurality of partition layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

The invention discloses a semiconductor device with a nanosheet transistor and a manufacturing method thereof. The method includes forming a sacrificial layer between a first stacked layer and a second stacked layer, the first stacked layer including first semiconductor layers and second semiconductor layers alternately stacked, the second stacked layer including third semiconductor layers and fourth semiconductor layers alternately stacked, and the sacrificial layer including a semiconductor metal oxide; forming a sacrificial gate structure over a portion of the second stack layer; removing parts of the first stack layer and the second stack layer which are not covered by the sacrificial gate structure; removing the sacrificial layer to form a cavity; filling the cavity with a dielectric to form an isolation layer; and forming a first source / drain feature and a second source / drain feature on opposite sides of the sacrificial gate structure, where the first source / drain feature is disposed lower than the second source / drain feature, the first source / drain feature and the second source / drain feature being in contact with the isolation layer, the first semiconductor layer, and the third semiconductor layer.

The invention discloses a power device with a drain electrode led out from the front side and a manufacturing method thereof, the power device comprises a substrate, an epitaxial layer and an isolation layer, and the power device is divided into a gate contact region, an active region, a terminal region and a terminal peripheral region along the horizontal direction; gate metal is arranged on the isolation layer of the gate contact region and is connected with the gate interconnection structure; source electrode metal is arranged on the isolation layer of the active region and is connected with the source region; the terminal region is provided with a voltage-withstanding ring and a cut-off ring structure, the isolation layer of the terminal peripheral region is provided with drain electrode metal, and the drain electrode metal is connected with the first injection region of the terminal peripheral region. According to the invention, the drain electrode metal of the power device is changed into the terminal peripheral area arranged on the front surface of the power device, so that the source electrode metal, the drain electrode metal and the grid electrode metal of the power device are all located on the same plane, the demand of clip materials can be effectively reduced, the performance of the power device can be improved, and the parasitic effect can be reduced.

The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: forming a plurality of first trenches arranged at intervals and extending along a first direction in a base; forming a first insulating layer on a sidewall of the first trench, where a thickness of the first insulating layer is smaller than a target value, and the first insulating layer defines a second trench; performing a silicification reaction on a substrate exposed in the second trench; forming a second insulating layer on a sidewall of the second trench, where the second insulating layer defines a third trench, and a sum of thicknesses of the first insulating layer and the second insulating layer is equal to the target value; and forming an isolation layer in the third trench.

Provided is a semiconductor memory device. The semiconductor memory device includes a plurality of trenches including a plurality of first trenches in a substrate and a plurality of second trenches between ones of the plurality of first trenches, and a plurality of device isolation layers. A first height of a lowermost surface of a direct contact in a vertical direction may be higher than a second height of a lowermost surface of a buried contact in the vertical direction, relative to a lower surface of the substrate.

A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.

A method for preparing a hybrid filter on a chip with IPD and FBAR, includes: preparing a leakage isolation layer on a supporting substrate by deposition; obtaining an inductor layer on the leakage isolation layer, leaving a window at a bottom of a groove surrounding a cross section of a TGV inductor stack on a mask, and patterning an inductor metal simultaneously; forming a first insulating layer on the inductor metal, and forming lead through holes by photolithography; repeating steps and alternately to obtain a three-layer stacked TGV inductor; depositing a second insulating layer on the TGV inductor; depositing two capacitor layers on the second insulating layer, and depositing a third insulating layer between the two capacitor layers to form an MIM capacitor; and preparing a BAW resonator on the MIM capacitor, and connecting the TGV inductor, the MIM capacitor and the BAW resonator through the lead through holes.

The invention relates to the technical field of photovoltaic, provides a photovoltaic cell and a photovoltaic module, and at least facilitates the improvement of the efficiency and yield of the photovoltaic cell. The photovoltaic cell comprises a cell body, the surface of the cell body is provided with an isolation layer, and the isolation layer is used for isolating adjacent cell bodies; the isolation layer comprises a first isolation layer which covers the surface of the battery body; the second isolation layer is positioned on one side, far away from the battery body, of the first isolation layer; the light trapping parts are located between the first isolation layer and the second isolation layer, each light trapping part is in a cone shape, the top of each cone faces the first isolation layer, and the bottom of each cone faces the second isolation layer.

The invention discloses a planar gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure capable of improving irradiation capability and a manufacturing method thereof. A substrate gradient buffer region is added between a substrate and an N-drift region of a conventional planar structure MOSFET; a P-type isolation layer and a P-type isolation layer gradient buffer region are added between the P-Well region and the N-drift region; a P-Plus region gradient buffer region is additionally arranged between the P-Plus region and the P-Well region; an N-Plus region gradient buffer region is additionally arranged between the N-Plus region and the P-Well region; a grid electrode is set as a separation grid electrode, and a P-type high-energy particle injection layer is integrated in the middle of the separation grid electrode. The arranged substrate gradient buffer region can reduce a peak electric field caused by high-energy particles injected from any region of the device in the irradiation period, and the probability that the device is out of control in the irradiation period of the high-energy particles is reduced.

The pressure sensor chip comprises a substrate, a sensitive resistor, a lead-out part and a bonding part, the sensitive resistor, the lead-out part and the bonding part are all connected with the substrate, the thickness direction perpendicular to the pressure sensor chip is defined as the horizontal direction, and the lead-out part is located on one side of the bonding part in the horizontal direction; the pressure sensor chip comprises a pressure sensing part, the pressure sensor chip is provided with a first cavity, and at least part of the pressure sensing part is exposed out of the first cavity; the pressure sensing part comprises an isolating layer and a pressure sensing film; at least part of the substrate forms a pressure-sensitive film, the isolating layer is arranged on the pressure-sensitive film, at least part of the sensitive resistor is arranged on the isolating layer, and at least part of the isolating layer is located between the sensitive resistor and the pressure-sensitive film; the invention further discloses a manufacturing method of the pressure sensor chip. According to the invention, the isolation layer is arranged between the sensitive resistor and the substrate, so that the current generated by the sensitive resistor is reduced to partially flow into the substrate under a high-temperature condition, and the chip can be well applied in a high-temperature environment.

The invention relates to a fast recovery diode and a manufacturing method thereof. The fast recovery diode comprises a substrate; the first epitaxial layer is located on one side of the substrate, at least one floating region is formed in the first epitaxial layer, the doping type of the first epitaxial layer is the same as that of the substrate, and the doping type of the floating region is different from that of the first epitaxial layer; the active layer is located on the side, away from the substrate, of the first epitaxial layer, the active layer comprises an anode region and a terminal region, the anode region and the terminal region are both in contact with the first epitaxial layer, the terminal region is arranged around the anode region, and the doping types of the anode region and the floating region are the same; the isolation layer is located on the side, away from the substrate, of the active layer, the isolation layer comprises a contact hole, and the contact hole exposes part of the anode region; the first metal layer is located on the side, away from the substrate, of the isolation layer, and the first metal layer makes contact with the anode region through the contact hole; therefore, the reverse recovery speed of the fast recovery diode with the positive temperature coefficient is improved.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

Acoustic sensor systems with different heights, as well as methods for configuring and operating such sensor systems are disclosed. In some embodiments, a sensor system described herein may include an acoustic transmitter element; and an acoustic receiver element; wherein the first portion of the piezoelectric material of the acoustic transmitter element comprises a first thickness, and the second portion of the piezoelectric material of the acoustic receiver element comprises a second thickness different from the first thickness; and wherein the isolation layer is structured to create a gap that physically separates the first portion of the second electrode layer from the second portion of the second electrode layer.