7958 results about "Isolation layer" patented technology

Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. Multilayer devices are constructed to position a neutral mechanical surface coincident or proximate to a functional layer having a material that is susceptible to strain-induced failure. Neutral mechanical surfaces are positioned by one or more layers having a property that is spatially inhomogeneous, such as by patterning any of the layers of the multilayer device.

A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.

Provided are a multi-channel semiconductor device and a method for manufacturing the semiconductor device through a simplified process. A sacrificial layer and a channel layer are alternately stacked on a semiconductor substrate. Thereafter, the sacrificial layer and the channel layer are etched to form a separated active pattern, and a device isolation layer is formed to cover sidewalls of the active pattern. Dopant ions are implanted into the entire semiconductor substrate, thereby forming a channel separation region under the active pattern. A portion of the active pattern is etched to separate the active pattern from a pair of facing sidewalls of the device separation layer, thereby forming a channel pattern having a pair of first exposed sidewalls. Source/drain semiconductor layers are formed on the first sidewalls of the channel pattern, and a part of the device isolation layer is removed to expose a pair of second sidewalls of the channel pattern contacting with the device separation layer. Thereafter, the sacrificial layer included in the channel pattern is remove, and a conductive layer for a gate electrode is formed to cover the channel layer exposed by the removing of the sacrificial layer.

A system and method of operation is disclosed describing migration, management, and operation of applications and servers from customer data centers to cloud computing platforms without modification to existing environments or user access procedures. A cloud isolation layer operates as a virtual layer on the cloud platform, enabling server operation in a virtual environment that appears the same as the prior local environment. A cloud software image and a local cloud gateway act to redirect existing addressing from the local environment to the cloud implementation through secure network and data paths. A local management application provides a control interface and maps and manages the local environment and utilized cloud resources.

A chemical vapor deposition apparatus is disclosed. The chemical vapor deposition apparatus comprises a chamber having a base plate, a chamber wall, a gas inlet and a gas outlet. The base plate has holes therethrough. A plurality of electrodes extend through the holes of the base plate. The plurality of electrodes are capable of being attached to a power source. At least two of the plurality of electrodes are capable of being electrically coupled to a silicon rod positioned in the chamber. An electrical isolation bushing can be positioned between each of the plurality of electrodes and the base plate. The electrical isolation bushing comprises a sleeve portion surrounding a portion of the electrodes that extends through the base plate and a collar portion surrounding the holes at a surface of the base plate. In some instances, the collar portion can comprise a different material than the sleeve portion. In some instances, an isolation layer can be employed in addition to the isolation bushing, the isolation layer surrounding the holes at the surface of the base plate. In some instances, the collar portion and the sleeve portion are both ceramic.

A detecting device for biochemical detections is provided. The detecting device includes a first substrate, a magnetic layer located on the first substrate, an isolation layer located on the magnetic layer, at least a first electrode located on the isolation layer, a first dielectric layer located on the first electrode, a first hydrophobic layer located on the first dielectric layer, a second substrate, at least a second electrode located on the second substrate and having a cathode and an anode, a second dielectric layer located on the second electrode and a second hydrophobic layer located on the second dielectric layer. The first electrode is zigzag-shaped, and the cathode and the anode of the second electrode are comb-shaped and interlaced with each other.

A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

An isolation method of defining active fins, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby are provided. The method of fabricating a semiconductor device includes: preparing a semiconductor substrate; and forming a plurality of active fins having major and minor axes and two-dimensionally arrayed on the semiconductor substrate in directions of the major and minor axes. A liner pattern is formed on lower sidewalls of the active fins. An isolation layer is formed on the semiconductor substrate having the liner pattern, and the isolation layer exposes top surfaces of the active fins and a part of the active fins' sidewalls substantially parallel to the major axis. Parallel gate lines are formed to cover the top surfaces and the exposed sidewalls of the active fins, cross over the active fins, and run on the isolation layer.

Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

A nitride semiconductor light emitting device including a light emitting diode and a diode formed on a single substrate, in which the light emitting diode and the diode use a common electrode. According to the present invention, an active layer and a p-type nitride semiconductor layer are each divided into a first region and a second region by an insulative isolation layer, and an ohmic contact layer is formed on the p-type nitride semiconductor layer contained in the first region. A p-type electrode is formed on the ohmic contact layer and is extended to the p-type nitride semiconductor layer contained in the second region. An n-type electrode is formed on the p-type nitride semiconductor layer contained in the second region, passes through the p-type nitride semiconductor layer and the active layer contained in the second region, and is connected to the first n-type nitride semiconductor layer.

Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first etching process. A protection layer pattern is formed on a sidewall of the first recess. A second recess is formed beneath the first recess. The second recess has a width substantially larger than that of the first recess. The second recess is formed by a second etching process using an etching gas containing an SF₆ gas, a Cl₂ gas and an O₂ gas. A gate insulation layer is formed on surfaces of the first and the second recesses. The second recess having an enlarged shape may reduce a width of the junction between the gate electrode and the isolation layer so that a leakage current generated through the junction may decrease.

A network abstraction and isolation layer (NAIL) for masquerading the machine identity of a computer in a network to enable the computer to communicate in the network with a different machine identity including an isolated network interface for communicating with the computer, an abstraction network interface for communicating with a network device coupled to the network, and control logic. The control logic is coupled to the isolated and abstraction network interfaces and performs machine identity translation to masquerade machine identity of the computer relative to the network. Machine identity masquerading includes selectively translating any one or more of an IP address, a MAC address, a machine name, a system identifier, and a DNS Name in the header or payload of communication packets.

A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.

A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.