3249 results about "Isolation layer" patented technology

The embodiment of the invention discloses a display panel and a display device, an isolation layer is arranged in a display area, the isolation layer comprises a plurality of isolation openings, and light-emitting function layers are located in the isolation openings, so that the isolation layer isolates the light-emitting function layers of adjacent light-emitting devices, and it is ensured that crosstalk does not occur between the light-emitting devices. According to the display panel, the power source wire is arranged in at least part of the non-display area except the first side edge circuit area, that is, the power source wire can not be arranged in the first side edge circuit area, so that the distance between the dam and the display area does not comprise the width of the frame occupied by the power source wire. Therefore, the distance between the dam and the display area can be reduced, the width of the first frame area is reduced, a narrow frame is achieved, and the screen-to-body ratio is increased.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and an electronic device, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises an isolation layer and a plurality of first isolation structures which are arranged at intervals in a first direction parallel to the surface of the substrate; forming first isolation parts in the substrate, wherein the first isolation parts and the first isolation structures are arranged in a one-to-one manner and extend to the isolation layer through the back surface of the substrate; removing the substrate between the adjacent first isolation parts to obtain side wall semiconductor layers located on the side surfaces of the first isolation parts and first grooves between the adjacent side wall semiconductor layers; the size of the side wall semiconductor layer is gradually increased in the direction close to the isolation layer. And forming a bottom photosensitive layer in the first groove, and epitaxially growing a top photosensitive layer on the bottom photosensitive layer. And forming a second isolation part connected with the first isolation part in a gap between the adjacent top photosensitive layers, thereby improving the photoelectric conversion efficiency and the quantum efficiency.

A display panel manufacturing method, a display panel and an electronic device, the display panel manufacturing method comprises: sequentially forming a pixel definition layer and an isolation layer on a driving backboard along a first direction, the pixel definition layer comprising a plurality of pixel definition structures arranged at intervals along a second direction, the isolation layer comprising a plurality of isolation columns, the isolation columns being in one-to-one correspondence with the plurality of pixel definition structures, the isolation columns being in one-to-one correspondence with the plurality of pixel definition structures, and the isolation columns being in one-to-one correspondence with the plurality of pixel definition structures; the isolation column comprises a first surface and a second surface which are oppositely arranged in the first direction, the first surface faces the pixel definition structure, and in the orthographic projection of the first direction, the second surface is located in the first surface; a first light-emitting structure is formed, the first light-emitting structure comprises a first light-emitting part and a first residual part which are spaced, the first light-emitting part is formed on the driving backboard and located between every two adjacent pixel definition structures, and the first residual part is formed on the second surface; and separating the isolation layer from the pixel definition layer. According to the preparation method of the display panel, the display effect of the display panel can be improved, and the manufacturing difficulty is reduced.

An interconnection structure, including: a first BEOL (Back-End-Of-Line) level which includes a first MLG (Multi-Layer Graphene) layer which includes at least one first line structure of MLG material; and a first isolation layer which includes an electrically isolating material and is disposed above and beside the at least one first line structure of MLG material; a second BEOL level which includes a second MLG layer (includes MLG material) disposed above the first isolation layer; a connection path electrically connecting first MLG layer to second MLG layer; and at least one via with serrated edges mitigating misalignment impacts and providing low via to line contact resistance, where the connection path includes one of the at least one via, where a width of the at least one first line structure of MLG material is greater than a diameter of the one of the at least one via, and where both MLG layers are intercalation doped.

The invention discloses a wafer composite film and a preparation method thereof, and belongs to the technical field of semiconductor preparation. The method comprises the following steps: (1) performing hydrogen ion or hydrogen-helium mixed ion implantation on a piezoelectric wafer to obtain an implanted wafer, wherein the implanted wafer sequentially comprises a thin film layer, an implanted layer and a residual layer; (2) sequentially forming a defect layer and an isolation layer on the supporting substrate; (3) bonding the isolation layer and the thin film layer of the injected wafer to obtain a bonding body; and (4) laser is adopted to heat the injection layer, then annealing heat treatment is carried out on the bonding body to achieve complete stripping, polishing and cleaning of the film, then the wafer composite film is obtained, the wavelength of the laser is 100-700 nm, the power of the laser is 50 mw to 100 w, and the scanning speed of the laser is 10-50 mm / s. According to the method, complete stripping of the composite film and combination of laser and thermal annealing processes can be effectively achieved, the method has high process stability, the yield of the composite film can be greatly improved, and the processing time cost of the composite film is shortened.

The invention provides an intelligent sorting method and system for radioactive substances. The method comprises the following steps: synchronously detecting surface element composition and radiation intensity of a radioactive substance through an X-ray fluorescence spectrometer, and constructing a spatial difference matrix of element abundance distribution and a radiation gradient topological graph; the three-dimensional coordinates, the pressure threshold value and the shape adaptation parameters of the target grabbing position are determined on the basis, the curvature radius of the clamping jaw deformation contour is dynamically adjusted, and the error of the dynamic geometric envelope and the contour template is converged to be within the threshold value; finally, when the clamping jaw reaches a target position, the area of the heat shrinkage material is activated to be heated according to the radiation intensity abrupt change boundary coordinates, a sealed isolation layer synchronously expanded with the dynamic geometric envelope is generated, and safe grabbing and sealed isolation of radioactive substances are achieved. According to the technical scheme, accurate grabbing of radioactive substances, error self-adaptive compensation and synchronous isolation of radiation leakage can be achieved, and the sorting safety and efficiency are improved.

The embodiment of the invention provides a laminated cell and a preparation method of the laminated cell, the laminated cell comprises a top cell unit, a bottom cell unit and a composite layer located between the top cell unit and the bottom cell unit, the composite layer has a first surface facing the top cell unit along the thickness direction of the laminated cell, and the first surface is provided with a second surface facing the bottom cell unit. A first passivation isolation layer is arranged on the first surface, and the surface area of the first passivation isolation layer is smaller than that of the first surface. By arranging the first passivation isolation layer on the first surface, the separation effect on the perovskite layer and the composite layer can be improved, the phenomenon of contact between the perovskite layer and the composite layer is reduced, and the possibility of electric leakage of the laminated cell is remarkably reduced, so that the working performance of the laminated cell is ensured. And the surface area of the first passivation isolation layer is smaller than that of the first surface, so that carriers can circulate between the hole transport layer and the composite layer, and normal use of the laminated cell is ensured.

Provided is a semiconductor device 10 and a method of manufacturing the semiconductor device 10. The semiconductor device 10 includes: a 1st source / drain region 130L; a 2nd source / drain region 130R; a channel structure 110 connecting the 1st source / drain region 130L to the 2nd source / drain region 130R; a gate structure 115 surrounding the channel structure 110; a backside contact structure 150, below the 1st source / drain region 130L, connected to the 1st source / drain region 130L; and a 1st backside spacer 151 at a lateral side of the backside contact structure 150, and / or an isolation stack 100, below the gate structure 115, comprising at least one isolation layer 103 and a substrate layer 105 which are vertically stacked.

The embodiment of the invention provides a display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate, a pixel definition layer, a process structure layer, an isolation structure and a display function layer comprising a plurality of light-emitting devices, the pixel definition layer comprises a pixel limiting part, the process structure layer is located on the side, away from the substrate, of the pixel limiting part, and the orthographic projection of the process structure layer on the substrate is located in the orthographic projection of the pixel limiting part on the substrate. The isolation structure is located on the side, away from the substrate, of the technological structure layer and comprises a first isolation layer, a second isolation layer and a third isolation layer which are sequentially arranged in a stacked mode, and the orthographic projection of the second isolation layer on the substrate is located in the orthographic projection of the first isolation layer on the substrate. The light-emitting device comprises a first electrode, a light-emitting function layer and a second electrode which are arranged in a stacked mode, and the second electrode is electrically connected with the first isolation layer. According to the embodiment of the invention, the flatness of the pixel limiting part can be improved, and the film formation of the electrode layer is facilitated, so that the display effect of the display panel is ensured.

The present inventive concepts relate to semiconductor devices and methods for fabricating the same, and a semiconductor device according to some example embodiments includes: a substrate including an active region defined by a device isolation layer; a word line that crosses and overlaps the active region; a bit line crossing the active region in a direction different from the word line; a direct contact that connects the active region and the bit line and includes a metallic material; a buried contact connected to the active region; and a bit line spacer between the bit line and the buried contact, wherein a width of the direct contact is different from that of the bit line, and the bit line spacer is on an upper surface of the direct contact.

Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source / drain features on opposing sides of sacrificial gate structure, wherein the first source / drain feature is disposed below the second source / drain feature, and the first and second source / drain features are in contact with the isolation layer, first semiconductor layers, and third semiconductor layers.

The invention relates to a current sensor chip packaging structure and a packaging method. The current sensor chip packaging structure comprises a bus frame and a chip which are packaged through a plastic package body, the side, provided with the chip bonding pad, of the chip is defined as the front face of the chip, only one side of the front face is configured to be opposite to the back face of the bus frame, the chip bonding pad is arranged on the other side, extending out of the bus frame, of the front face, and a sensor element is arranged on the side, right opposite to the bus frame, of the front face of the chip. A gap between the chip and the bus frame is provided with an isolation layer, and the front surface is connected to the back surface of the bus frame through the isolation layer. According to the current sensor chip packaging structure and the packaging method, the front surface of the chip is connected to the back surface of the bus frame through the isolation layer, and the sensor element is arranged at the position opposite to the front surface of the chip, so that the distance between the sensor element and the bus frame is minimized, and the reliability of the current sensor chip is improved by minimizing the distance between the sensor element and the bus frame. Sensitivity and measurement precision of the sensor are remarkably improved, and the problems of reduction of isolation voltage endurance capability and process fluctuation are avoided.

The invention discloses a power MOSFET and a preparation method thereof, and belongs to the technical field of microelectronics. The power MOSFET comprises a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer which are arranged from bottom to top, wherein the top surface of the Ga2O3 epitaxial layer is provided with a groove, and an oxide isolation layer is arranged in the groove; the drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxide isolation layer; the source electrode is arranged in the middle area of the other side of the Ga2O3 epitaxial layer; second grooves are formed in the two sides of the source electrode; a NiO layer and an insulated gate dielectric layer are arranged on the second groove from bottom to top; a gate electrode with a non-planar gate structure is arranged on the insulated gate dielectric layer; and a gap part around the second groove and the gate electrode is filled with a first oxide isolation layer. Through structural design and material selection, the problems of serious heat dissipation and gate electrode electric leakage of existing similar devices are solved, and the voltage withstanding performance of the device is improved.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; forming a protective layer on the natural oxide layer; a mask layer is formed on the protective layer, the protective layer and the natural oxide layer are etched downwards with the mask layer as a mask, and a reserved overlapping structure position is formed; forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position under a preset condition; and forming a second metal layer on the subsequent oxide layer, etching the second metal layer to form an overlapping structure, and taking the protection layer as an etching stop layer to protect the first metal structure layer when the second metal layer is etched. According to the invention, the first metal structure layer at the non-overlapping structure can be effectively prevented from being damaged when the second metal layer is etched, and the reliability problem is avoided.

The invention relates to a flexible two-dimensional strain and pressure composite sensor and a preparation method and application of the flexible two-dimensional strain and pressure composite sensor. The two-dimensional sensing unit comprises a first flexible substrate, and a first sensing layer, an isolation layer, a second sensing layer and a first packaging layer which are sequentially stacked on the first flexible substrate, the first sensing layer and the second sensing layer are arranged in a staggered manner, and the two-dimensional sensing unit comprises a first part and a second part; the elastic modulus of the first part is greater than that of the second part, and the elastic modulus difference is greater than or equal to 160MPa; the pressure sensing unit is arranged on the two-dimensional sensing unit, the third part corresponds to the first part, and the fourth part is of a paper-cut structure. The flexible two-dimensional strain and pressure composite sensor can monitor the strain in the two-dimensional direction in the plane and the pressure in the vertical direction of the plane at the same time, the sub-sensors work independently and do not interfere with one another, the sensitivity is high, and the monitoring accuracy is high.

A semiconductor device and methods for forming the semiconductor device are described. The semiconductor device can include a top transistor and a bottom transistor arranged in a stack configuration, and an isolation layer situated between the top transistor and the bottom transistor. The top transistor can be encompassed by a high-k gate dielectric. The bottom transistor can be encompassed by a metal-doped high-k gate dielectric. A first portion of the isolation layer can be encompassed by the high-k gate dielectric. A second portion of the isolation layer can be encompassed by the metal-doped high-k gate dielectric. The metal-doped high-k gate dielectric can encompass the bottom transistor and the second portion of the isolation layer can be encompassed by a layer of first work function material (WFM). The first WFM can be encompassed by a second WFM.

The invention discloses a display substrate and a display device. The display substrate comprises a substrate body, a plurality of circles of isolation columns and an inorganic layer, wherein the isolation columns and the inorganic layer are located on the substrate body. The multiple circles of isolation columns are located in a non-hole area on the substrate and surround the hole area. The isolation column at least comprises a first isolation layer and a second isolation layer which are arranged in a stacked mode, the second isolation layer is located on the side, away from the substrate, of the first isolation layer, the edge of the second isolation layer protrudes relative to the edge of the first isolation layer, and the first isolation layer and the second isolation layer are both made of conductive materials; the inorganic layer wraps the side surfaces of the first isolation layer and the second isolation layer of at least one circle of isolation column. According to the invention, the electrical connection between the isolation layer in the isolation column configured to isolate the light-emitting function layer and the film layer in the light-emitting function layer can be prevented, and the etching step under the condition that the inorganic layer is remained in the isolation column can be saved.

The utility model discloses an intelligent early warning cable, which comprises a power line insulation wire core arranged in a first belting layer, the power line insulation wire core comprises a conductor and an insulation layer coated outside the conductor, and a temperature measuring element is arranged in the conductor; an armor layer is arranged outside the first belting layer, and a vibration measuring element is arranged in the armor layer; and an isolating layer is arranged between the first belting layer and the armor layer. The temperature measuring element with the temperature measuring function is arranged on the outermost layer of the conductor, so that the temperature of the cable conductor can be monitored more accurately; the vibration measurement element with the vibration measurement function is arranged in the armor layer, and the isolation layer is arranged between the first belting layer and the armor layer, so that an electromagnetic field generated by the cable in the first belting layer under the conditions of high voltage and large current can be isolated, and the problem that the electromagnetic field interferes optical signal transmission in the vibration optical fiber is avoided; the vibration signal can be accurately detected, and the detection accuracy is prevented from being influenced by deviation.

The invention relates to the technical field of ceramic materials, in particular to a method for reducing the surface roughness of a silicon nitride instant-fired sheet, which comprises the following steps: S1, mixing alpha-silicon nitride, beta-silicon nitride, absolute ethyl alcohol and herring fish oil, grinding and dispersing to obtain basic mixed powder; s2, mixing, grinding and dispersing the filling mixed powder, absolute ethyl alcohol and herring fish oil, then carrying out filter pressing and drying, calcining and regrinding to obtain ground filling mixed powder; s3, mixing and ball-milling the basic mixed powder, the ground filling mixed powder, a solvent, an adhesive, a plasticizer and a dispersing agent to obtain slurry; s4, casting the slurry into a film; s5, attaching the thin film to the surface of the silicon nitride green body, and pressing the silicon nitride green body into a whole piece through an isostatic press to obtain a pressed green body; s6, a boron nitride isolation layer is printed on the surface of the pressed green body, and the green body with the isolation layer is obtained; and S7, stacking the green bodies with the isolating layers, and then carrying out adhesive removal and sintering reaction to obtain the silicon nitride ceramic chip.

A semiconductor device may include a substrate including an active pattern, a device isolation layer defining the active pattern, a channel pattern on the active pattern, a gate electrode on the channel pattern, and a first isolation pattern and a second isolation pattern penetrating the gate electrode. The first isolation pattern may be extended into the device isolation layer, and the second isolation pattern may be provided to penetrate the gate electrode and the device isolation layer and may be extended into an upper portion of the substrate. A level of a bottom surface of the second isolation pattern may be lower than a level of a bottom surface of the device isolation layer.

A battery, comprising a battery cell (1) and a housing. The battery cell (1) comprises a first electrode sheet (8), an isolation layer (7), a second electrode sheet (9), a first tab (2), and a second tab (4) which are sequentially stacked or wound; the first tab (2) is provided with a first welding mark (3), and the second tab (4) is provided with a second welding mark (5); the metal material of the first tab (2) is the same as that of the housing; the first welding mark (3) protrudes out of the surface of the first tab (2) and faces the housing, and the first welding mark (3) is not covered with an adhesive tape (6); and the second welding mark (5) is covered with the adhesive tape (6). According to the battery provided by the present application, by means of the structural arrangement, on the basis of not causing any safety hazard, the adhesive tape (6) does not need to be adhered to the first tab (2), so that the volume ratio of a charging / discharging component of the battery is increased, improving the energy density of the battery.

An integrated circuit includes active regions on an upper surface of a semiconductor substrate and having no electrical connection on the semiconductor substrate, an isolation layer on the upper surface of the semiconductor substrate and defining the active regions, and polysilicon resistors on the active regions and the isolation layer. The polysilicon resistors extend in a second direction that is perpendicular to a first direction in which the active regions extend, and are configured such that the number of active regions overlapping each of the polysilicon resistors in a vertical direction is identical.

The invention discloses a back contact battery, a manufacturing method thereof and a photovoltaic module, relates to the technical field of photovoltaic, and aims to reduce the electric leakage risk of the edge part, close to a groove, of a first doped semiconductor part and facilitate the improvement of the conversion efficiency of the back contact battery. The back contact battery comprises a semiconductor substrate, a first doped semiconductor part, an isolation layer and a second doped semiconductor part. The bottom surface of the third region is recessed into the semiconductor substrate relative to the surfaces of the first region and the second region, respectively, to form a groove. The surface height of the second area is smaller than the surface height of the first area in the direction from the second face to the first face. The first doped semiconductor portion is disposed in the first region. The isolation layer is at least arranged on the portion, close to the notch of the groove, of the first side face. The second doped semiconductor portion is disposed on the second region and a side of the isolation layer facing away from the semiconductor substrate. And the doping types of the second doped semiconductor part and the first doped semiconductor part are opposite.

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other, the first surface is provided with a first doped region and a second doped region which are arranged in a staggered mode, the second doped region comprises a contact region and isolation regions located on the two sides of the contact region, and the isolation regions are connected with the first doped region; the first doped layer is positioned in the first doped region; the first isolation layer is located in the isolation region; the second doping layer at least covers the contact region and one side, deviating from the semiconductor substrate, of the first isolation layer; the conduction type of the second doping layer is opposite to that of the first doping layer; and a first electrode and a second electrode, the first electrode being in electrical contact with the first doped layer, and the second electrode being in electrical contact with the second doped layer located in the contact region. The isolation effect can be improved.

The invention discloses a crystal growth device and a crystal growth method for gallium oxide crystal downward growth, and belongs to the technical field of gallium oxide single crystal preparation. The device comprises a crucible, an upper shaft, a heating mechanism and a heat preservation mechanism, the crucible is composed of a metal layer and an isolation layer arranged on the inner side wall of the metal layer, an opening is formed in the top of the metal layer, the thermal expansion coefficient of the side, away from the metal layer, of the isolation layer ranges from 0.5 * 10 <-6 > k <-1 > to 2.5 * 10 <-6 > k <-1 >, and the thermal expansion coefficient of the isolation layer is gradually increased outwards from the side, away from the metal layer, of the isolation layer. The rising rate is 2 * 10 <-6 >-3 * 10 <-6 > k <-1 > / mm; the upper shaft is arranged above an opening of the crucible and can lift and rotate relative to the crucible, a seed crystal support is arranged below the upper shaft, a first cooling pipeline is arranged in the upper shaft, and a second cooling pipeline is arranged in the seed crystal support. The crystal growth device breaks through the limitation of a traditional Czochralski method, a casting method and a Bridgman method, realizes downward growth of crystals, and can reduce the influence of crucible metal impurities on the crystals, so that gallium oxide single crystals with high quality, large size and high yield are obtained.

Various embodiments of the utility model relate to a semiconductor device, the semiconductor device comprises a plurality of photodiode doped regions formed in a substrate and a deep trench isolation (DTI) structure formed in the substrate, the DTI structure separates the photodiode doped regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material comprises a top, a side wall and a bottom. The semiconductor device also includes a first isolation layer surrounding and contacting the top, sidewalls, and bottom of the first fill material.

Integrated circuit structures having void-free internal spacers, and methods of fabricating integrated circuit structures having void-free internal spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent nanowires of the stack of horizontal nanowires and laterally adjacent to the gate structure. An epitaxial source or drain structure is coupled to an end of the stack of horizontal nanowires and in contact with the internal gate spacer. A dielectric structure is beneath and in contact with the epitaxial source or drain structure, the dielectric structure including a same material as the internal gate spacer, and the dielectric structure not including a seam therein.

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the steps of forming a first fin-shaped structure, a middle lamination layer and a second fin-shaped structure on a substrate; forming a first power rail structure; performing fin cutting processing on the first front source drain region to form a first gap; forming a first intermediate isolation layer based on the first gap; etching the first intermediate isolation layer in the first front source-drain region to form a second gap; forming a front metal electric connection layer based on the second gap; forming a first semiconductor structure; reversing the wafer and removing the substrate; forming a second power rail structure; performing fin cutting processing on the first back source-drain region and the second back source-drain region to form a third gap; forming a second intermediate isolation layer based on the third gap; etching the second intermediate isolation layer in the second back source-drain region to form a fourth gap; forming a back metal electric connection layer based on the fourth gap; and forming a second semiconductor structure.