4346 results about "Gate dielectric" patented technology

Gate isolation processes (e.g., gate-to-source / drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

The invention provides a planar gate silicon carbide VDMOS capable of improving short circuit reliability and a preparation method, and the preparation method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming drain electrode metal; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a current sharing layer; forming a barrier layer on the drift layer, and performing etching and ion implantation to form a P-type well region and a low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region and a P-type source region are formed; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a first gate dielectric layer; depositing to form a second gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; and re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, and removing the barrier layer to complete preparation. And the heat conduction capability and the thermal reliability of the insulating medium are effectively improved.

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a current sharing layer, a body region, a P-type well region and an N-type source region are formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; a barrier layer is formed again, and etching and deposition are carried out to form a gate dielectric layer; the preparation method comprises the following steps: forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, removing the barrier layer, and completing the preparation. The gate reliability of the device can be effectively improved, and the follow current loss and reverse recovery speed of a body diode can be effectively improved.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises an active structure and a first sacrificial layer; forming a pseudo gate structure covering the stacked structure in the gate region; etching the stack structure which is not covered by the pseudo gate structure to form a first deep groove; epitaxially growing a first source drain structure in the first deep groove based on the first active structure in the gate region; removing the pseudo gate structure and the first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; reversing and removing the semiconductor substrate; epitaxially growing a second source drain structure in the first deep groove based on a second active structure in the gate region; and depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a gate structure and a side wall on the substrate, and enabling the gate structure to comprise a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer; forming a first patterned photoresist layer covering the NMOS region; forming grooves in the substrate at two sides of the gate structure in the PMOS region, and reserving an amorphous carbon layer with a partial thickness on the second hard mask layer; the first patterned photoresist layer is removed; and removing the amorphous carbon layer by adopting an ashing process. In the process of forming the groove in the PMOS region, the amorphous carbon layer protects the second hard mask layer below the amorphous carbon layer from being thinned, and after the amorphous carbon layer is removed, the thickness of the second hard mask layer in the two regions can be ensured to be consistent, so that the height of the dummy gate is ensured to be consistent, and the electrical performance of the device is improved.

A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source / drain epitaxial layers on opposite sides of the first channel layer; forming second source / drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.

The invention relates to an enhanced gallium nitride high-mobility transistor and a preparation method thereof. The transistor sequentially comprises a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer from bottom to top, the source electrode and the drain electrode are respectively in ohmic contact with the two-dimensional electron gas, and the grid electrode and the p-GaN layer are in Schottky contact, so that the two-dimensional electron gas below the grid electrode is exhausted to realize normal closing; an electrode is arranged in a region between the grid electrode and the drain electrode, a thin-layer medium is arranged below the electrode, and the thin-layer medium and the electrode form an equivalent MIS grid structure; and the electrode is electrically connected with the source electrode. The switching time of the device is determined by the switching speed of the p-GaN HEMT composed of S-G1-D. Compared with a traditional Si MOS cascade structure, the device has the advantages of being fast in switching and free of reverse recovery charges. And meanwhile, the withstand voltage of the device is determined by a depletion mode MIS GaN HEMT consisting of S-G2-D, and the p-GaN grid does not bear high voltage, so that the device has the advantage of high reliability.

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The invention provides a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, forming a plurality of N-type body regions and a plurality of diffusion regions, and forming a P-type well region, an N-type source region and a current sharing layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps of: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

The invention relates to the technical field of semiconductors, in particular to a VDMOS semiconductor power device and a preparation method thereof, and the VDMOS semiconductor power device comprises a semiconductor substrate and a semiconductor epitaxial layer. The well region is positioned in the semiconductor epitaxial layer; the source region is positioned in the well region; the local thick oxygen layer is positioned below the grid electrode between the adjacent well regions on the semiconductor epitaxial layer; the gate dielectric layer is positioned below the gate between the adjacent source regions on the semiconductor epitaxial layer; the grid electrode is positioned above the grid dielectric layer and the local thick oxygen layer; wherein the local thick oxygen layer is formed before diffusion of the well region. The VDMOS semiconductor power device adopts a gate-last oxide process and is provided with a local thick oxygen layer structure, and the local thick oxygen layer structure is formed before well region diffusion, so that the LOCOS boron absorption and phosphorus discharge effect is effectively avoided, and the reliability and the electrical property of the device are improved.

A semiconductor device includes a top transistor, a bottom transistor, an isolation box between the top transistor and the bottom transistor, a first gate dielectric, and a second gate dielectric. First portions of the first gate dielectric cover a top surface and top-half of sidewalls of the isolation box, and first portions of the second gate dielectric cover a bottom surface and bottom-half of the sidewalls of the isolation box.

The invention provides a semi-super-junction high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a first drift region; a barrier layer is formed, etching and ion implantation are carried out, and a column region is formed; the barrier layer is removed, epitaxial growth is carried out on the first drift region, a second drift region is formed, and the drift layer comprises the first drift region and the second drift region; forming a barrier layer, etching, performing ion implantation, and forming a first P-type well region, a lug boss, a second P-type well region, an N-type source region and a Schottky region; re-forming a barrier layer, etching and depositing to form a gate dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: re-forming a barrier layer, etching, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that dual protection can be provided during reverse voltage withstanding, and the reliability of the device is improved.

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. The MOSFET comprises a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor contact region, a first groove, a first conductive type carrier diffusion layer, a second groove, a second conductive type semiconductor shielding region, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole. And a source end metal electrode and a drain end metal electrode. A first conductive type semiconductor carrier diffusion layer (CSL) is prepared in a local region of the bottom and the side wall of a first groove, so that the specific on-resistance (Ron, sp) of the device is reduced; second conductive type semiconductor shielding regions short-circuited with the source end metal electrode are prepared in all regions of the bottom and the side wall of the second groove, so that the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, and the reliability of the device is improved.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

The invention discloses a quasi one-dimensional (TaSe4) 2I and two-dimensional MoTe2 mixed-dimensional heterojunction phototransistor detector and a preparation method thereof, the detector sequentially comprises a Si substrate, a SiO2 gate dielectric layer, a quasi one-dimensional (TaSe4) 2I and two-dimensional MoTe2 nano film from bottom to top, the quasi one-dimensional (TaSe4) 2I and MoTe2 nano film are respectively provided with a metal electrode, and a heterostructure of the (TaSe4) 2I, the MoTe2 and the metal electrodes is formed. The preparation method comprises the following steps: (1) transferring the (TaSe4) 2I nanowire to the Si substrate; (2) transferring the MoTe2 nano film to one side of the (TaSe4) 2I nanowire; (3) preparing a pattern of a bottom electrode; (4) positioning, exposing and developing the pattern of the bottom electrode to expose the electrode part needing to be evaporated; and (5) preparing a metal electrode. According to the invention, the composite effect of a (TaSe4) 2I / MoTe2 heterojunction is utilized, and dark current is inhibited through a vertical structure; moTe2 is utilized to increase light absorption, and meanwhile, grid voltage is applied, so that light current is improved, and high responsivity and external quantum efficiency are obtained.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

The invention discloses a low contact resistance thin film transistor and a preparation method thereof, and the thin film transistor comprises a substrate; a gate electrode on the substrate; the gate dielectric layer is positioned on the gate electrode; the channel layer and the source and drain electrodes are located on the gate dielectric layer; the source electrode and the drain electrode are separated by the channel layer, and the channel particle layers are located between the source electrode and the drain electrode and the channel layer respectively. The metal oxide layer is formed on the contact interface of the channel layer and the source and drain electrodes of the thin film transistor, so that the contact resistance of the thin film transistor is greatly reduced.

In an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.

The invention provides a semi-super junction side isolation planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth to obtain a first drift region; performing ion implantation to form a first source region; depositing to form a first insulating dielectric layer; epitaxially forming a second drift region, wherein the drift layer comprises a first drift region and a second drift region; performing ion implantation to form a second source region, wherein the P-type source region comprises a first source region and a second source region; depositing to form a second insulating medium layer, wherein the insulating medium region comprises the first insulating medium layer and the second insulating medium layer; forming a barrier layer again, and performing etching and ion implantation to form a column region, a P-type well region, a lug boss and an N-type source region; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer and a source metal layer; the voltage endurance capability of the device is effectively improved, and the on-resistance of the device is reduced.

The invention discloses an ultra-steep sub-threshold slope transistor and a preparation method thereof, and belongs to the technical field of integrated circuits. An ultra-steep sub-threshold slope transistor is realized by using a superlattice stacked high-kappa gate dielectric, the superlattice stacked high-kappa gate dielectric comprises a plurality of HfO2 / ZrO2 / HfO2 stacking units which are stacked together, and an insertion layer is arranged between every two adjacent stacking units. Growing the superlattice stacked high-kappa gate dielectric by adopting an atomic layer deposition method, performing annealing treatment, and adjusting the gate dielectric interface, the electric leakage characteristic and the proportion of a ferroelectric quadrature phase to an antiferroelectric tetragonal phase by adjusting the type of an insertion layer and / or adjusting an oxygen source and pulse time thereof during growth, so as to obtain the superlattice stacked high-kappa gate dielectric. An ultra-steep sub-threshold slope transistor with a high on-off ratio is achieved. Compared with a traditional transistor, the transistor provided by the invention has higher on-state current, lower sub-threshold swing and smaller electric leakage.

The invention belongs to the technical field of semiconductor devices, and discloses a diamond-based CMOS (complementary metal oxide semiconductor) inverter and a preparation method thereof. The diamond-based CMOS inverter comprises a diamond substrate, a monocrystalline diamond film, a hydrogen terminal region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer and a second gate electrode. The first drain electrode and the second drain electrode are in metal interconnection; the first gate electrode and the second gate electrode are metal-interconnected. The diamond-based CMOS phase inverter is prepared by combining the p-type hydrogen terminal diamond and the n-type oxide semiconductor, so that the technical problem that an n-type MOS device is difficult to realize by the diamond at present is effectively avoided, respective advantages of the diamond and the n-type oxide semiconductor are fully exerted, and the high-performance diamond-based monolithic integrated CMOS phase inverter is realized.

The invention discloses a multi-time programmable device and electronic equipment. The multi-time programmable device comprises a semiconductor layer; the well region and the isolation structure are located in the semiconductor layer, and the isolation structure surrounds the well region; the selection transistor and the floating gate transistor are formed in the well region, and a floating gate of the floating gate transistor extends to the position above the isolation structure from the position above the well region; the control gate is located above the isolation structure, and the control gate is opposite to the floating gate in the horizontal direction; wherein the floating gate and the control gate are isolated through an inter-gate dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate form a capacitor structure, and the control gate controls the potential of the floating gate. According to the multi-time programmable device, the size of the device is reduced, and the coupling ratio between the control gate and the floating gate is increased.

The invention discloses a power MOSFET and a preparation method thereof, and belongs to the technical field of microelectronics. The power MOSFET comprises a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer which are arranged from bottom to top, wherein the top surface of the Ga2O3 epitaxial layer is provided with a groove, and an oxide isolation layer is arranged in the groove; the drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxide isolation layer; the source electrode is arranged in the middle area of the other side of the Ga2O3 epitaxial layer; second grooves are formed in the two sides of the source electrode; a NiO layer and an insulated gate dielectric layer are arranged on the second groove from bottom to top; a gate electrode with a non-planar gate structure is arranged on the insulated gate dielectric layer; and a gap part around the second groove and the gate electrode is filled with a first oxide isolation layer. Through structural design and material selection, the problems of serious heat dissipation and gate electrode electric leakage of existing similar devices are solved, and the voltage withstanding performance of the device is improved.

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

A semiconductor device and methods for forming the semiconductor device are described. The semiconductor device can include a top transistor and a bottom transistor arranged in a stack configuration, and an isolation layer situated between the top transistor and the bottom transistor. The top transistor can be encompassed by a high-k gate dielectric. The bottom transistor can be encompassed by a metal-doped high-k gate dielectric. A first portion of the isolation layer can be encompassed by the high-k gate dielectric. A second portion of the isolation layer can be encompassed by the metal-doped high-k gate dielectric. The metal-doped high-k gate dielectric can encompass the bottom transistor and the second portion of the isolation layer can be encompassed by a layer of first work function material (WFM). The first WFM can be encompassed by a second WFM.