1797 results about "Gate dielectric" patented technology

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

An example thin-film transistor includes a source and a gate. The source includes a body of source metal and a body of capacitance-tuning material disposed on the body of source metal. The body of capacitance-tuning material is configured to control a capacitance between the source and the gate. A drain of the thin-film transistor may also include a body of capacitance-tuning material. Capacitance-tuning material may be provided outside the source / drain, for example, adjacent a gate dielectric material. The thin-film transistor may further include a body of reducing material to draw oxygen out of other materials of the thin-film transistor. The thin-film transistor may further include a body of hardmask material used during the making of the thin-film transistor.

The invention relates to a p-type niobium oxide dipole-based metal-oxide-semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor device manufacturing. According to the technical scheme, the MOS device is provided. A gate dielectric stack of the MOS device sequentially comprises an interface layer, a high-k dielectric layer and a p-type electric dipole layer containing niobium oxide from bottom to top. According to the preparation method, the dipole layer is deposited by adopting an atomic layer deposition process, and then atoms in the dipole layer are driven to be diffused to the interface of the high-k dielectric layer and the interface layer through high-temperature rapid annealing treatment so as to form effective electric dipoles. Compared with the prior art, the high dielectric constant characteristic is utilized, the threshold voltage can be positively regulated and controlled to a larger extent, meanwhile, the increase of EOT is remarkably inhibited, and good interface quality is kept.

The invention discloses a comprehensive two-dimensional vertical structure metal-semiconductor field effect transistor and a preparation method thereof. A source electrode, a lower isolation layer, a drain electrode and an upper isolation layer which are vertically stacked are formed on the surface of a substrate, an inclined side wall is formed, a channel covers the inclined side wall, a grid electrode and the channel are self-aligned, and a semi-metal grid electrode and a semiconductor channel are in direct contact to form a Schottky junction; based on a comprehensive two-dimensional material system, the Fermi pinning effect and unintentional doping are effectively inhibited, and the performance of the device is optimized by optimizing the grid control capability and the electric contact performance; a gate dielectric layer is not arranged, so that the problems of electrical performance deterioration and the like under a limit miniature scale are avoided; the integration density of the device is improved and the research and development and manufacturing cost is controlled while excellent performance is kept; the channel length and the contact length are synchronously and accurately reduced by utilizing a side wall vertical structure; the method is applied to the industrial application fields of next-generation integrated circuit chips, high-density memories, flexible and wearable electronics and the like which break through the silicon-based physical limit.

The invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; forming a laminated structure formed by alternately stacking a plurality of semiconductor material layers and a plurality of insulating material layers on the substrate; channel region laminations and an initial gate column are formed in the lamination structure, the initial gate column at least comprises an initial gate conductive layer and an initial gate dielectric layer, the initial gate column is provided with two opposite first side walls which are in contact with the two adjacent channel region laminations respectively, and a second side wall is not in contact with the channel region laminations; at least removing the gate dielectric layer and the gate conductive layer on the second side wall to form a target gate column, the target gate column having two opposite third side walls in contact with the two adjacent channel region lamination layers, the gate conductive layer on the third side walls having a first length and the gate dielectric layer having a second length, the first length being smaller than the second length, the semiconductor structure with relatively high performance can be obtained through the manufacturing method.

The invention relates to a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a substrate, a first dielectric layer, a first gate structure and a second gate structure, and an epitaxial layer is arranged in the substrate; the first gate structure is located in the substrate below the epitaxial layer and comprises a first gate, a first gate dielectric layer and a second gate dielectric layer, the second gate dielectric layer is located between the first gate and the epitaxial layer, and the first gate dielectric layer covers the side wall and the bottom of the first gate; the second gate structure is located on the substrate, and the orthographic projection of the second gate structure towards the surface of the substrate partially coincides with the orthographic projection of the first gate structure towards the surface of the substrate. According to the semiconductor device and the manufacturing method thereof, the leakage current of the substrate is reduced, the current and voltage of the semiconductor device are accurately controlled, the performance of the semiconductor device is improved, the noise of the semiconductor device is effectively reduced, and the frequency band of the semiconductor device is expanded.

The invention discloses a transistor structure and a manufacturing method thereof. The transistor structure comprises a substrate, an isolation structure, a first epitaxial layer, a second epitaxial layer, a gate dielectric layer and a gate. The isolation structure is in the substrate. The isolation structure defines an active region in the substrate. The isolation structure has a first recess and a second recess on both sides of the active region. The first recess and the second recess respectively expose a first sidewall and a second sidewall of the substrate in the active region. The first epitaxial layer and the second epitaxial layer are located on the first side wall and the second side wall respectively. The first epitaxial layer is located in the first recess and on the isolation structure. The second epitaxial layer is located in the second recess and on the isolation structure. The gate dielectric layer is located on the substrate, the first epitaxial layer and the second epitaxial layer. The gate electrode is located on the gate dielectric layer. The transistor structure can effectively reduce the leakage current.

The invention relates to an oxychloride gate dielectric material and a preparation method and application thereof. The preparation method comprises the following steps: respectively placing a chloride precursor and a substrate material at the bottom and a single-side opening of a same reaction container with a single-side opening, and placing the reaction container with an opening at one side in a chemical vapor deposition device, with the opening positioned at one side of a vent in the chemical vapor deposition device, regulating the relative humidity of the reaction chamber, and depositing on the surface of the substrate material to obtain the oxychloride gate dielectric material. According to the invention, a chemical vapor deposition preparation process is adopted to control and obtain the oxychloride gate dielectric material with controllable and uniform morphology, so that the problems of random shape and non-uniform morphology of the oxychloride gate dielectric material in the chemical vapor deposition process are solved, the controllable growth of the material is realized, and the material has a high dielectric constant; the material also has an atomic-scale flat surface and is applied to a transistor device and / or a capacitor device, and the device has higher performance.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

A method is provided that includes providing a substrate having an N-type region for n-type field effect transistors (nFETs) and a P-type region for p-type field effect transistors (pFETs); forming a gate dielectric layer in the N-type region and the P-type region to wrap the vertically stacked channels; performing dipole processing on the first part of the gate dielectric layer in the N-type region, and keeping the second part of the gate dielectric layer in the P-type region unprocessed; depositing a P-type metal layer in the gate dielectric layer of the P-type region and the N-type region; and forming a filling metal layer on the P-type metal layer of the P-type region and the N-type region.

A string driver device is described in this disclosure. The string driver device includes a semiconductor channel disposed in an upper portion of a semiconductor substrate and a gate dielectric layer disposed above the semiconductor channel. The string driver device also includes a source region and a drain region disposed at opposite sides of the semiconductor channel, each of the source region and the drain region having a corresponding contact disposed thereon. The string driver device further includes a gate that is disposed above the gate dielectric layer and has a first length, and a field plate layer disposed above the gate, the field plate layer having a second length larger than the first length of the gate, wherein the field plate layer includes one or more edge regions extending across the semiconductor channel edge and toward the source region or the drain region.

The invention discloses a trench separation gate field effect transistor. The trench separation gate field effect transistor comprises a multi-stage step trench structure. The first-stage groove structure comprises a gate dielectric layer formed on the side face of the gate groove, a first dielectric layer on the surface of the bottom and a filled gate conductive material layer. The second-stage groove structure comprises a plurality of source electrode grooves, source dielectric layers and source electrode conductive material layers, wherein the source dielectric layers and the source electrode conductive material layers are formed in the source electrode grooves. First spacer regions are arranged among the source trenches, and the sum of the widths of all the source trenches and the first spacer regions is smaller than the width of the gate trench. A first buried layer and a second buried layer doped with a first conductive type and a second conductive type are formed at the top and the bottom of the first spacer region, and the second buried layer further wraps the bottom corners of the adjacent source trenches on the two sides. The gate conductive material layer is connected to the gate. Each source conductive material layer, the first buried layer and the second buried layer are connected to a source. The invention further discloses a manufacturing method of the trench separation gate field effect transistor. The invention can reduce the electric field intensity at the bottom of the gate trench.

Dipole engineering techniques for stacked device structures are disclosed herein. According to various aspects of the present disclosure, an exemplary dipole engineering technique includes (1) forming at least two patterned dipole dopant source layers having different patterns and covering gate dielectric layers of some transistors, but not other transistors, (2) performing a thermal drive-in process (e.g., a dipole drive-in anneal), and (3) after removing the dipole dopant source layer, forming gate electrodes for the transistors, where a same gate electrode material is used for the transistors. Thickness(es) and / or material characteristics (e.g., dipole dopant) of the patterned dipole dopant source layers and / or parameters of the thermal drive-in process may be configured to achieve desired threshold voltages. Such technique may provide 2N threshold voltages (Vt), where N is a number of patterned dipole dopant source layers formed on the gate dielectric layers of the transistors to tune their threshold voltages.

A stack of semiconductor layers is formed. The semiconductor layers are spaced apart from one another in a vertical direction by a plurality of gaps in a cross-sectional side view. A plurality of gate dielectric layers is formed over the semiconductor layers. Each of the gate dielectric layers circumferentially surrounds a respective one of the semiconductor layers, and the gate dielectric layers are still spaced apart from one another in the vertical direction by the gaps in the cross-sectional side view. A dipole layer is formed that circumferentially surrounds each of the gate dielectric layers in the cross-sectional side view. The dipole layer contains dopants. The gaps are filled by different portions of the dipole layer in the cross-sectional side view. One or more annealing processes is performed to drive dopants of the dipole layer into the gate dielectric layers. The dipole layer is then removed.

The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention discloses a sensor for detecting gas based on a two-dimensional material, and relates to the technical field of semiconductor sensors and battery safety. In order to solve the problems that an existing lithium ion battery management system lags in early warning and a traditional sensor is difficult to integrate and not resistant to corrosion, flexible polyimide is used as a substrate of the sensor, a back gate type two-dimensional material field effect transistor serves as a core, and a gate dielectric layer is arranged between a gate and a two-dimensional material channel in a spaced mode. A functional modification layer is arranged on the surface of the channel to improve the gas recognition specificity, a breathable hydrophobic layer covers one side deviating from the gate dielectric layer, and the breathable hydrophobic layer is matched with a passivation layer and a sensing window to form anti-corrosion packaging. The sensor can be implanted into a battery, real-time in-situ detection of ppb-level trace characteristic gas is realized through an adsorption-charge transfer-field effect amplification mechanism, and the sensor is linked with a BMS (Battery Management System) to realize ultra-early warning of thermal runaway. The device has the advantages of flexibility, easiness in integration, high sensitivity, corrosion resistance and long service life, and the safety management level of the battery is greatly improved.

An NCFET transistor comprises a semiconductor-on-insulator substrate for a field-effect transistor, and the NCFET transistor successively comprises, from its base to its surface: a semiconductor carrier substrate; a single ferroelectric layer, arranged in direct contact with the carrier substrate, which layer is designed to be biased so as to form a negative capacitance; and an active layer of a semiconductor material, which layer is designed to form the channel of the transistor, and is arranged in direct contact with the ferroelectric layer. The NCFET transistor further comprises a channel that is arranged in the active layer, a source and a drain that are arranged in the active layer on either side of the channel, and a gate that is arranged on the channel and is insulated from the channel by a gate dielectric.

The invention discloses a composite JTE structure for a silicon carbide VDMOS and a preparation method of the composite JTE structure. The composite JTE structure comprises an N + substrate; an N-drift layer; a JTE3 region; the JTE3 protection ring region is arranged at the right end of the upper surface of the N-drift layer; the source P-doped region is arranged at the left end of the upper surface of the N-drift layer; the JTE2 region is connected with the JTE3 region; a JTE2 step protection ring; the JTE1 region is connected with the JTE2 region; a JTE1 step protection ring; the P + doped region is arranged between the source P-doped region and the JTE1 region; the source N + doped region is connected with the P + doped region; the sawtooth transition region is arranged on the JTE1 region; the high-K dielectric layer is arranged on the JTE structure; the gate dielectric layer is arranged on the N-drift layer, the source P-doped region and the source N + doped region; the gate metal is arranged on the gate dielectric layer; the gate masking layer is arranged on the gate metal; and the source metal and the field plate are arranged on the grid masking layer, the source N + doped region and the P + doped region. According to the invention, process steps are reduced.

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source / drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having nanoribbons selectively removed to allow for thicker gate dielectric materials. In forming an alternating stack of semiconductor and sacrificial layers, a cladding layer is applied to those semiconductor layers to be removed during nanoribbon release. Prior to nanoribbon release, atoms of the cladding layer are diffused into only those semiconductor layers having the cladding. During nanoribbon release etch, the sacrificial layers and those semiconductor layers having diffused atoms therein are removed while the semiconductor layers without cladding remain. By removing nanoribbons, an increased ribbon-to-ribbon spacing is attained for application of thicker gate dielectric materials in gate all around field effect transistors.

The invention provides a gallium oxide power device and a manufacturing method thereof, and relates to the technical field of semiconductors, and the gallium oxide power device comprises a drain electrode, an n-doped gallium oxide substrate and an n-type gallium oxide drift region, the drift region comprises a first n-type gallium oxide drift region, a second n-type gallium oxide drift region and a fin-shaped channel; a high-k gate dielectric layer, a gate electrode, an insulating layer and a source electrode are sequentially arranged on two sides of the fin-shaped channel; an n-type heavily-doped top contact region is arranged in the middle of the insulating layer; in the first direction, the second n-type gallium oxide drift region, the fin-shaped channel and the n-type heavily doped top contact region are sequentially arranged in a laminated manner; the maximum height of the high-k gate dielectric layer is equal to the maximum height of the fin-shaped channel, and the maximum height of the gate is equal to the difference between the maximum height of the fin-shaped channel and the thickness of the high-k gate dielectric layer; the maximum height of the first n-type gallium oxide drift region is equal to that of the second n-type gallium oxide drift region; and the width of the second n-type gallium oxide drift region in the second direction is greater than that of the fin-shaped channel.

Methods of forming gate structures for stacked multi-gate devices are provided. A method according to the present disclosure includes forming a gate dielectric layer to wrap around a bottom channel member and a top channel member, depositing a dipole layer over the gate dielectric layer, forming a dummy layer such that the top channel member is disposed above the top surface of the dummy layer, removing the dipole layer around the top channel member, forming a self-assembled monolayer (SAM) on the top surface of the dummy layer, depositing a hard mask layer to wrap over the top channel member, removing the SAM and the dummy layer, performing a thermal drive-in process to drive a dipole dopant species from the dipole layer into the gate dielectric layer around the bottom channel member, removing the hard mask layer, and removing the dipole layer.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a semiconductor layer; a well region in the semiconductor layer; the source region is located in the well region; the gate dielectric layer is located on the semiconductor layer; the plurality of gate conductors are positioned on the gate dielectric layer; the grid connecting part is respectively connected with the grid conductors, the grid connecting part is provided with a plurality of holes, and each hole increases the equivalent resistance by reducing the cross sectional area of the grid connecting part, so that the plurality of equivalent resistors are respectively connected in series on a conduction path of the corresponding grid conductor and the grid connecting part; by adjusting the number, the distribution density and the arrangement mode of the holes, the uniformity of resistance between cells at different positions can be realized, so that the switching speed is balanced, and the internal oscillation is reduced.

A semiconductor structure includes: a substrate; and gate-all-around transistors on the substrate. Each gate-all-around transistor includes: a discrete protrusion on the substrate; a channel structure layer spaced apart from and suspended on the protrusion, including channel layers longitudinally stacked at intervals along a direction perpendicular to a surface of the substrate, a distance between the protrusion and a channel layer adjacent to the protrusion being larger than a distance between adjacent channel layers along the direction perpendicular to the surface of the substrate; a gate structure crossing the channel structure layer and surrounding each channel layer in the channel structure layer; a gate dielectric layer between the gate structure and the channel layers, and between the gate structure and the protrusion; and source-drain doped regions on the protrusion at two sides of the gate structure and in contact with ends of each channel layer along an extension direction.

The invention provides a semiconductor device threshold voltage control method, system and equipment and a medium, and the control method comprises the steps: manufacturing a gate dielectric layer, and measuring and obtaining the first thickness of the gate dielectric layer; forming a gate polycrystalline silicon layer on the basis of the gate dielectric layer, oxidizing the surface of the gate polycrystalline silicon layer to obtain an ion barrier layer, and measuring and obtaining a second thickness of the polycrystalline silicon layer and a third thickness of the ion barrier layer; and determining the ion implantation amount of grid pre-doping according to the first thickness, the second thickness and the third thickness so as to perform ion implantation on the grid polycrystalline silicon layer, so that the threshold voltage of the device after grid pre-doping is kept within a preset target voltage range. According to the method, the pre-doped threshold voltage can be dynamically adjusted under the condition of not increasing any device manufacturing process steps, and the threshold voltage control precision and the product stability are guaranteed.

The embodiment of the invention provides a wafer bonding method, a manufacturing method of a gate-all-around transistor and a product. The wafer bonding method comprises the following steps: providing a semiconductor material donor wafer and a support wafer, forming a first dielectric layer on the support wafer, and forming a second dielectric layer on one side, to be bonded to the support wafer, of the semiconductor material donor wafer; performing chemical mechanical polishing on the first dielectric layer to form a first bonding surface, and performing chemical mechanical polishing on the second dielectric layer to form a second bonding surface; and bonding the support wafer and the semiconductor material donor wafer through the first bonding surface and the second bonding surface. The manufacturing method of the transistor comprises the following steps: thinning a target semiconductor material layer in a semiconductor material donor wafer; and defining a source region, a drain region and a channel region of the transistor, and enabling the channel region to be separated from the buried oxide layer and suspended. And depositing a gate dielectric layer, defining a gate region and depositing gate metal. And carrying out ion implantation and annealing. And opening holes in the source region and the drain region, and depositing a source region electrode and a drain region electrode.

According to the preparation method of the semiconductor structure and the semiconductor structure provided by the invention, the longitudinal space of a chip is fully utilized, and a gate dielectric layer, an active layer and a first source-drain layer are sequentially formed on a shallow trench isolation structure in a substrate, so that a longitudinally arranged high-voltage gate oxide layer MOS (Metal Oxide Semiconductor) tube is formed; therefore, the transverse area of the high-voltage gate oxide layer MOS tube is reduced, and the integration level of a chip where the high-voltage gate oxide layer MOS tube is located is improved. As the high-voltage gate oxide MOS tube is positioned above the shallow trench isolation structure in the substrate and is positioned on a different horizontal plane from the first MOS tube positioned in the substrate in the chip, the interference of the high-voltage gate oxide MOS tube on the adjacent first MOS tube is reduced. Therefore, an isolation structure does not need to be arranged between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube, the horizontal distance between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube is reduced, the overall area of a chip is reduced, the integration degree of the chip is further improved, and the preparation cost of the chip is reduced.