3089 results about "Gate dielectric" patented technology

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

A semiconductor device includes a top transistor, a bottom transistor, an isolation box between the top transistor and the bottom transistor, a first gate dielectric, and a second gate dielectric. First portions of the first gate dielectric cover a top surface and top-half of sidewalls of the isolation box, and first portions of the second gate dielectric cover a bottom surface and bottom-half of the sidewalls of the isolation box.

The invention provides a semi-super-junction high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a first drift region; a barrier layer is formed, etching and ion implantation are carried out, and a column region is formed; the barrier layer is removed, epitaxial growth is carried out on the first drift region, a second drift region is formed, and the drift layer comprises the first drift region and the second drift region; forming a barrier layer, etching, performing ion implantation, and forming a first P-type well region, a lug boss, a second P-type well region, an N-type source region and a Schottky region; re-forming a barrier layer, etching and depositing to form a gate dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: re-forming a barrier layer, etching, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that dual protection can be provided during reverse voltage withstanding, and the reliability of the device is improved.

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

Dipole engineering techniques for devices of stacked device structures are disclosed herein. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. A drive-in temperature of the thermal drive-in process is less than 600° C. (e.g., about 300° C. to about 500° C.). The p-dipole dopant can be titanium. The method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k / interfacial interface ±0.5 nm.

The invention discloses a quasi one-dimensional (TaSe4) 2I and two-dimensional MoTe2 mixed-dimensional heterojunction phototransistor detector and a preparation method thereof, the detector sequentially comprises a Si substrate, a SiO2 gate dielectric layer, a quasi one-dimensional (TaSe4) 2I and two-dimensional MoTe2 nano film from bottom to top, the quasi one-dimensional (TaSe4) 2I and MoTe2 nano film are respectively provided with a metal electrode, and a heterostructure of the (TaSe4) 2I, the MoTe2 and the metal electrodes is formed. The preparation method comprises the following steps: (1) transferring the (TaSe4) 2I nanowire to the Si substrate; (2) transferring the MoTe2 nano film to one side of the (TaSe4) 2I nanowire; (3) preparing a pattern of a bottom electrode; (4) positioning, exposing and developing the pattern of the bottom electrode to expose the electrode part needing to be evaporated; and (5) preparing a metal electrode. According to the invention, the composite effect of a (TaSe4) 2I / MoTe2 heterojunction is utilized, and dark current is inhibited through a vertical structure; moTe2 is utilized to increase light absorption, and meanwhile, grid voltage is applied, so that light current is improved, and high responsivity and external quantum efficiency are obtained.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

The invention provides a semi-super junction side isolation planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth to obtain a first drift region; performing ion implantation to form a first source region; depositing to form a first insulating dielectric layer; epitaxially forming a second drift region, wherein the drift layer comprises a first drift region and a second drift region; performing ion implantation to form a second source region, wherein the P-type source region comprises a first source region and a second source region; depositing to form a second insulating medium layer, wherein the insulating medium region comprises the first insulating medium layer and the second insulating medium layer; forming a barrier layer again, and performing etching and ion implantation to form a column region, a P-type well region, a lug boss and an N-type source region; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer and a source metal layer; the voltage endurance capability of the device is effectively improved, and the on-resistance of the device is reduced.

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

A semiconductor device and methods for forming the semiconductor device are described. The semiconductor device can include a top transistor and a bottom transistor arranged in a stack configuration, and an isolation layer situated between the top transistor and the bottom transistor. The top transistor can be encompassed by a high-k gate dielectric. The bottom transistor can be encompassed by a metal-doped high-k gate dielectric. A first portion of the isolation layer can be encompassed by the high-k gate dielectric. A second portion of the isolation layer can be encompassed by the metal-doped high-k gate dielectric. The metal-doped high-k gate dielectric can encompass the bottom transistor and the second portion of the isolation layer can be encompassed by a layer of first work function material (WFM). The first WFM can be encompassed by a second WFM.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

Method to selectively diffuse dipole dopants into the high-k gate dielectric layer is provided. A method of the present disclosure includes an etching back process controlling DC and bias power, a periodical switching of the bias power is synchronized with a periodical switching of the DC power, leading to a balanced etching rate and uniform depth of recesses in dummy materials within the gate trenches for the subsequent selective diffusion process across different devices. Additionally, during the etching back process, a protective passivation layer can be formed as a barrier on the sidewall of the recess and / or at the bottom of the recess.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The utility model relates to a semiconductor structure. The semiconductor structure comprises a substrate; the source electrode, the grid electrode and the drain electrode are stacked on the substrate; the first isolation layer is arranged between the grid electrode and the drain electrode; the second isolation layer is arranged between the first isolation layer and the drain electrode; the channel layer penetrates through the grid electrode, the first isolation layer and the second isolation layer, and the channel layer is arranged on the source electrode; the gate dielectric layer is arranged between the gate and the channel layer; the insulating layer is arranged on the inner side of the channel layer; the contact pad is arranged on the insulating layer; the nitrogen component content of the second isolation layer is greater than the nitrogen component content of the first isolation layer. The second isolation layer protects the first isolation layer in the etching or grinding process, the first isolation layer is prevented from being damaged, the integrity of the semiconductor structure is protected, and the product yield of the semiconductor structure is improved.

Techniques are provided to form an integrated circuit having backside epaxially grown source or drain regions in addition to the frontside source or drain regions to reduce backside contact resistance. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The substrate beneath the semiconductor device may be removed from the backside to expose a subfin region beneath the semiconductor region. The subfin region may be removed using a backside etch to open a backside recess that exposes a bottom surface of a given frontside source or drain region. A backside source or drain region may be grown on a bottom surface of the given frontside source or drain region and remain within the backside recess or extend out of the backside recess.

The invention discloses a gate dielectric film growth process, an HEMT (High Electron Mobility Transistor) device and a preparation method, and the gate dielectric film growth process comprises the steps: executing a primary process cycle of atomic layer deposition, and forming an amorphous gate dielectric film on the surface of a substrate; after the primary process circulation is completed, in-situ gas plasma treatment is executed, a single crystal gate dielectric film converted from the amorphous gate dielectric film after treatment is obtained, and when the single crystal gate dielectric film is formed between a metal gate and a barrier layer of the HEMT device, the interface state of the metal gate at a gate groove can be improved, the quality of a contact interface below gate metal is improved, and the performance of the HEMT device is improved. And the defect density and the electron trapping effect are reduced, so that the problems of serious influence on safe operation of the device and even grid degradation caused by grid leakage and threshold voltage drift after stress of the device can be effectively avoided, and the performance of the device is improved.

A semiconductor device is disclosed. The semiconductor device includes a substrate, an active region in the substrate, a recessed region in the active region, a gate dielectric layer on the recessed region, a gate structure on the gate dielectric layer, and a source / drain region in the active region and at a side of the gate structure. An edge portion of the gate dielectric layer comprises a rounded profile, and the source / drain region directly contacts the edge portion of the gate dielectric layer.

The utility model provides a double-channel planar gate silicon carbide LDMOS. The double-channel planar gate silicon carbide LDMOS is characterized in that a first N-type source region is connected with a silicon carbide substrate; the first channel region is connected with the silicon carbide substrate and the first N-type source region; the isolation region is respectively connected with the first channel region, the first N-type source region and the second N-type source region; the second channel region is connected to the isolation region and the first N-type source region; the P-type well region is connected with the isolation region and the second channel region, and the P-type well region is connected to the first N-type source region; the second N-type source region is arranged in the first through hole, the second N-type source region is connected to the isolation region, the body diode metal layer is arranged in the second through hole, and the body diode metal layer is connected to the isolation region; the gate dielectric layer is connected with the P-type well region, the source metal layer is arranged in the third through hole, and the source metal layer is connected to the second N-type source region and the body diode metal layer; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the first N-type source region; double-channel structure design is carried out in the transverse power device, so that the on-resistance of the device is reduced.

The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.

The utility model provides a trench gate silicon carbide VDMOS with low on-resistance. The trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side of the P-type source region is connected to the upper side of the drift layer; the freewheeling region is connected to the drift layer, and the freewheeling region is connected to the P-type source region; a groove is formed in the follow current area, and a masking layer is arranged at the bottom of the groove; a P-type well region and an N-type source region are arranged in the follow current region, and the upper side surface of the P-type well region is connected to the lower side surface of the N-type source region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side of the gate dielectric layer is connected with the N-type source region and the P-type well region, and the lower side face of the gate dielectric layer is connected to the upper side face of the masking layer; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source electrode metal layer is respectively connected with the P-type source region, the follow current region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the on-resistance of the device can be effectively reduced, the body diode conduction loss of the device is reduced, and the switching speed of the device is improved.

An example thin-film transistor includes a source and a gate. The source includes a body of source metal and a body of capacitance-tuning material disposed on the body of source metal. The body of capacitance-tuning material is configured to control a capacitance between the source and the gate. A drain of the thin-film transistor may also include a body of capacitance-tuning material. Capacitance-tuning material may be provided outside the source / drain, for example, adjacent a gate dielectric material. The thin-film transistor may further include a body of reducing material to draw oxygen out of other materials of the thin-film transistor. The thin-film transistor may further include a body of hardmask material used during the making of the thin-film transistor.

A semiconductor device includes a source region, a drain region, and a gate dielectric layer formed on a substrate; a gate electrode formed on the gate dielectric layer; a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region to a portion of an upper surface of the gate electrode; a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region; and a gate silicide layer formed between the first dielectric pattern and the spacer.

The invention discloses a vacancy-based controllable doping p-type two-dimensional transistor and a preparation method thereof, and mainly solves the problem that accurate controllable doping is difficult to realize in the prior art. According to the scheme, the device comprises an insulating substrate, a two-dimensional material channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, wherein the source electrode and the drain electrode are located at the two ends of the two-dimensional material channel layer; the gate dielectric layer is located on the two-dimensional material channel layer and the source and drain electrodes; the method comprises the following steps: depositing a thick mask layer, thinning the mask layer part through photoetching and etching to form a patterned thin layer, bombarding a two-dimensional material and a two-dimensional material under a mask plate thin layer through treated mask layer ions to form a surface vacancy, removing a mask plate, exposing the two-dimensional material in an oxygen flow, and oxidizing to form surface charge transfer doping. According to the invention, under the condition that the two-dimensional material is not damaged and the performance is not influenced, partitioned controllable doping is realized, and the conductivity of the two-dimensional transistor is effectively improved.

A method of fabricating a semiconductor device can include providing a substrate, etching the substrate from a first side to form at least one vertical pillar having a first and a second end, forming at least one gate line on a gate dielectric layer formed on sidewalls of the at least one vertical pillar, forming a first p-type region at the first end of the at least one vertical pillar, forming a storage unit connecting the first p-type region, removing a portion of the substrate at a second side opposite to the first side of the substrate to expose the second end of the at least one vertical pillar, forming a second p-type region made of at least p-type SiGe at the second end of the at least one vertical pillar, and forming a bit line in connection with the second p-type region.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a gate laterally positioned between the trench and the source, and a field plate inside the trench. The field plate is laterally positioned between the gate and the drain. The structure further comprises a gate dielectric between the gate and the semiconductor substrate. The gate dielectric includes a first section adjacent to the field plate and a second section adjacent to the source. The first section is thicker than the second section.

A method for manufacturing a semiconductor structure includes: forming a gate electrode; forming a gate dielectric layer over the gate electrode; forming a channel over the gate dielectric layer opposite to the gate electrode, the channel including a semiconductor material; forming a first confinement layer on the channel opposite to the gate electrode, an energy band gap of the first confinement layer being greater than an energy band gap of the channel; and forming a drain electrode and a source electrode which are connected to the channel, the drain electrode and the source electrode being spaced apart from each other and each including an electrically conductive material.

A semiconductor device includes a plurality of active regions in a substrate; a gate trench formed in at least one of the plurality of the active regions, the gate trench including a first sidewall, a second sidewall opposite to the first sidewall, and a bottom sidewall; a growth promotion region formed on the first sidewall of the trench; a first gate dielectric layer formed on the first sidewall of the trench to contact the growth promotion region; a second gate dielectric layer formed on the second sidewall of the trench to be thinner than the first gate dielectric layer; and a gate electrode partially filling the trench over the first and second gate dielectric layers.