305 results about "Electromigration" patented technology

Various implementations of electrophoretic systems and instruments are provided to improve electrophoresis and ease of use. Various electrophoretic systems and instruments utilize different electrode designs that can result in uniform electromigration of analytes. The electrophoretic systems and instrumentations optimize the size and / or location of electrodes relative to a sample, thereby increasing uniformity of electric field and reducing or minimizing drift of analyte migration. In addition, the electrophoresis systems and instruments provide a solution to conveniently check for electrical connections in the systems and instruments, and alert users of potential improper electrical connections, prior to performing electrophoresis.

Circuits and methods for increasing the long-term reliability and performance of phase change material (PCM) switches. To overcome the effects of electromigration damage of the resistive heater(s) of a PCM switch and of the PCM itself, and thus improve long-term performance and reliability, embodiments apply an AC control pulse of equal power to a conventional DC control pulse. An embodiment encompasses a PCM switch, including a PCM region including first and second signal ports configured to be coupled to a signal source; a resistive heater adjacent the PCM region and including first and second heater control signal ports; and a source of AC control pulses coupled to the first and second heater control signal ports, the AC control pulses having a first power profile to transform the PCM region into a low resistance state and a second power profile to transform the PCM region into a high resistance state.

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

The invention discloses a method for realizing low-temperature diffusion bonding of zirconium and alloy thereof based on a constant-current electric field, and relates to the technical field of material bonding. The method aims at solving the problems that in current direct diffusion bonding of zirconium and zirconium alloy, the joint strength is low at the low bonding temperature, and base metal performance is reduced and post-welding deformation is large at the high bonding temperature. According to the method, hole closing and atomic diffusion at a diffusion connection interface are jointly promoted mainly through the electromigration effect under the action of the constant-current electric field, the vacancy concentration of zirconium and the alloy thereof improved by the constant-current electric field, and high-temperature plasticity, so that the high-strength zirconium and the alloy connector thereof are obtained at low temperature. The method for realizing low-temperature diffusion bonding of the zirconium and the zirconium alloy under the action of the constant-current electric field can be obtained.

The invention discloses a design optimization method and system for an integrated circuit layout, and relates to the technical field of integrated circuits, the system can accurately identify current density abnormal regions through a concentrated region analysis module, and calculates electromigration tolerance coefficients Drxs according to signal interconnection situation data in the regions, a signal interference coefficient Xgxs is constructed through a layout design analysis module in combination with a material state and attribute data, a trade-off evaluation index Qgzs is obtained through a trained risk prediction model, and the series of steps ensure that the balance state between electromigration tolerance and signal integrity is accurately evaluated. Finally, the optimization management module compares the Qgzs with a preset evaluation threshold value Q, and whether the current design reaches a balance state or not can be accurately judged. And if not, the system automatically sends out an optimization command, and optimization adjustment is carried out aiming at the electromigration tolerance and the signal integrity.

Provided are a package structure and a method of forming the same. The package structure includes an interposer at least including a first die sandwiched between a first redistribution layer (RDL) structure and a second RDL structure. The first die includes: a device layer disposed on a substrate; an inductor device disposed on the device layer; an internal RDL structure disposed on the inductor device; a plurality of conductive connectors disposed on the internal RDL structure; and an inductor contact disposed aside the inductor device and electrically connecting the internal RDL structure and inductor device. The internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors, thereby preventing the electromigration (EM) failure.

The invention discloses a micro-copper pillar bump interconnection resistor electromigration degradation prediction method. The method comprises the following steps: obtaining the net flux of Cu atoms in a Cu6Sn5 layer and a Cu3Sn layer and the net flux of Ni atoms in a Ni-Cu-Sn compound layer under forward current and reverse current; establishing a relationship between the net flux of Ni atoms and the thickness change of the Ni-Cu-Sn compound layer and a relationship between the net flux of Cu atoms and the thickness change of the Cu6Sn5 layer and the Cu3Sn layer; establishing a thickness polarity growth model of the Ni-Cu-Sn compound, the Cu6Sn5 layer and the Cu3Sn layer; establishing a thickness polarity consumption model of the Cu bonding pad, the Sn solder and the Ni layer; and establishing a resistance electromigration degradation model of micro-copper pillar bump interconnection. According to the method, the electromigration degradation prediction of the interconnection resistor of the copper pillar bump plated with the Ni layer can be realized, and a large amount of service life and time and economic cost generated by a failure analysis test are greatly reduced or avoided.

The invention discloses silver-coated copper particles, a preparation method thereof and application of the silver-coated copper particles in sintering slurry. The invention belongs to the field of sintered materials. The problem that in the prior art, the sintering temperature of high-temperature welding flux is high is solved. According to the silver-coated copper particles, a multi-step chemical synthesis method is adopted, firstly, silver-coated copper particle suspension is prepared, and then a silver complexing solution, a second chelating agent solution and a complexing agent solution are used for regulating and controlling the release and reduction rate difference of silver ions, so that gradient structure evolution of a silver layer from a compact structure to a porous structure is achieved; the surfaces of the silver-coated copper particles have multistage pore structures, so that the contact resistance among the particles can be effectively reduced, the sintering initial temperature is effectively reduced, the problem of poor oxidation performance of the copper particles is solved, the use amount of silver is reduced, the manufacturing cost is reduced, the ion migration path length is increased, and the electromigration life is prolonged; the prepared silver-coated copper particles greatly meet the requirements of the current electronic packaging field for novel welding materials, and have remarkable social benefits and economic benefits.

The invention provides a wafer-level cluster coplanar waveguide electrode array, a preparation method and a test system. The coplanar waveguide electrode array comprises an insulating substrate and a plurality of coplanar waveguide electrodes which are arranged in a periodic array; each coplanar waveguide electrode comprises a central transmission section, a probe pad and a gradual transition section; through the design of the central transmission section and the gradual transition section of the coplanar waveguide configuration, the whole-course impedance matching from an external probe to a nano gap is ensured, so that nanosecond and even picosecond-level ultrafast electric pulses can be transmitted to the cluster function unit with extremely low loss and distortion; through overlay and multi-step photoetching and in combination with a negative feedback electromigration technology, a nano gap is manufactured with high success rate, and a cluster function unit is integrated; besides, a test system integrating a coplanar waveguide electrode array and a high-end test instrument is used for exciting and capturing the ultrafast response of a cluster functional unit, and the single write-in time of a cluster device is directly pushed to a subnanosecond level (lt;

The invention relates to the technical field of failure evaluation, and discloses a TSV-RDL wafer level package electro-failure reliability evaluation system, which comprises an upper computer, a precision power supply, an editable controller, a direct current voltmeter and a relay array, the upper computer is connected with the precise power supply, the programmable controller and the direct-current voltmeter through a communication bus; the programmable controller is connected with the direct-current voltmeter and the relay array, the programmable controller responds to a control instruction and controls the on-off state of a current path at the connecting end of the TSV sample through the relay array, and the TSV sample receives current and voltage and responds to the current and the voltage in real time; the direct current voltmeter is used for measuring the voltage change of the TSV sample; the programmable controller judges whether a set condition is met or not based on data fed back by the direct-current voltmeter in real time, and then the on-off state of the relay is controlled. According to the invention, the current-voltage-resistance characteristics of the TSV sample can be comprehensively recorded, and the automation level of the test is improved, so that the requirements of the TSV electromigration failure test are met.

The invention relates to the technical field of integrated circuits, in particular to an electron migration violation combined repair method and system, which comprises the following steps: after double-through-hole processing is completed, judging whether a power line inspection result meets a power line current standard or not, if not, adding a power grid to a damaged power line area, and if yes, adding a power grid to the damaged power line area; if yes, after high-layer metal wiring and buffer insertion are completed, large driving unit forbidding is carried out on a signal line to be repaired, a signal line inspection result, a unit path conversion value set and a unit clock conversion value set are recognized, whether the signal line inspection result meets a signal line current standard or not is judged, and if not, after buffer segmentation and damaged line widening are completed, the signal line to be repaired is repaired. And judging whether the unit path conversion value set and the unit clock conversion value set accord with a conversion value standard or not, and if not, disabling the non-standard driving unit until the signal line inspection result accords with a signal line current standard. According to the invention, the repair efficiency of electron migration violation can be improved.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a radio frequency resistor calibration structure based on an RDL process and a manufacturing method, and the radio frequency resistor calibration structure comprises a main resistor module, a redundant resistor module, a laser fine tuning module, a shielding layer module and a temperature compensation module. The main resistor module is sputtered into a film through a low-temperature coefficient metal alloy, and the high-frequency skin effect is reduced by adopting a snakelike or interdigital geometric layout; and the redundant resistor module drives metal ions to migrate through a narrow-neck structure and an electromigration effect, and compensates photoetching line width deviation and uneven sputtering thickness. The laser fine tuning module adjusts a conductive path through selective ablation or annealing of pulse laser, and forms closed-loop calibration in combination with real-time feedback of the metal induction electrode. And the consistency regulation and control of radio frequency circuit parameters of a packaging level are realized.

The invention discloses a method for efficiently improving electromigration reliability of lead-free interconnection welding spots based on ultrafast laser processing, and relates to the technical field of material processing and welding. A microstructure with a special latticed groove is prepared on the end face of a welding body to be interconnected by adopting an ultrafast laser processing technology, and micro-nano particles are densely distributed in the latticed groove and around the latticed groove; and then lead-free interconnection welding is adopted, so that the electromigration reliability is improved. The distance between the grooves is 20-200 microns, the width is 30-50 microns, and the depth is about 10-50 microns, a special surface structure is obtained through ultrafast laser processing, the surface area of a connecting surface is effectively increased through the multi-scale latticed micro-nano structure, uniform distribution of a series of brazing filler metal and mechanical combination of the series of brazing filler metal after solidification are facilitated, and the problem that existing linear welding spots are poor in electromigration failure performance is solved.

Provided in the present invention are a nanotwinned silver material and a preparation method therefor. The preparation method comprises the following steps: step S1, cleaning a substrate, and drying same; and S2, selecting a silver target as a target material, placing the substrate and the target material into a magnetron sputtering device, vacuumizing same, and then applying a negative bias voltage to the substrate to perform direct-current magnetron sputtering deposition, wherein the bias voltage of the substrate ranges from -50 V to -200 V, the temperature of the substrate is 25-50ºC, the argon flow is 30-50 sccm, the vacuum degree of a sputtering chamber is 0.3-1.0 Pa, and the deposition time is 15-90 min. By means of the technical solution of the present invention, the prepared nanotwinned silver material contains high-density nano-twins, the proportion of twin boundaries is greater than 90%, and the hardness, electromigration resistance and thermal stability of the material are improved while the material has both high conductivity and high heat conductivity; and the obtained nanotwinned silver material has good comprehensive performance.

The invention discloses a reliability evaluation method for a conductive thermal interface material. The method comprises the following steps: manufacturing a substitute sample according to a conductive thermal interface material bonding layer structure of an actual device and a sintering process; gradually increasing the environment temperature to test an actual device, and taking the amplification of the interface thermal resistance as a failure threshold value when the performance of the device cannot meet the requirement; according to the set temperature stress and current stress conditions, thermoelectric stress tests are carried out on all the alternative samples, the tests are stopped after a period of time, and interface thermal resistance tests are carried out; when the amplification of the interface thermal resistance of the alternative sample exceeds a failure threshold value, stopping the thermoelectric stress test of the alternative sample and recording the failure life until the amplification of the interface thermal resistance of all the alternative samples exceeds the failure threshold value; and obtaining the failure life of the conductive thermal interface material according to the failure life data of all the alternative samples, thereby realizing reliability evaluation of the conductive thermal interface material. According to the method, the reliability of interface thermal resistance degradation caused by the electromigration effect can be effectively evaluated.

The embodiment of the invention provides a simulation method and device of a chip system and related equipment, and the method comprises the steps: obtaining the connection data of the chip system; the connection data comprises physical connection data, and the physical connection data is formed based on physical connection relations among chips in the chip system; extracting a power supply network simulation node of the chip system from the physical connection data, and constructing a power supply network structure of the chip system based on the extracted power supply network simulation node; and simulating the chip system based on the power network structure. According to the technical scheme provided by the embodiment of the invention, the reliability of a voltage drop electromigration simulation result can be improved.

The invention provides a method for predicting and evaluating the electromigration life of a low-temperature interconnected Sn-Bi-based alloy micro-welding spot and application, and relates to the field of reliability evaluation of advanced electronic packaging micro-scale welding spots. Based on an electromigration failure physical mechanism, starting from a theory that Bi atoms are directionally migrated by electron wind power, the association between atomic diffusion flux and beta-Sn / Bi two-phase separation, anode Bi-rich layer growth and resistance evolution is disclosed; according to the method, cross-scale systematic correlation of micro atom migration (Bi atom migration)-mesoscopic structure evolution (beta-Sn / Bi two-phase separation and anode Bi phase precipitation)-macroscopic welding spot failure (resistance increase) is achieved, micro structure evolution of Sn-Bi-based alloy micro welding spots in the electromigration process is quantified, reliable physical mechanism support is achieved, and the method is suitable for large-scale application. The parameter calibration workload is remarkably reduced (compared with an empirical formula Black equation commonly used in current electromigration life prediction, the parameter calibration workload is reduced by 80%), and the prediction precision can reach 90% or above.

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and / or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

To realize a high-performance semiconductor device which has excellent reliability.SOLUTION: A semiconductor device 1 includes a semiconductor layer 70b which is provided in a semiconductor laminate structure 20 that includes an electron transit layer 22 and an electron supply layer 24 on a drain electrode 40 side and is connected to the drain electrode 40. The semiconductor layer 70b extends from a surface 20a on the electron supply layer 24 side of the semiconductor laminate structure 20 to the electron transit layer 22 and contains n-type impurities. The drain electrode 40 covers the semiconductor layer 70b and a portion 20ab of the surface 20a adjacent to the semiconductor layer 70b. With this, the formation of an interface where the semiconductor layer 70b contacts an insulating film 60 provided on the surface 20a is avoided, and electron traps of the interface and the performance reduction caused by the electron traps can be suppressed. In addition, the increase in the current density between the drain electrode 40 and the electron transit layer 22 and the reliability reduction due to electromigration caused by the increase can be suppressed.SELECTED DRAWING: Figure 4

The invention discloses a full-chip power supply network design method, which comprises the following steps of: 1, analyzing power consumption, and respectively calculating maximum transient power consumption and average power consumption of a chip under different application conditions; 2, estimating parameters of the power supply network, and estimating the parameters of the power supply network so as to provide reference design for the power supply network; 3, designing a power supply network, namely determining the density of the power supply network, the number of power supply IOs and selecting the style of a power supply rail; and step 4, analyzing network grid points. The full-chip power supply network is optimally designed, so that the chip area occupied by the power supply network is minimum on the premise of ensuring that voltage drop and electromigration are within ideal ranges, unlimited congestion is not caused, the adaptability of the power supply network and a chip is improved, the area of the full-chip power supply network is smaller than that of a uniform distribution method, and the power supply network can be applied to the power supply network. And the working life of the chip is greatly prolonged.

The application discloses a semiconductor device and a curve processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by a plurality of boundary lines with different directions and connected by transition lines; the transition line between two adjacent boundary lines is a curve determined according to the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. The end points of the related lines forming the metal interconnection layer are taken as processing objects, and the transition lines are used for transition at the positions where the related lines change direction, so that the overall coverage adjustment of each angle is realized, the inradius of all concave corner positions is increased as much as possible, the stress distribution concentration effect at each concave corner is weakened, the crack formation is avoided, the metal electromigration, the connected lines or the broken lines and other phenomena are eliminated, the product quality is obviously improved, and the chip life is prolonged.

The present invention provides a method for forming a metal interconnection structure and a metal interconnection structure, and specifically relates to the field of semiconductor technology. The formation method comprises: providing a substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer; forming a through hole on the first interlayer dielectric layer, wherein a portion of the conductive layer is exposed at the bottom of the through hole; sequentially forming a diffusion barrier layer and a seed layer on the inner wall of the through hole and the first interlayer dielectric layer on both sides of the through hole; forming an interconnection metal line on the seed layer, the interconnection metal line comprising a first interconnection metal line and a second interconnection metal line, the first interconnection metal line is filled in the through hole, the second interconnection metal line is located on the first interlayer dielectric layer and connected to the first interconnection metal line; forming a self-aligned alloy region on the top wall and side wall of the second interconnection metal line; and forming a second interlayer dielectric layer on the self-aligned alloy region. The method can improve the resistance of the interconnection metal to electromigration and improve the diffusion problem of the interconnection metal.

The application discloses an electronic skin-oriented conductive silver paste and a preparation method and application thereof, and relates to the technical field of flexible printed electronic materials.The raw materials of the electronic skin-oriented conductive silver paste include flaky silver powder, silver nanoparticles, thermoplastic polyurethane elastomer, acrylic elastomer, PEDOT:PSS microgel dispersion, (3-glycidylpropoxy)trimethoxysilane, polydiallyldimethylammonium chloride, hexanedial modified dopamine copolymer, (3-aminopropyl)triethoxysilane, methacryloyloxypropyltrimethoxysilane, cellulose acetate, modified polyurea thixotropic agent, hydrogenated castor oil, ethylene glycol ether acetate, dibasic acid ester, leveling agent and water.The electronic skin-oriented conductive silver paste has the advantages of good electrical performance, good mechanical-electrical stability, good anti-electromigration and sweat corrosion resistance, and can still maintain dendrite-free and low drift under long-term coupling of sweat and bias, and is suitable for electronic skin.

The application provides an electromigration reliability non-uniform discrete equivalent circuit modeling method and system, adopts an equivalent circuit-based method to analyze electromigration stress evolution of a general complex interconnection structure, fully considers a thermal field effect in a model, realizes stress analysis equivalent circuit modeling under multi-physical field coupling, and solves the problem of waste of computing resources in processing large-span interconnection structures by using a traditional uniform discrete method, avoids unnecessary transient simulation on an immortal interconnection tree, reduces the computing load of full-chip-level analysis, and realizes efficient and high-precision transient analysis of electromigration reliability of a large-scale interconnection network under multi-physical field coupling effects.

The invention discloses a metal ceramic substrate and a manufacturing method thereof. The metal ceramic substrate comprises a ceramic substrate layer, a metal solder layer and a conductive metal layer. The metal solder layer includes a first sub-solder layer and a second sub-solder layer. The first sub-solder layer is disposed on the ceramic substrate layer. The composition of the first sub-solder layer includes a first metal solder including metal copper (Cu) and an active metal, and not including metal silver (Ag); wherein the thickness of the first sub-solder layer is greater than 6 microns. The second sub-solder layer is disposed on the first sub-solder layer. The composition of the second sub-solder layer comprises a second metal solder which comprises metal tin (Sn) and metal copper (Cu) and does not comprise metal silver (Ag); wherein the second sub solder layer is larger than 6 microns. The conductive metal layer is disposed on the second sub-solder layer. Therefore, the problem of electromigration can be effectively avoided, and the manufacturing cost can be reduced.

To prevent deterioration and mechanical destruction of a membrane in a light source by suppressing electromigration in the light source.SOLUTION: A light-source driving device 80A includes a light source 2, a power source 800, and an NMOSFET 801, 802, 803, and 804 as a switching element. The light source 2 has a heater layer containing metal, and emits infrared rays based on a power supply voltage applied to the heater layer. The power supply 800 outputs a voltage V as the power supply voltage to the light source 2. The NMOSFET 801 to 804 switches a path of current flowing from the power source 800 to the light sources 2 and alternately drives a direction of the current flowing to the light sources 2.SELECTED DRAWING: Figure 7

The embodiment of the invention discloses a semiconductor device and a curve type processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by connecting a plurality of boundary lines in different directions through transition lines; a transition line between every two adjacent boundary lines is a curve determined according to the intersection relation of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. End points of related lines forming the metal interconnection layer are used as processing objects, curves are used for transition at reversing positions of the related lines, all angles are comprehensively covered and adjusted, the inscribed circle radiuses of all concave angle positions are increased as much as possible, the stress distribution concentration effect at each concave angle is weakened, cracks are avoided, and the stability of the metal interconnection layer is improved. The phenomena of metal electromigration, strip connection or strip breakage and the like are eliminated, the product quality is obviously improved, and the service life of a chip is prolonged.

The invention relates to the technical field of high-efficiency refining of molten metal silicon, and discloses a high-efficiency refining process of molten metal silicon under the synergistic effect of multiple fields, which comprises the following steps: S1, placing molten metal silicon in a refining device which can apply a controllable temperature gradient field and an external electric field; s2, by regulating and controlling the size and the direction of the temperature gradient field, metal impurities are directionally migrated to a low-temperature area in the melt under the action of thermal diffusion and are enriched; s3, an external electric field is applied at the same time, and non-metal impurities are directionally migrated to an electrode area and enriched under the electromigration effect by regulating and controlling the type, intensity and frequency of the electric field; s4, performing cooperative control on the temperature gradient field and an external electric field; and S5, carrying out physical isolation or online removal on the enriched impurity region. Compared with the prior art, the device and the method have the advantages that metal and nonmetal impurities are respectively driven to directionally migrate and enrich, so that efficient separation of the impurities and deep purification of the silicon melt are realized.

The invention provides a reliability test structure and a reliability test method. The reliability test structure comprises a semiconductor substrate; the dielectric layer covers the semiconductor substrate; the at least one first test structure and the at least one second test structure are located in the dielectric layer; the first test structure comprises a first metal layer, a second metal layer and a first through hole layer; and the second test structure comprises a third metal layer, a fourth metal layer and a second through hole layer. According to the reliability test structure, electromigration, dielectric breakdown and voltage slope test structures are integrated through 3D design, electromigration and dielectric breakdown / voltage slope test structures can be tested in the same area in sequence, the position of a wafer does not need to be moved, the test process is simplified, and meanwhile the test efficiency is improved. The electromigration test / dielectric breakdown test, the electromigration test / voltage ramp test and the dielectric breakdown test / voltage ramp test are carried out in parallel, so that the overall reliability test time is greatly shortened. In addition, by means of the design, the wafer area occupied by the testing structure is saved, and the wafer utilization rate is increased.

Provide various implementations of electrophoresis systems and instruments to improve electrophoresis and ease of use. The various electrophoresis systems and instruments utilize different electrode designs, which can result in uniform electro-migration of analytes. The electrophoresis systems and instruments optimize the size and / or position of the electrodes relative to the sample, thereby increasing the uniformity of the electric field and reducing or minimizing the drift of analyte migration. In addition, the electrophoresis systems and instruments provide a solution to conveniently check the electrical connections in the systems and instruments before performing electrophoresis and alert the user to potential inappropriate electrical connections.