185 results about "Electromigration" patented technology

Various implementations of electrophoretic systems and instruments are provided to improve electrophoresis and ease of use. Various electrophoretic systems and instruments utilize different electrode designs that can result in uniform electromigration of analytes. The electrophoretic systems and instrumentations optimize the size and / or location of electrodes relative to a sample, thereby increasing uniformity of electric field and reducing or minimizing drift of analyte migration. In addition, the electrophoresis systems and instruments provide a solution to conveniently check for electrical connections in the systems and instruments, and alert users of potential improper electrical connections, prior to performing electrophoresis.

A dynamic grid allocation system for power distribution in the development of integrated circuits in the sub-five-nanometer range, wherein the system comprises the following: a placement processor unit configured to receive a synthesized netlist comprising a variety of standard cells and macros, each associated with switching activity data derived from simulation or synthesis activity profiles, and to generate a spatial cell placement arrangement by grouping cells into microzones based on activity correlation, time sensitivity, and connection proximity; a power density calculation unit coupled to the placement processor unit and configured to calculate the local power density and instantaneous current demand for each microzone based on the spatial distribution of switching operations, capacity load, and effective switching frequencies; a dynamic network generation unit coupled to the power density calculation unit and configured to generate a multilayer power distribution network with variable network topology, where the width, spacing, via density and metal layer assignment of the power network are adaptively determined as continuous functions of the localized power density and power demand calculated for each microzone; a topology control processor configured to monitor voltage drop and electromigration data obtained from signoff analyses or predictive models in real time and dynamically adjust the power grid topology parameters to ensure compliance with predefined reliability thresholds for voltage drop and electromigration; a predictive current modeling unit configured to receive historical switching and voltage data, train a predictive model for transient current peaks, and provide predictive power boost instructions to the dynamic grid generation unit before power integrity violations occur; and A feedback synchronization controller is communicatively connected to the placement processor unit and the topology control processor, whereby the feedback synchronization controller continuously exchanges updated power density information and placement constraints, so that cell placement and network topology adapt together in real time, thereby minimizing routing congestion, ensuring a uniform voltage distribution, and guaranteeing compliance with electromigration and IR drop regulations under various activity conditions.

Provided are a package structure and a method of forming the same. The package structure includes an interposer at least including a first die sandwiched between a first redistribution layer (RDL) structure and a second RDL structure. The first die includes: a device layer disposed on a substrate; an inductor device disposed on the device layer; an internal RDL structure disposed on the inductor device; a plurality of conductive connectors disposed on the internal RDL structure; and an inductor contact disposed aside the inductor device and electrically connecting the internal RDL structure and inductor device. The internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors, thereby preventing the electromigration (EM) failure.

The invention discloses a micro-copper pillar bump interconnection resistor electromigration degradation prediction method. The method comprises the following steps: obtaining the net flux of Cu atoms in a Cu6Sn5 layer and a Cu3Sn layer and the net flux of Ni atoms in a Ni-Cu-Sn compound layer under forward current and reverse current; establishing a relationship between the net flux of Ni atoms and the thickness change of the Ni-Cu-Sn compound layer and a relationship between the net flux of Cu atoms and the thickness change of the Cu6Sn5 layer and the Cu3Sn layer; establishing a thickness polarity growth model of the Ni-Cu-Sn compound, the Cu6Sn5 layer and the Cu3Sn layer; establishing a thickness polarity consumption model of the Cu bonding pad, the Sn solder and the Ni layer; and establishing a resistance electromigration degradation model of micro-copper pillar bump interconnection. According to the method, the electromigration degradation prediction of the interconnection resistor of the copper pillar bump plated with the Ni layer can be realized, and a large amount of service life and time and economic cost generated by a failure analysis test are greatly reduced or avoided.

The invention discloses silver-coated copper particles, a preparation method thereof and application of the silver-coated copper particles in sintering slurry. The invention belongs to the field of sintered materials. The problem that in the prior art, the sintering temperature of high-temperature welding flux is high is solved. According to the silver-coated copper particles, a multi-step chemical synthesis method is adopted, firstly, silver-coated copper particle suspension is prepared, and then a silver complexing solution, a second chelating agent solution and a complexing agent solution are used for regulating and controlling the release and reduction rate difference of silver ions, so that gradient structure evolution of a silver layer from a compact structure to a porous structure is achieved; the surfaces of the silver-coated copper particles have multistage pore structures, so that the contact resistance among the particles can be effectively reduced, the sintering initial temperature is effectively reduced, the problem of poor oxidation performance of the copper particles is solved, the use amount of silver is reduced, the manufacturing cost is reduced, the ion migration path length is increased, and the electromigration life is prolonged; the prepared silver-coated copper particles greatly meet the requirements of the current electronic packaging field for novel welding materials, and have remarkable social benefits and economic benefits.

The invention provides a wafer-level cluster coplanar waveguide electrode array, a preparation method and a test system. The coplanar waveguide electrode array comprises an insulating substrate and a plurality of coplanar waveguide electrodes which are arranged in a periodic array; each coplanar waveguide electrode comprises a central transmission section, a probe pad and a gradual transition section; through the design of the central transmission section and the gradual transition section of the coplanar waveguide configuration, the whole-course impedance matching from an external probe to a nano gap is ensured, so that nanosecond and even picosecond-level ultrafast electric pulses can be transmitted to the cluster function unit with extremely low loss and distortion; through overlay and multi-step photoetching and in combination with a negative feedback electromigration technology, a nano gap is manufactured with high success rate, and a cluster function unit is integrated; besides, a test system integrating a coplanar waveguide electrode array and a high-end test instrument is used for exciting and capturing the ultrafast response of a cluster functional unit, and the single write-in time of a cluster device is directly pushed to a subnanosecond level (lt;

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a radio frequency resistor calibration structure based on an RDL process and a manufacturing method, and the radio frequency resistor calibration structure comprises a main resistor module, a redundant resistor module, a laser fine tuning module, a shielding layer module and a temperature compensation module. The main resistor module is sputtered into a film through a low-temperature coefficient metal alloy, and the high-frequency skin effect is reduced by adopting a snakelike or interdigital geometric layout; and the redundant resistor module drives metal ions to migrate through a narrow-neck structure and an electromigration effect, and compensates photoetching line width deviation and uneven sputtering thickness. The laser fine tuning module adjusts a conductive path through selective ablation or annealing of pulse laser, and forms closed-loop calibration in combination with real-time feedback of the metal induction electrode. And the consistency regulation and control of radio frequency circuit parameters of a packaging level are realized.

The invention discloses a reliability evaluation method for a conductive thermal interface material. The method comprises the following steps: manufacturing a substitute sample according to a conductive thermal interface material bonding layer structure of an actual device and a sintering process; gradually increasing the environment temperature to test an actual device, and taking the amplification of the interface thermal resistance as a failure threshold value when the performance of the device cannot meet the requirement; according to the set temperature stress and current stress conditions, thermoelectric stress tests are carried out on all the alternative samples, the tests are stopped after a period of time, and interface thermal resistance tests are carried out; when the amplification of the interface thermal resistance of the alternative sample exceeds a failure threshold value, stopping the thermoelectric stress test of the alternative sample and recording the failure life until the amplification of the interface thermal resistance of all the alternative samples exceeds the failure threshold value; and obtaining the failure life of the conductive thermal interface material according to the failure life data of all the alternative samples, thereby realizing reliability evaluation of the conductive thermal interface material. According to the method, the reliability of interface thermal resistance degradation caused by the electromigration effect can be effectively evaluated.

The invention provides a method for predicting and evaluating the electromigration life of a low-temperature interconnected Sn-Bi-based alloy micro-welding spot and application, and relates to the field of reliability evaluation of advanced electronic packaging micro-scale welding spots. Based on an electromigration failure physical mechanism, starting from a theory that Bi atoms are directionally migrated by electron wind power, the association between atomic diffusion flux and beta-Sn / Bi two-phase separation, anode Bi-rich layer growth and resistance evolution is disclosed; according to the method, cross-scale systematic correlation of micro atom migration (Bi atom migration)-mesoscopic structure evolution (beta-Sn / Bi two-phase separation and anode Bi phase precipitation)-macroscopic welding spot failure (resistance increase) is achieved, micro structure evolution of Sn-Bi-based alloy micro welding spots in the electromigration process is quantified, reliable physical mechanism support is achieved, and the method is suitable for large-scale application. The parameter calibration workload is remarkably reduced (compared with an empirical formula Black equation commonly used in current electromigration life prediction, the parameter calibration workload is reduced by 80%), and the prediction precision can reach 90% or above.

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and / or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

The application discloses a semiconductor device and a curve processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by a plurality of boundary lines with different directions and connected by transition lines; the transition line between two adjacent boundary lines is a curve determined according to the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. The end points of the related lines forming the metal interconnection layer are taken as processing objects, and the transition lines are used for transition at the positions where the related lines change direction, so that the overall coverage adjustment of each angle is realized, the inradius of all concave corner positions is increased as much as possible, the stress distribution concentration effect at each concave corner is weakened, the crack formation is avoided, the metal electromigration, the connected lines or the broken lines and other phenomena are eliminated, the product quality is obviously improved, and the chip life is prolonged.

The application discloses an electronic skin-oriented conductive silver paste and a preparation method and application thereof, and relates to the technical field of flexible printed electronic materials.The raw materials of the electronic skin-oriented conductive silver paste include flaky silver powder, silver nanoparticles, thermoplastic polyurethane elastomer, acrylic elastomer, PEDOT:PSS microgel dispersion, (3-glycidylpropoxy)trimethoxysilane, polydiallyldimethylammonium chloride, hexanedial modified dopamine copolymer, (3-aminopropyl)triethoxysilane, methacryloyloxypropyltrimethoxysilane, cellulose acetate, modified polyurea thixotropic agent, hydrogenated castor oil, ethylene glycol ether acetate, dibasic acid ester, leveling agent and water.The electronic skin-oriented conductive silver paste has the advantages of good electrical performance, good mechanical-electrical stability, good anti-electromigration and sweat corrosion resistance, and can still maintain dendrite-free and low drift under long-term coupling of sweat and bias, and is suitable for electronic skin.

The application provides an electromigration reliability non-uniform discrete equivalent circuit modeling method and system, adopts an equivalent circuit-based method to analyze electromigration stress evolution of a general complex interconnection structure, fully considers a thermal field effect in a model, realizes stress analysis equivalent circuit modeling under multi-physical field coupling, and solves the problem of waste of computing resources in processing large-span interconnection structures by using a traditional uniform discrete method, avoids unnecessary transient simulation on an immortal interconnection tree, reduces the computing load of full-chip-level analysis, and realizes efficient and high-precision transient analysis of electromigration reliability of a large-scale interconnection network under multi-physical field coupling effects.

To prevent deterioration and mechanical destruction of a membrane in a light source by suppressing electromigration in the light source.SOLUTION: A light-source driving device 80A includes a light source 2, a power source 800, and an NMOSFET 801, 802, 803, and 804 as a switching element. The light source 2 has a heater layer containing metal, and emits infrared rays based on a power supply voltage applied to the heater layer. The power supply 800 outputs a voltage V as the power supply voltage to the light source 2. The NMOSFET 801 to 804 switches a path of current flowing from the power source 800 to the light sources 2 and alternately drives a direction of the current flowing to the light sources 2.SELECTED DRAWING: Figure 7

The embodiment of the invention discloses a semiconductor device and a curve type processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by connecting a plurality of boundary lines in different directions through transition lines; a transition line between every two adjacent boundary lines is a curve determined according to the intersection relation of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. End points of related lines forming the metal interconnection layer are used as processing objects, curves are used for transition at reversing positions of the related lines, all angles are comprehensively covered and adjusted, the inscribed circle radiuses of all concave angle positions are increased as much as possible, the stress distribution concentration effect at each concave angle is weakened, cracks are avoided, and the stability of the metal interconnection layer is improved. The phenomena of metal electromigration, strip connection or strip breakage and the like are eliminated, the product quality is obviously improved, and the service life of a chip is prolonged.

The invention relates to the technical field of high-efficiency refining of molten metal silicon, and discloses a high-efficiency refining process of molten metal silicon under the synergistic effect of multiple fields, which comprises the following steps: S1, placing molten metal silicon in a refining device which can apply a controllable temperature gradient field and an external electric field; s2, by regulating and controlling the size and the direction of the temperature gradient field, metal impurities are directionally migrated to a low-temperature area in the melt under the action of thermal diffusion and are enriched; s3, an external electric field is applied at the same time, and non-metal impurities are directionally migrated to an electrode area and enriched under the electromigration effect by regulating and controlling the type, intensity and frequency of the electric field; s4, performing cooperative control on the temperature gradient field and an external electric field; and S5, carrying out physical isolation or online removal on the enriched impurity region. Compared with the prior art, the device and the method have the advantages that metal and nonmetal impurities are respectively driven to directionally migrate and enrich, so that efficient separation of the impurities and deep purification of the silicon melt are realized.

The invention provides a reliability test structure and a reliability test method. The reliability test structure comprises a semiconductor substrate; the dielectric layer covers the semiconductor substrate; the at least one first test structure and the at least one second test structure are located in the dielectric layer; the first test structure comprises a first metal layer, a second metal layer and a first through hole layer; and the second test structure comprises a third metal layer, a fourth metal layer and a second through hole layer. According to the reliability test structure, electromigration, dielectric breakdown and voltage slope test structures are integrated through 3D design, electromigration and dielectric breakdown / voltage slope test structures can be tested in the same area in sequence, the position of a wafer does not need to be moved, the test process is simplified, and meanwhile the test efficiency is improved. The electromigration test / dielectric breakdown test, the electromigration test / voltage ramp test and the dielectric breakdown test / voltage ramp test are carried out in parallel, so that the overall reliability test time is greatly shortened. In addition, by means of the design, the wafer area occupied by the testing structure is saved, and the wafer utilization rate is increased.

Embodiments include herein are directed towards a method for electromigration analysis of a circuit design. Embodiments may include performing a first transient simulation of an electronic design using one or more electronic design tools. Embodiments may further include storing a level of current associated with one or more generic passive device tap points. Embodiments may also include identifying a resistor capacitor (RC) model for one or more generic passive devices using the one or more electronic design tools and performing a second transient simulation for the one or more generic passive devices. Embodiments may further include analyzing a current density obtained from the first and second transient simulation to obtain a single current density map.

A system and method of using a multi-zone substrate to perform electromigration testing of integrated circuits in the high-frequency RF domain. Here, the device under test (DUT) is affixed to a single, multi-zone substrate with a high-temperature zone, a transitional thermal isolation zone, to a low-temperature zone. The high-temperature zone has a DUT interface with a localized heater arrangement. The low-temperature zone provides the interface with RF lines or high speed digital lines to the RF test instrumentation. The DUT input and output pins are attached to the high-temperature zone, and the configuration allows both direct current (DC) and RF stressing of the DUT. The high-temperature zone can raise the DUT temperature to 300-450° C. The RF test port and associated test equipment remain at room temperature.

The invention provides a semiconductor metal interconnection structure, a semiconductor structure and a preparation method of the semiconductor metal interconnection structure, and cobalt metal, ruthenium metal and molybdenum metal are applied to the metal interconnection structure of a back-end process of the semiconductor structure. A main body conductive layer of a metal interconnection line with the line width not larger than (namely smaller than or equal to) 17nm in a metal interconnection layer is set as a cobalt metal interconnection layer or a ruthenium metal interconnection layer or a molybdenum metal interconnection layer, and a main body conductive layer of a metal interconnection line with the line width larger than 17nm is set as a copper metal interconnection layer, so that a composite metal interconnection layer design is realized; by combining the advantages of copper metal under large-size line width and the advantages of cobalt metal, ruthenium metal and molybdenum metal under small-size line width, the RC delay of the rear-section metal interconnection line is obviously improved, and the electromigration resistance of the rear-section metal interconnection line is improved, so that the reliability of the line is improved, and the service life of the line is prolonged.

The invention relates to a preparation method of a semiconductor structure and a copper electroplating solution. The semiconductor structure comprises a glass substrate, a barrier layer, a dielectric layer, a buffer layer and a redistribution layer which are sequentially stacked, the barrier layer comprises silicon dioxide, the dielectric layer comprises benzocyclobutene, and the buffer layer comprises at least one of tantalum and titanium tungsten. Benzocyclobutene is used as the dielectric layer, the dielectric constant is low, and the transmission loss of high-frequency signals is small; the silicon dioxide is used as the barrier layer and is arranged between the glass substrate and the dielectric layer, so that the dielectric layer can be prevented from being damaged by chemical substance etching of the glass substrate, and the adhesive force between the glass substrate and the dielectric layer can be enhanced; the buffer layer comprising at least one of tantalum and titanium tungsten is arranged between the dielectric layer and the redistribution layer, so that the adhesive force and the electromigration resistance between the dielectric layer and the redistribution layer can be improved, and the high-frequency signal transmission loss can be reduced; all the layers interact with each other, so that the electrical property and the reliability of the semiconductor structure are relatively good.

The present application discloses a three-dimensional integration process method without a bump interface, which constructs a bump-free three-dimensional integrated structure based on a silicon adapter plate, eliminates micro-bumps and their heterogeneous interfaces, avoids many problems existing in the bump bonding process, enables the three-dimensional stacking to obtain better electrical and mechanical performance, and at the same time realizes a more compact device layout, which is conducive to reducing the device size. It solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The use of copper pillar bumps has high manufacturing costs, requires precise process control, and faces reliability issues such as bond breakage, pressure reduction or electrical performance degradation.

The invention provides a method for improving the electromigration performance in a Cu interconnection structure, and the method comprises the steps: introducing SiH4 gas into the surface of a copper wire for pretreatment, and generating a CuSix transition layer; a SiN layer is deposited on the CuSix transition layer; and depositing an NDC dielectric layer on the SiN layer. According to the invention, the adhesiveness between Cu and the NDC dielectric layer can be greatly improved, so that the electromigration performance of the device is improved.

The application provides a low-temperature interconnection Sn-Bi-based alloy micro-welding spot electromigration life prediction and evaluation method and application, and relates to the reliability evaluation field of advanced electronic packaging micro-welding spots. Based on the physical mechanism of electromigration failure, starting from the electronic wind-driven Bi atom directional migration theory, the correlation between atomic diffusion flux and beta-Sn / Bi two-phase separation, anode Bi layer growth and resistance evolution is revealed, the cross-scale systematic correlation of "microscopic atomic migration (Bi atom migration)-mesoscopic organization evolution (beta-Sn / Bi two-phase separation, anode Bi phase precipitation)-macroscopic weld failure (resistance growth)" is realized, the microstructure evolution of the Sn-Bi-based alloy micro-welding spot in the electromigration process is quantified, has reliable physical mechanism support, significantly reduces the parameter calibration workload (compared with the current electromigration life prediction commonly used empirical formula Black equation, reduces by 80%), and the prediction accuracy can reach more than 90%.

The invention discloses an electromigration stress modeling method and device for an embedded power supply rail, relates to the technical field of embedded power supply rails, and aims to solve the problem of low fidelity during modeling simulation of the embedded power supply rail in the prior art. The modeling method comprises the following steps: constructing a two-dimensional grain boundary structure based on grain boundary line segment coordinate data of the embedded power supply rail; determining an included angle parameter between the grain boundary direction of each grain boundary in the two-dimensional grain boundary structure and the current direction; constructing a target electromigration stress model based on the included angle parameters; and solving the target electromigration stress model to obtain the electromigration stress distribution of the embedded power rail. The method is used for improving the fidelity of modeling simulation of the embedded power rail.

The application relates to the technical field of optoelectronic manufacturing, and particularly discloses a flip LED chip and a preparation method thereof. The flip LED chip comprises a substrate, an epitaxial layer, an insulating protective layer, a reflection layer, a first insulating layer, a P-type metal conductive layer, an N-type metal conductive layer, a second insulating layer, a P-type pad layer and an N-type pad layer which are stacked on the substrate; the reflection layer is arranged above the P-type semiconductor layer; the reflection layer comprises an electromigration-resistant part, a reflection part and a protective part; the electromigration-resistant part and the reflection part are arranged adjacently, the electromigration-resistant part is arranged close to the N-type conductive step, and the protective part covers the electromigration-resistant part and the reflection part; the electromigration-resistant part comprises an electromigration-resistant main part and a first oxidation-resistant part which are stacked in sequence; each group of metal pairs comprises an Ag metal layer and an AgNi alloy layer which are stacked in sequence; and the first oxidation-resistant part is made of one or more of Ni, Au, Ti and Cr. By implementing the application, the reliability can be improved.

The application relates to a 16Bit off-chip one-time programmable circuit, which belongs to the technical field of programming circuits and comprises basic storage units, a clock module, a pulse generator module, a counter module, a latch module, a code decoder module, a shutdown delay module and a switch module. Under the joint action of the related modules, the electromigration resistance change memory is easy to realize due to the resistor device, the mask plate manufacturing cost is reduced, the current for causing the electromigration of the resistor is smaller than the current for fusing the FUSE resistor, the metal splashing does not affect the safety of the surrounding circuit, the area required by the electromigration resistance change memory is small, the chip flow cost is reduced, the comparator can detect the slight change of the resistance value, the fault tolerance rate of data writing is increased to a certain extent, data can be written after the whole is packaged into a chip, and the calibration of the parameters of the chip in the actual use environment is facilitated.

This invention provides a method and apparatus for measuring solder joint electromigration. The method includes: determining the voltage of the daisy chain between one or more solder joints based on voltage measurement nodes led out from both ends of one or more solder joints; and determining the resistance of one or more solder joints based on the voltage. This method can solve the problem in related technologies where the resistance of a single solder joint cannot be measured by detecting the resistance of a single solder joint using the two-end method. It can measure the resistance of a single solder joint and enable effective reliability assessment of solder joint electromigration failure.

The application discloses an electromigration analysis system, wherein the system comprises a detection outer shell, the detection outer shell forms a closed electromigration analysis space; a high-voltage wire, the high-voltage wire passes through the detection outer shell and forms a high-voltage strong magnetic field environment in the electromigration analysis space; a sensor, the sensor is arranged in the electromigration analysis space; a detected device, the detected device is connected with the sensor; and a detection analysis host computer, the detection analysis host computer is connected with the sensor and is used for detecting a working state and signal transmission stability of the sensor. The application solves the technical problem that a system for comprehensively evaluating the electromigration performance of the sensor is lacked in the prior art.

A conformal nitride-rich carbide layer located on a dielectric-on-dielectric layer (a dielectric layer located on an interlayer dielectric) and metal line cap layers in an interconnect stack of an integrated circuit structure provides for improved electromigration. The carbide layer can enable integrated circuit structures to have a reduced topography prior to etch stop stack formation. In addition to enabling improved electromigration of the metal lines the carbide layers can reduce the current leakage between metal lines and nearby vias.