224 results about "Deposition process" patented technology

Method for creating an electrode on a substrate using a laser assisted deposition process. A metal paste is printed and dried on the substrate to form a conductive layer, and by 2D or 3D inspection, the dimensions of the conductive layer are measured. The substrate is subject to a pretreatment process so as to increase adhesion and / or conduction of the conductive layer to the substrate. An electrode that is produced according to the present method may be used in flexible devices.

This invention relates to the field of robot joint surface engineering technology, specifically to a nanopowder strengthening process for aluminum-based robot joint surfaces, comprising: Step S1, pretreatment: cleaning and roughness adjustment of the aluminum alloy joint surface; Step S2, ultra-hard nanopowder dispersion: hydrogen-terminated modification of the ultra-hard nanopowder to prepare a highly dispersed suspension; Step S3, joint surface embedding: uniformly embedding the ultra-hard nanopowder into the joint surface; Step S4, preparation of a three-layer composite coating: forming an interface by treating the joint surface using a nickel-diamond-nickel three-layer composite deposition process; Step S5, surface morphology control; and Step S6, post-treatment strengthening: low-temperature curing and stress release treatment. This invention provides a nanopowder strengthening process for aluminum-based robot joint surfaces, improving the hardness and wear resistance of the aluminum-based robot joint surfaces.

Methods and systems for depositing vanadium and / or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and / or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and / or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and / or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

This invention provides a NiCoB-P-F high-efficiency hydrogen evolution electrocatalyst, its preparation method, and its application. The catalyst uses a monomeric NiCoB substrate, on which phosphorus (P) and phosphorus (F) elements are co-doped. The mass ratio of P to F is (2-6):(1-3). The raw material for P doping is NaH₂PO₂; the raw material for F doping is NH₄F. The method employs a vapor deposition process to co-dope P and F elements onto the monomeric NiCoB substrate. The hydrogen evolution electrocatalyst of this invention enhances the electrocatalytic performance of the hydrogen evolution reaction under alkaline conditions, with an overpotential η... 10 As low as 25mV, η 300 With a voltage as low as 134mV, it can significantly reduce the hydrogen evolution overpotential under high current density, thereby improving the overall catalytic efficiency and stability.

A method for forming a metal, phosphorus, and nitrogen layer structure is disclosed. The method includes performing one or more deposition cycles of an atomic layer deposition process, the atomic layer deposition process including the introduction of a metal precursor and a phosphorus precursor. A method for forming a threshold voltage offset layer comprising the metal, phosphorus, and nitrogen layer structure is further disclosed.

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Implementations of the present disclosure generally relate to low k dielectric films disposed over a substrate. More particularly, implementations described herein provide, organic framework low k dielectric films and methods for forming the same. In at least one implementation, a process for depositing a film is provided and includes sequentially exposing a surface to a first organic compound and a second organic compound to form a film on the surface during a cyclic vapor deposition process, where the film has a dielectric constant (k) of 3 or less.

A method of forming a metal phosphide film on a substrate using a cyclical deposition process includes contacting the substrate with a vapor-phase metal precursor, contacting the substrate with a vapor-phase halogenating agent, and contacting the substrate with a vapor-phase phosphorus-containing precursor. A method of filling a gap includes placing a substrate in a reaction chamber, wherein the substrate comprises a gap; forming a flowable metal halide on the substrate to fill the gap; and converting the flowable metal halide into a metal phosphide.

A patterning method for semiconductor processes is provided, comprising: forming a photoresist layer on a substrate; patterning the photoresist layer; and forming a guide template on the substrate based on the patterned photoresist layer; coating the guide template with a neutral layer; removing the neutral layer that is not bonded to the substrate; coating a block copolymer; driving the block copolymer to undergo microphase separation; and guiding the block copolymer to self-assemble according to the guide template to form an array pattern comprising polar and nonpolar phases; selectively oxidizing the nonpolar phase; depositing a nonmetallic oxide in the oxidized nonpolar phase using a selective penetration deposition process; removing the polar and nonpolar phases to form a nonmetallic oxide layer corresponding to the structure of the nonpolar phase in the array pattern; and transferring the pattern of the nonmetallic oxide layer to the substrate using an etching process with the nonmetallic oxide layer as a mask.

The present application belongs to the technical field of semiconductor, and particularly relates to a gate structure containing an effective work function adjustable work function metal layer and a preparation method thereof. The gate structure comprises a semiconductor substrate, a gate dielectric layer, a work function metal layer, and the material of the work function metal layer is TiAlC. The work function metal layer is changed in density so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage, and other gate layers. In the process of forming the work function metal layer on the gate dielectric layer, the work function metal layer with different densities is obtained through different process conditions, so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage. The different process conditions include the pretreatment process of the gate dielectric layer and / or the deposition process of the work function metal layer. The present application only needs one layer of work function metal layer to realize the regulation of the threshold voltage, meets the multi-threshold voltage device, avoids the complex process of other work function regulation methods, and reduces the manufacturing cost.

This invention discloses a CrN-W / DLC composite coating for WE43 magnesium alloy and its preparation method, belonging to the field of surface engineering and materials processing technology. The preparation method includes: pretreating the WE43 magnesium alloy substrate, placing it in a thin film deposition system, evacuating the system, introducing an Ar / N2 mixed gas, and using a Cr target for reactive magnetron sputtering deposition to form a CrN transition layer. During the deposition process, a W target is simultaneously introduced and co-deposited with the Cr target using reactive magnetron sputtering to obtain the CrN-W transition layer. Using a PECVD process, a carbon source precursor gas is introduced, and under the action of radio frequency plasma, it dissociates to form highly reactive species. These species are adsorbed, recombined, and cross-linked on the surface of the CrN-W transition layer to form a DLC functional layer, resulting in the CrN-W / DLC composite coating. The composite coating of this invention exhibits excellent bonding strength, wear resistance, and low friction performance, significantly improving the service performance of WE43 magnesium alloy.

The invention belongs to the technical field of micro-nano machining, and particularly relates to a hollow metal nano array and a preparation method and application thereof. According to the invention, a regular polymer nano array is prepared based on an ultraviolet light curing nano imprinting technology and a plasma etching technology; then metal evaporation is carried out in combination with an electron beam evaporation dip angle evaporation process, so that the surface of the polymer nano array is partially coated with metal, and a polymer / metal composite nano array with a notch is obtained; and dissolving by using a solvent to remove the water-soluble polymer nano-columns in the polymer / metal nano-array with the notches, so as to prepare the large-area hollow metal nano-array of which the morphology, the size and the period can be flexibly designed. Sulfydryl benzaldehyde molecules are fixed on the surface of the hollow metal nano array to form an SERS (Surface Enhanced Raman Scattering) substrate which is used for detecting hydrazine hydrate. The SERS substrate prepared on the basis of the hollow metal nano array shows high sensitivity, specificity, repeatability and stability.

Vapor phase methods of depositing a metal or a semimetal—comprising materials on a substrate are provided. In the methods, various metal or semimetal precursors may be used together with reactants that may generate hydrogen radical or amino radical to react with the metal or semimetal precursor to deposit the metal or semimetal—comprising material on the substrate. Further provided are materials and structures deposited by the disclosed methods, as well as deposition assemblies.

This invention discloses a method for large-scale batch preparation of bulk semiconductor materials using natural ores. The method uses natural ores such as galena as raw materials. After weighing and vacuum sealing in an inert gas environment, the materials are placed in a tube furnace with at least two temperature zones. By controlling the heating rate, temperature difference between the zones, and holding time, the ores undergo a reaction and deposition process at high temperatures to obtain dense bulk semiconductor materials. By introducing halide or sulfide dopants and adjusting the doping ratio, carrier concentration and mobility can be effectively improved. The resulting material achieves a power factor of 1.5–2.0 mW·m⁻¹·K⁻² at room temperature and a thermoelectric figure of merit (zT) of over 0.4 in the high-temperature zone. Compared with existing synthesis methods that rely on high-purity raw materials, this invention has a simple process flow, low cost, and high efficiency, avoiding the risk of tube explosion caused by sulfur vapor. It is suitable for large-scale application in the fabrication of thermoelectric power generation devices, refrigeration devices, and infrared detection devices.

The application relates to the technical field of metal processing, and discloses a surface nanometer strengthening treatment system for metal pieces, which comprises a data acquisition module, an intelligent decision module, a process simulation module, a verification and optimization module and an instruction output module, extracts initial state data of the surface of the metal pieces, carries out nanometer strengthening decision analysis on the initial state data to obtain a nanometer strengthening process parameter sequence of the surface of the metal pieces, simulates an electrochemical deposition process on the nanometer strengthening process parameter sequence to obtain nanocrystalline layer growth prediction data of the surface of the metal pieces, carries out stability verification on the nanocrystalline layer growth prediction data, adjusts weight parameters in the nanometer strengthening decision analysis when the verification fails, obtains an optimized process parameter sequence of the surface of the metal pieces, encodes the optimized process parameter sequence to obtain nanometer strengthening treatment instructions, and can improve the process research and development efficiency and production implementation efficiency of the surface nanometer strengthening treatment of the metal pieces.

The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.

This invention discloses an image sensor and its manufacturing method. The method includes: Step S1, providing a wafer including a substrate and a plurality of gates formed on the substrate, with adjacent gates forming a gate spacer; the substrate is ion-implanted to form an active / drain region; Step S2, depositing an oxide layer on the surface of the gate spacer and above the gates; Step S3, performing high-temperature rapid annealing on the wafer to activate the active / drain regions; Step S4, depositing a silicon nitride layer on the oxide layer surface using an HCD process. This invention, by depositing a silicon nitride layer using the HCD process, not only avoids lattice damage caused by plasma in existing deposition processes, but also, due to the high process temperature and long processing time of the HCD process, the prolonged and sufficiently high temperature heat treatment effectively improves the uniformity of implanted ion distribution and lattice repair, thereby significantly improving WP performance by approximately 35%.

The present invention relates to a thermal radiation trap for measuring the internal temperature of a chamber, and more specifically, to a thermal radiation trap for accurately and stably measuring the internal temperature of a deposition chamber, and even more specifically, to a thermal radiation trap for measuring the internal temperature of a chamber that provides a thermal radiation trap in the form of a deep groove formed inside a deposition chamber and a method for measuring temperature using the same. According to the present invention, the effect of enabling stable temperature measurement is provided by minimizing the influence of temperature deviation on the chamber surface. In addition, it provides the effect of being able to measure a constant internal temperature without being affected by temperature changes occurring during the deposition process.

A method of forming a metal phosphide film on a substrate using a cyclic deposition process includes contacting the substrate with a gas phase metal precursor, contacting the substrate with a gas phase halogenating agent, and contacting the substrate with a gas phase phosphorus-containing precursor. A method of filling a gap includes placing a substrate in a reaction chamber, wherein the substrate includes a gap; forming a flowable metal halide on the substrate to fill the gap; and converting the flowable metal halide to a metal phosphide.

This invention discloses a high-crystal-quality light-emitting diode epitaxial wafer and its fabrication method. The method includes: after depositing a buffer layer on a substrate and before depositing a three-dimensional nucleation layer, performing a high-temperature recrystallization treatment on the buffer layer under low-pressure and high-temperature conditions in an atmosphere containing H2 and NH3 but without N2; subsequently, sequentially depositing a low-temperature three-dimensional nucleation layer, a three-dimensional nucleation transition layer, and a high-temperature three-dimensional nucleation layer in the same N2-free atmosphere; wherein the deposition process of the three-dimensional nucleation transition layer includes a gradual increase in deposition temperature and trimethylgallium flux with increasing deposition time. This invention, through buffer layer recrystallization treatment and the use of a "double-gradient" transition layer process to grow the three-dimensional nucleation layer in an N2-free atmosphere, effectively reduces N vacancies and GaN epitaxial layer defects, improves crystal quality, reduces leakage current, and enhances electrostatic breakdown resistance.

The invention relates to a method for depositing a profiled product onto a substrate, the profiled product being made of an elastomeric compound and cut to a predefined length before being deposited onto said substrate, the two ends of the profiled product joining together when the profiled product is deposited onto said substrate, the depositing method comprising a step of applying marks to the two ends of the profiled product, this marking step being carried out before the profiled product is deposited onto the substrate, and the depositing method comprising a step of acquiring at least one image of the junction of the two ends of the profiled product and the marks affixed to these two ends, this acquisition step being carried out after the profiled product is deposited onto the substrate.The deposition process is characterized in that the markings applied to the ends of the profiled product are applied with an ink visible only under ultraviolet or infrared radiation, or with an ink that disappears under the effect of heat when the profiled product is subjected to a temperature above 50°C, for example between 90 and 150°C. Figure in the abstract: none.

The present application relates to the field of solar cells, and particularly relates to a TBC cell and a preparation method thereof. A predetermined pattern is formed on a polysilicon layer on the back of a silicon wafer by printing a sucrose solution using screen printing, and a temporary carbon film mask is formed by carbonizing the sucrose solution after drying. Then, an aluminum oxide sol is sprayed on the surface of the silicon wafer with the carbon film mask, the film plays a self-protection role in the deposition process, and is easy to remove after deposition. The method only needs to perform deposition of a tunneling oxide layer and a polysilicon layer once, greatly reducing the cost of mask, polysilicon layer deposition and wet etching in the production process.

The embodiment of the application provides a three-dimensional porous boron nitride sulfur-loaded material, a positive plate and a preparation method thereof. The three-dimensional porous boron nitride sulfur-loaded material comprises: a positive current collector; and a three-dimensional porous boron nitride modified layer which is in-situ grown through a gas deposition process and is coated on the surface of the positive current collector. The technical scheme of the application can effectively solve the technical problems of the shuttle effect caused by the dissolution of polysulfides and the slow oxidation-reduction reaction kinetics in the lithium-sulfur battery in the prior art.

An electronic device manufacturing system configured to obtain sensor data associated with a deposition process performed in a process chamber to deposit a film stack on a surface of a substrate. The film stack can include a known film pattern and an unknown film pattern. The manufacturing system is further configured to input the sensor data into a first trained machine-learning model to obtain a first output value of the first trained machine-learning model. The first output value can be associated with the known film pattern. The manufacturing system is further configured to input the first output value into a second trained machine-learning model to obtain a second output value of the second trained machine-learning model. The second output value can be indicative of metrology data of the known film pattern.

A preparation method of an active layer of a flexible organic solar cell based on polymer toughening, comprising: dissolving PM6 in toluene to configure a donor solution; dissolving BTP-eC9 in toluene to configure a solution, adding 0-20wt% of PM6 and 1,3-dibromo-5-chlorobenzene to form an acceptor solution; coating the donor solution and the acceptor solution on the surface of the PEDOT:PSS hole transport layer of the flexible organic solar cell in turn twice, and annealing after each coating to obtain the active layer of the flexible organic solar cell based on polymer toughening. The application utilizes the dilution of the acceptor solution by the polymer donor PM6 to inhibit excessive crystallization of the acceptor, utilizes the compatibility difference between the donor and the acceptor to optimize the solution penetration process of the last solution to the bottom layer of the donor film in the deposition process, spontaneously induces the gradient distribution of the active layer of the donor and the acceptor, and cooperatively improves the energy conversion efficiency and the mechanical stability of the flexible organic solar cell.

This invention belongs to the field of conductive materials technology. It provides a method for preparing submicron hollow silver powder, employing a nanobubble generator to produce bubbles in a reaction solution. A spiral submicrochannel reactor is used to create a hypergravity field to control the reaction solution in the reactor, achieving high-density directional deposition and crystallization of silver on the surface of spherical or near-spherical bubbles, thus regulating the crystal structure, morphology, density, and particle size of the hollow silver powder. By optimizing the chemical deposition process and precisely controlling the nucleation and crystallization processes, dispersibility is improved, resulting in submicron hollow silver powder with high sintering activity and excellent conductivity, significantly improving the conversion efficiency of photovoltaic cells.

The application discloses a kind of high-precision stable control methods for industrial metal gallium electrolytic deposition process temperature, comprising: the dynamic mechanism model of metal gallium electrolytic process temperature is established, and the steady-state temperature of electrolytic process is solved;Collect metal gallium electrolytic process temperature control input and temperature output data, and construct input-output data set;According to the preset mechanism enhancement proportion, replace several data points of original output data set with steady-state temperature value, and obtain mechanism-enhanced output data set;Using mechanism-enhanced output data set and original input data set, a subspace identification method is used to obtain a temperature prediction model;According to Lyapunov theorem, the stable solution of control quantity is solved, and the objective function of asymptotically stable model predictive control is constructed using the temperature prediction model;And under the premise of meeting the system constraint condition, the optimal control quantity sequence of temperature is solved by rolling optimization.The application can efficiently and stably control the temperature of metal gallium electrolytic deposition process.

The present invention relates to a deposition apparatus for a superconductor, the apparatus comprising: a withdrawal unit around which a wire rod unit is wound; a plurality of chambers through which the wire rod unit withdrawn from the withdrawal unit passes and which are spaced apart from one another so as to perform individual deposition processes; and a retraction unit which retracts the wire rod unit having passed through the chambers, wherein the wire rod unit is withdrawn from the withdrawal unit and then undergoes deposition while sequentially passing through the plurality of chambers, disposed between the withdrawal unit and the retraction unit, before retracting into the retraction unit. The wire rod unit is wound around each chamber unit one or more times such that the deposition time for the wire rod unit, in the limited inner spaces of the chamber units, is extended and thus the size of the entire facility can be reduced.

This application provides a semiconductor device and a method for manufacturing the same, as well as an electronic device. The method includes: providing a substrate comprising a gate and / or a source and a drain; sequentially forming a first insulating material layer, a spin-coated carbon layer, an anti-reflective coating, and a patterned photoresist layer on the substrate; using the patterned photoresist layer as a mask, etching the anti-reflective coating and the spin-coated carbon layer to form a first via exposing a portion of the first insulating material layer; performing a deposition process to form a second insulating material layer at least on the sidewalls of the first via to define a second via; using the second insulating layer as a mask, etching the first insulating material layer at the bottom of the second via to expose the gate and / or the source and drain. The solution of this application can reduce the critical size of the second via, improve the integration and reliability of the device, and also repair linewidth roughness, line edge roughness, and roundness defects.

A thin film deposition system deposits thin films on semiconductor wafers. The thin film deposition system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for a next deposition process by receiving static process condition and target thin film data. The analysis model can identify dynamic process condition data that, together with the static process condition data, can generate predicted thin film data that matches the target thin film data. The deposition system then uses the static and dynamic process condition data for the next thin film deposition process.