151 results about "Dielectric surface" patented technology

Disclosed herein are bonded structures and methods of forming the bonded structures. In some embodiments, the bonded structures include a first element having an inorganic dielectric surface, a second element having an organic dielectric surface, an interface layer between the first and second elements and bonded to the inorganic and organic dielectric surfaces. The method of forming the bonded structure includes providing the first and second elements, exposing the inorganic dielectric surface to a silane coupling agent to form the interface layer, contacting the organic dielectric surface to the interface layer, and heating the first element, second element, and interface layer to bond the first element to the second element.

Methods for fabricating branched substrates having conductive contact pads and hybrid dielectric bonding surfaces for directly bonding dies and electrically connecting them to the contact pads. A branched substrate can include a main portion and one or more branch portions hybrid bonded to the main portion. Some sections of the branched substrate can be flexible to allow deformable electrical connection between components that are hybrid bonded to different regions of the branched substrate. A flexible branch portion may provide electrical connection between vertically separated layers of two components. The method includes directly bonding a branch portion of the branched substrate to the main portion of the branched substrate via a hybrid bonding interface comprising a conductive interface between contact pads of the main and branch portions and a hybrid bonded dielectric interface between dielectric surfaces of the of the main and branch portions.

In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.

A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions. The method includes forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the first conductive layer, forming a sacrificial layer in the one or more openings, recessing the sacrificial layer, forming a support layer on the recessed sacrificial layer in each of the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric fill on the support layer, replacing the first conductive layer in the one or more openings with a second conductive layer, selectively forming a two-dimensional (2D) material layer on the second conductive layer, forming a first etch stop layer on the dielectric fill and the support layer, forming a second etch stop layer on the first etch stop layer and the 2D material layer, forming a dielectric material on the second etch stop layer, forming a contact opening through the dielectric material, the second etch stop layer, and the 2D material layer to expose a top surface of the second conductive layer, and forming a first conductive feature in the contact opening.

Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure can include selectively depositing the dielectric film via atomic layer deposition after features filled with metal in a top layer of oxide in an oxide-metal-substrate stack. In order to selectively deposit the dielectric film, the metal may be covered with a polymer which can be burned off. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

The current disclosure relates to methods and assemblies for selectively depositing metal-containing materials, such as metal oxides, on different surfaces of a semiconductor substrate by cyclic vapor deposition techniques, including atomic layer deposition. The metal-containing material is deposited using a metal precursor having a metal atom bound to an acetamidinato ligand, such as dialkylacetamidinato ligand. The metal-containing material may be deposited on a metal surface relative to a dielectric surface, or to a dielectric surface relative to a metal surface, depending on the process flow. The current disclosure further relates to layers, structures and semiconductor devices deposited according to the methods disclosed herein, as well as to semiconductor processing assemblies configured and arranged to perform said methods.

Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl4), hydrogen (H2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees C.; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A dielectric film-oxide-metal-substrate structure can be formed with the dielectric film on the top surface of the stack. A multi-material etch can be used etch features in the dielectric film and the oxide in a dielectric film-oxide-metal-substrate stack. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

The utility model provides a kind of high-power thick film heating device for new energy vehicle, including thick film heating plate, the upper surface of thick film heating plate is equipped with ceramic dielectric surface layer, the lower surface of thick film heating plate is equipped with metal base plate face, the upper of thick film heating plate is equipped with upper flow channel cavity mechanism, and lower is equipped with lower flow channel cavity mechanism;The utility model is by using single-layer thick film heating plate, and cooperate upper flow channel cavity mechanism and lower flow channel cavity mechanism to carry out up and down parallel flow guiding to heat conducting medium, so as to utilize heat conducting medium to synchronously absorb the heat of the upper and lower two sides of thick film heating plate, so as to reach double-sided heat exchange effect, to improve thick film heating device heat exchange coefficient and heat exchange area, to break through the maximum power density limit that thick film heating plate can use on traditional design, make thick film heating device realize higher electric power output under the same area, and simultaneously due to the improvement of heat exchange capacity, the thermal conversion efficiency of its product is also improved.

A method for selectively depositing material on a dielectric surface relative to a metal surface is disclosed. The metal surface is protected with a self-assembled monolayer comprising N-heterocyclic carbides before depositing a liner or barrier layer on an adjacent dielectric surface.

Methods for pre-cleaning a substrate having metal and dielectric surfaces are described. A substrate including a surface structure having a metal bottom, a dielectric sidewall, and a field of dielectric is exposed to a dual plasma process in a processing chamber to remove chemical residues and / or impurities from the metal bottom, the dielectric sidewall, and / or the field of dielectric, and / or to repair surface defects in the dielectric sidewall and / or the field of dielectric. The dual plasma process includes a direct plasma and a remote plasma.

The invention discloses a preparation method of a high-frequency resin multilayer co-extrusion film substrate for a satellite antenna. The preparation method comprises the following steps: S1, uniformly mixing polytetrafluoroethylene dispersion resin powder and an extrusion aid with a high-dielectric filler and a low-dielectric filler respectively to prepare a high-dielectric paste material and a low-dielectric paste material; s2, co-extruding the high-dielectric paste and the low-dielectric paste to obtain a three-layer composite sheet with a low-dielectric surface layer and a high-dielectric core layer; s3, calendering the three-layer composite sheet obtained in the step S2 to obtain a calendered sheet; and S4, heating the calendered sheet to obtain the high-frequency resin multi-layer co-extrusion film substrate for the satellite antenna. According to the production method of the high-frequency resin multi-layer co-extrusion film substrate for the satellite antenna, high-medium paste and low-medium paste are jointly extruded into a three-layer composite sheet from an extruder, and the technological process is remarkably shortened; the high-frequency resin multi-layer co-extrusion film substrate for the satellite antenna is prepared by calendering and heating the three layers of composite sheets, and the high-frequency resin multi-layer co-extrusion film substrate is not prone to layering and foaming after being heated.

In some embodiments, methods are provided for simultaneously and selectively depositing a first material on a first surface of a substrate and a second, different material on a second, different surface of the same substrate using the same reaction chemistries. For example, a first material may be selectively deposited on a metal surface while a second material is simultaneously and selectively deposited on an adjacent dielectric surface. The first material and the second material have different material properties, such as different etch rates.

Methods for surface conditioning based on cyclic processing are disclosed. The method includes activating the surface, removing excess material from the surface, applying a low energy particle treatment to the surface, and repeating the above steps until the surface has a desired smoothness. The method can be applied to various surfaces, including semiconductor surfaces, metal surfaces, dielectric surfaces, and 2D material surfaces, as well as patterned and non-patterned surfaces. The low energy particle treatment may be etch or deposition, and the process may be combined with ion beam shaping techniques and angled particle beam etch to improve surface conditioning. Methods of making substrates and epitaxial material grown surfaces are also provided.

The invention discloses a molecular dynamics simulation method for electron-induced gas desorption, and belongs to the technical field of molecular simulation. The method comprises the following steps: firstly, constructing an aluminum oxide molecular model, and then simulating adsorption equilibrium of hydrogen on the surface of aluminum oxide at different temperatures and air pressures by adopting a giant regular Monte Carlo method to obtain a stable adsorption configuration; then, based on the configuration, an electron force field is adopted to introduce explicit electron particles to simulate electron beam bombardment, and an electron-induced gas desorption kinetic process is simulated under a molecular dynamics framework; and finally, performing quantitative analysis on the desorption product. Through full-atom molecular dynamics simulation, coherent research from gas adsorption to electron-induced desorption is realized, the limitation that related experimental measurement is difficult and a micromechanism is difficult to reveal under a high-voltage condition is overcome, and an effective simulation tool is provided for deeply understanding a physical mechanism of dielectric surface gas desorption-induced discharge.

Methods for cleaning a substrate are disclosed. The substrate comprises a dielectric surface and a metal surface. The methods comprise providing a cleaning agent to the reaction chamber.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

A method for increasing dielectric bonding strength during wafer-level processing is incorporated into a hybrid bonding process. A method may include immersing a substrate into a chemical bath at atmospheric conditions where the chemical bath forms a self-assembled monolayer on metal surfaces of the substrate and selectively depositing a high-k dielectric material to form a dielectric cap on dielectric surfaces of the substrate absent of the self-assembled monolayer.

Methods and apparatuses for using molecules having a carbon-nitrogen triple bond as inhibitors on metal-containing surfaces to selectively deposit dielectric material on a dielectric surface on a substrate surface having a metal-containing surface and a dielectric surface are provided. A method for processing substrates comprises providing a substrate having a first material and a second material thereon to a process chamber, exposing the substrate to an isonitrile inhibitor to adsorb onto the first material to inhibit deposition on the first material, and depositing a dielectric film on the second material.

The invention relates to a method for transferring a thin film (7) onto a final carrier (11), the thin film (7) and the final carrier (11) having different coefficients of thermal expansion. The method comprises transferring the thin film (7) onto an intermediate carrier (5) at a first bonding interface (IA1) and forming a dielectric surface layer (10) on the exposed face of the thin film (7). The method further comprises activating the dielectric surface layer (10) by exposing it to a plasma having a radiofrequency power density of strictly greater than 1.1 W / cm^2, then assembling the thin film (7) via the dielectric surface layer (10) to the final carrier (11) and thus defining a second bonding interface (IA2). Finally, the method comprises mechanically stressing the final carrier (11) and / or the intermediate carrier (5) to remove the intermediate carrier (5) from the thin layer (7) at the first bonding interface (IA1).

A substrate support includes a top plate including a dielectric material and an outer dielectric surface configured to support a substrate, printed heater sealed within the top plate, and a printed electrostatic chuck (ESC) circuit sealed within the top plate. A printed wiring layer may also be sealed within the top plate. The printed heater includes a heater material printed on a first interior dielectric surface of the top plate. The printed ESC circuit includes an electrically conductive material printed on a second interior dielectric surface of the top plate. When included, the printed wiring layer may include wiring traces printed on a third interior dielectric surface of the top plate. A dielectric base layer with vias electrically coupling the wiring traces to the printed heater may be included between the printed wiring layer and the printed heater.

A system and a method for a monolithic wordline (WL) are disclosed. A structure includes a conductive element and a first dielectric. The conductive element connects an array WL in an array area at a first edge to a pad WL in a pad area at a second edge. The conductive element is disposed in an interconnecting area between the first edge and the second edge. The first dielectric is disposed on the array WL, the conductive element, and the pad WL. The first dielectric has a dielectric surface extending from the interconnecting area to the pad area. The conductive element and the first dielectric form a monolithic WL from the array WL and the pad WL through the second edge.

A composition for cleaning a microelectronic device substrate is provided. The composition is useful for cleaning in-process microelectronic device substrates possessing exposed cobalt, molybdenum, copper, molybdenum, tungsten, and dielectric surfaces. Also provided is a method for cleaning such devices and a kit comprising one or more of the components of the composition.

Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and / or carbon removal, is also disclosed.

A method of selective deposition that includes disposing in a deposition chamber a substrate having metallic and dielectric surfaces. The deposition chamber is connected to a bubbler that contains a 1,2,3-triazolium salt and / or a carboxylate zwitterion form of the 1,2,3-triazole, which are precursors to free 1,2,3-triazol-5-ylidene. By heating the bubbler, gaseous free 1,2,3-triazol-5-ylidene was generated which moved into the deposition chamber, where the 1,2,3-triazol-5-ylidene selectively chemisorbed onto the metallic surface(s).

Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and / or carbon removal, is also disclosed.

The embodiment of the invention provides a patch antenna, a PCB module and electronic equipment. Relates to the antenna field. Comprising a dielectric body, a radiating body and a fixing assembly, and the radiating body comprises a first metal sheet, a second metal sheet, a side metal sheet and a feed metal sheet which are connected in sequence; the feed metal sheet is arranged on a first dielectric surface of the dielectric body, the side metal sheet is arranged on a second dielectric surface of the dielectric body, the first dielectric surface is the bottom surface of the dielectric body, the second dielectric surface is the side surface of the dielectric body, and the first dielectric surface is adjacent to the second dielectric surface; the first metal sheet and the second metal sheet are arranged on a third dielectric surface of the dielectric body, and the third dielectric surface is the top surface of the dielectric body.

Structures for semiconductor devices having a high dielectric film on the upper surface of the structure can be used to form semiconductor devices consisting of a hybrid junction structure in which the dielectric surface area is reduced and the pitch of the metal studs is reduced. For example, the dielectric constant of the dielectric film may be greater than 7 or 8. Semiconductor devices can be formed by hybrid junctioning a dielectric film of a structure to a dielectric film of a similar structure. Dielectric film-oxide-metal-substrate structures can be formed so that the dielectric film is on the upper surface of the laminate. Multi-material etching can be used to etch features into the dielectric film and the oxide in the dielectric film-oxide-metal-substrate stack. Chemical mechanical polishing techniques can be used to precisely form the surface of the structure in preparation for hybrid junctions.

Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and / or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.