51 results about "Dielectric surface" patented technology

Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

The utility model provides a kind of high-power thick film heating device for new energy vehicle, including thick film heating plate, the upper surface of thick film heating plate is equipped with ceramic dielectric surface layer, the lower surface of thick film heating plate is equipped with metal base plate face, the upper of thick film heating plate is equipped with upper flow channel cavity mechanism, and lower is equipped with lower flow channel cavity mechanism;The utility model is by using single-layer thick film heating plate, and cooperate upper flow channel cavity mechanism and lower flow channel cavity mechanism to carry out up and down parallel flow guiding to heat conducting medium, so as to utilize heat conducting medium to synchronously absorb the heat of the upper and lower two sides of thick film heating plate, so as to reach double-sided heat exchange effect, to improve thick film heating device heat exchange coefficient and heat exchange area, to break through the maximum power density limit that thick film heating plate can use on traditional design, make thick film heating device realize higher electric power output under the same area, and simultaneously due to the improvement of heat exchange capacity, the thermal conversion efficiency of its product is also improved.

A method for selectively depositing material on a dielectric surface relative to a metal surface is disclosed. The metal surface is protected with a self-assembled monolayer comprising N-heterocyclic carbides before depositing a liner or barrier layer on an adjacent dielectric surface.

Methods for pre-cleaning a substrate having metal and dielectric surfaces are described. A substrate including a surface structure having a metal bottom, a dielectric sidewall, and a field of dielectric is exposed to a dual plasma process in a processing chamber to remove chemical residues and / or impurities from the metal bottom, the dielectric sidewall, and / or the field of dielectric, and / or to repair surface defects in the dielectric sidewall and / or the field of dielectric. The dual plasma process includes a direct plasma and a remote plasma.

In some embodiments, methods are provided for simultaneously and selectively depositing a first material on a first surface of a substrate and a second, different material on a second, different surface of the same substrate using the same reaction chemistries. For example, a first material may be selectively deposited on a metal surface while a second material is simultaneously and selectively deposited on an adjacent dielectric surface. The first material and the second material have different material properties, such as different etch rates.

Methods for surface conditioning based on cyclic processing are disclosed. The method includes activating the surface, removing excess material from the surface, applying a low energy particle treatment to the surface, and repeating the above steps until the surface has a desired smoothness. The method can be applied to various surfaces, including semiconductor surfaces, metal surfaces, dielectric surfaces, and 2D material surfaces, as well as patterned and non-patterned surfaces. The low energy particle treatment may be etch or deposition, and the process may be combined with ion beam shaping techniques and angled particle beam etch to improve surface conditioning. Methods of making substrates and epitaxial material grown surfaces are also provided.

The invention discloses a molecular dynamics simulation method for electron-induced gas desorption, and belongs to the technical field of molecular simulation. The method comprises the following steps: firstly, constructing an aluminum oxide molecular model, and then simulating adsorption equilibrium of hydrogen on the surface of aluminum oxide at different temperatures and air pressures by adopting a giant regular Monte Carlo method to obtain a stable adsorption configuration; then, based on the configuration, an electron force field is adopted to introduce explicit electron particles to simulate electron beam bombardment, and an electron-induced gas desorption kinetic process is simulated under a molecular dynamics framework; and finally, performing quantitative analysis on the desorption product. Through full-atom molecular dynamics simulation, coherent research from gas adsorption to electron-induced desorption is realized, the limitation that related experimental measurement is difficult and a micromechanism is difficult to reveal under a high-voltage condition is overcome, and an effective simulation tool is provided for deeply understanding a physical mechanism of dielectric surface gas desorption-induced discharge.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

A system and a method for a monolithic wordline (WL) are disclosed. A structure includes a conductive element and a first dielectric. The conductive element connects an array WL in an array area at a first edge to a pad WL in a pad area at a second edge. The conductive element is disposed in an interconnecting area between the first edge and the second edge. The first dielectric is disposed on the array WL, the conductive element, and the pad WL. The first dielectric has a dielectric surface extending from the interconnecting area to the pad area. The conductive element and the first dielectric form a monolithic WL from the array WL and the pad WL through the second edge.

A composition for cleaning a microelectronic device substrate is provided. The composition is useful for cleaning in-process microelectronic device substrates possessing exposed cobalt, molybdenum, copper, molybdenum, tungsten, and dielectric surfaces. Also provided is a method for cleaning such devices and a kit comprising one or more of the components of the composition.

Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and / or carbon removal, is also disclosed.

A method of selective deposition that includes disposing in a deposition chamber a substrate having metallic and dielectric surfaces. The deposition chamber is connected to a bubbler that contains a 1,2,3-triazolium salt and / or a carboxylate zwitterion form of the 1,2,3-triazole, which are precursors to free 1,2,3-triazol-5-ylidene. By heating the bubbler, gaseous free 1,2,3-triazol-5-ylidene was generated which moved into the deposition chamber, where the 1,2,3-triazol-5-ylidene selectively chemisorbed onto the metallic surface(s).

Structures for semiconductor devices having a high dielectric film on the upper surface of the structure can be used to form semiconductor devices consisting of a hybrid junction structure in which the dielectric surface area is reduced and the pitch of the metal studs is reduced. For example, the dielectric constant of the dielectric film may be greater than 7 or 8. Semiconductor devices can be formed by hybrid junctioning a dielectric film of a structure to a dielectric film of a similar structure. Dielectric film-oxide-metal-substrate structures can be formed so that the dielectric film is on the upper surface of the laminate. Multi-material etching can be used to etch features into the dielectric film and the oxide in the dielectric film-oxide-metal-substrate stack. Chemical mechanical polishing techniques can be used to precisely form the surface of the structure in preparation for hybrid junctions.

Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. A substrate with a metal surface, a dielectric surface and an aluminum oxide surface has a blocking layer deposited on the metal surface using an alkylsilane.

A method is provided to mitigate surface damage to probe pads during direct bonding of a substrate. The method and layer structure fabricate a semiconductor substrate for direct bonding processing by restoring a flat direct bonding surface after the probe pad surface is damaged during test probing. An exemplary method fills the damaged probe pad surface with a series of metals and oxides, and constructs a dielectric surface and interconnects for hybrid bonding. The interconnects can be connected to the probe pads and / or other electrical contacts on the substrate. The layer structure is described to increase the yield and reliability of the resulting direct bonding processing. Another process constructs probe pads on a penultimate metallization layer and applies a direct bonding dielectric layer and a metal damascene process without increasing the mask layer count. Another exemplary process and associated layer structure recesses the probe pads into a lower metallization layer and allows cavities on the probe pads.

This invention provides a method for depositing a metal film with low resistivity. [Solution] A method for filling features, including metal and dielectric surfaces, with a conductive material involves cleaning the metal surface with little or no damage to the dielectric surface. After cleaning, the features can be exposed to one or more reactants and then filled with the conductive material in an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. The deposition may be selective or non-selective to the metal surface. In some embodiments, the filled features are barrierless, so that the conductive material is in direct contact with the metal and dielectric surfaces without the interposition of a barrier or adhesive layer.

Methods for selective deposition of silicon oxide films on metal or metallic surfaces relative to dielectric surfaces are provided. A dielectric surface of a substrate may be selectively passivated relative to a metal or metallic surface, such as by exposing the substrate to a silylating agent. Silicon oxide is then selectively deposited on the metal or metallic surface relative to the passivated oxide surface by contacting the metal surface with a metal catalyst and a silicon precursor comprising a silanol.

The present invention provides an apparatus, method, and system for monolithic formation of array word lines and pad word lines within a memory circuit. [Solution] The present invention provides a system for monolithic word lines in a memory circuit, wherein the structure for connecting the word lines includes a conductive element and a first dielectric. The conductive element connects the array word line in the array region at the first edge to the padded word line in the pad region at the second edge. The conductive element is located within the interconnection region between the first and second edges. The first dielectric is located on the array word line, the conductive element, and the padded word line. The first dielectric has a dielectric surface that extends from the interconnection region to the pad region. The conductive element and the second dielectric form a monolithic word line from the array word line and the padded word line through the second edge.

A process of area selective deposition (ASD), a process of atomic layer deposition (ALD), and a process of device fabrication include forming a passivation layer on a metal surface of a substrate and forming a surface-bound polymer film on a dielectric surface of the substrate. The forming the passivation layer includes binding metal-selective inhibitor molecules to the metal surface. A device is formed in a process that includes forming a passivation layer on a metal surface of a substrate and forming a surface-bound polymer film on a dielectric surface of the substrate. The forming the passivation layer includes binding metal-selective inhibitor molecules to the metal surface. A composition for area selective deposition (ASD) includes a metal-selective inhibitor molecule have the following structure:wherein X is a metal-binding group, R is an organic ligand, and n is an integer greater than or equal to zero.

A system and method for forming a bonded integrated circuit, comprising dispensing a dielectric material on a first side of an integrated circuit, shaping the dielectric material on the first side of the integrated circuit to form a first dielectric surface; and dispensing a conductive material between a first printed circuit board (PCB) top surface and a top surface of the integrated circuit to form a first connection, the first connection situated on the first dielectric surface.

Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.

This invention relates to a method for preparing a superhydrophobic dielectric surface by transferring micro / nano structures. The method includes the following steps: pretreating a substrate; spin-coating a dielectric layer onto the substrate using a spin coater; covering the substrate with a Teflon film during the heating and film formation process; and then peeling it off under heavy pressure using a press to transfer the porous structure of the Teflon film to the dielectric layer; thus obtaining a superhydrophobic dielectric surface. Compared with existing technologies, this invention has the advantages of simple process, low cost, and wide applicability.

The disclosure relates to mitigating surface damage to probe pads when preparing direct bonds of substrates. A method of mitigating surface damage of a probe pad when preparing a direct bond of a substrate is provided. Methods and layer structures produce a semiconductor substrate for a direct bonding process by restoring a flat direct bonding surface after detecting that a pad surface is damaged during a test probe. An exemplary method fills a series of metals and oxides on the broken probe pad surface, and constructs a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads and / or other electrical contacts of the substrate. Layer structures are described for increasing the output and reliability of the resulting direct bonding process. Another process builds a probe pad on the last but one metallization layer, and applies a direct bond dielectric layer and a metal damascene process without increasing the count of the mask layer. Another exemplary process and related layer structures sink the probe pad to a lower metallization layer and allow for a cavity on the probe pad.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

A surface recovery process that restores the hydrophobicity of dielectric surfaces and promotes selective deposition of metal-fill such as molybdenum onto metal-containing surfaces while reducing or preventing growth on the dielectric surfaces. Additionally, the surface recovery process reduces film loss against subsequent wet etching processes such as DHF. The recovery precursor soak is performed with optional UV (concurrent or sequential) to react with silanols on damaged dielectric surface to replenish -CHS and recover hydrophobicity of the dielectric surface. The recovery precursor is a carbon-containing recovery precursor, for example, organohalosilanes, esters, silyl ethers, organoaminosilanes, silyl esters, hydrocarbons, or a combination thereof.

The current disclosure relates to method for selectively filling a gap on substrate with a material comprising molybdenum. In the method, molybdenum-containing material is deposited into a gap by a cyclic deposition process. The method comprises providing a substrate into a reaction chamber, wherein the substrate comprises at least one gap and wherein the gap comprises a silicon surface and a dielectric surface. The method further comprises executing at least one deposition cycle. A deposition cycle comprises providing a molybdenum precursor into the reaction chamber in vapor phase and providing a reactant into the reaction chamber in vapor phase. The molybdenum-containing material is selectively deposited on the silicon surface of the gap to at least partially fill the gap. The disclosure further relates to a semiconductor processing apparatus for filling a gap with a molybdenum-containing material.

The invention relates to a method for transferring a thin film (7) onto a final substrate (11), the thin film (7) and the final substrate (11) having different coefficients of thermal expansion. The method comprises transferring the thin film (7) onto an intermediate substrate (5) at a first adhesion interface (IA1) and forming a dielectric surface layer (10) on the exposed face of the thin film (7). The method also comprises activating the dielectric surface layer (10) by exposing it to a plasma having a radiofrequency power density strictly greater than 0.8 W / cm², then assembling the thin film (7) via the dielectric surface layer (10) to the final substrate (11), thus defining a second adhesion interface (IA2).Finally, the process includes mechanically stressing the final support (11) and / or the intermediate support (5) to detach the intermediate support (5) from the thin film (7) at the first adhesion interface (IA1). Figure to be published with the abbreviation: Fig. 4g.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

The provided method is for selectively depositing a silicon oxide film on a metal or metal-containing surface relative to a dielectric surface. The dielectric surface of the substrate can be selectively passivated relative to the metal or metal-containing surface, for example, by exposing the substrate to a silanizing agent. Subsequently, silicon oxide is selectively deposited on the metal or metal-containing surface relative to the passivated oxide surface by contacting the metal surface with a metal catalyst and a silicon precursor containing silanol.

This disclosure relates to a method for selectively filling gaps on a substrate with a molybdenum-containing material. In this method, the molybdenum-containing material is deposited into the gaps via a cyclic deposition process. The method includes providing a substrate into a reaction chamber, wherein the substrate includes at least one gap, and wherein the gap includes a silicon surface and a dielectric surface. The method further includes performing at least one deposition cycle. The deposition cycle includes providing a molybdenum precursor in the gas phase into the reaction chamber and providing reactants in the gas phase into the reaction chamber. The molybdenum-containing material is selectively deposited on the silicon surface of the gap to at least partially fill the gap. The invention further relates to a semiconductor processing apparatus for filling gaps using a molybdenum-containing material.