18781 results about "Engineering physics" patented technology

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

The invention provides a packaging structure and a packaging method. The package structure includes a substrate, a wafer disposed on the substrate and having a backside surface remote from the substrate, a heat sink disposed over the substrate and having a surface facing the backside surface, and a thermal interface material disposed between the wafer and the heat sink, wherein there is no organic adhesive between the wafer and the heat sink.

A semiconductor device includes a semiconductor layer having first and second principal surfaces, an insulated gate bipolar transistor (IGBT) region formed in the semiconductor layer, and a diode region formed adjacent to the IGBT region in a first direction. A plurality of gate trenches are arranged in the IGBT region and extend in a second direction intersecting the first direction. Each trench includes a gate conductive layer embedded through a gate insulating layer, and unit cells are defined between adjacent trenches. An emitter region is formed on the first principal surface of each unit cell. The emitter region of a unit cell located closer to the diode region has a smaller area than the emitter region of a unit cell located farther from the diode region.

The present disclosure relates to a display system (1, 1′) for hydrothermal sanitary components (10a-10d), comprising:at least a first device or module (1), comprising an exhibition panel (2) configured to lay, in use, at least partially on a plane substantially inclined with respect to a horizontal plane and destined and configured to support a plurality of hydrothermal sanitary components (10a-10d); andat least a retainer (2f, 4, 10p, 11) configured to realize a removable connection between the exhibition panel (2) and the hydrothermal sanitary components (10a-10d), the retainer (2f, 4, 10p, 11) being further destined and configured to allow a user to arrange, and repeatedly re-arrange multiple times, the hydrothermal sanitary components (10a-10d) on the exhibition panel (2) according to a plurality of user-defined and re-definable patterns or spatial configurations, simulating a real installation of said hydrothermal sanitary components (10a-10d) in an operating environment, such as a bathroom or similar.

According to one embodiment, a sensor includes a structure. The structure includes a first layer, a first film including a first film region, and a first intermediate layer including a first partial region. The first partial region is between the first layer and the first film region. A volume of the first layer is changeable depending on a detection target around the structure. The first film includes silicon and oxygen. The first intermediate layer includes at least one selected from the group consisting of Pd, Pt and Ti.

A hybrid antenna substrate of an embodiment comprises: a core part including a core layer and a core wiring layer laminated in the vertical direction; and an antenna part disposed on the core part, wherein: the antenna part comprises a plurality of antenna wiring layers successively laminated on the core part and antenna insulating layers disposed between the plurality of antenna wiring layers; and the core layer has a greater dielectric constant than the antenna insulating layers.

A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

The invention provides an LPDDR packaging method, which can effectively reduce the packaging thickness and can effectively improve the heat dissipation capability of a product. The method is characterized in that redistributed solder balls are led out from each stacked LPDDR chip through vertical routing, then the whole stacked assembly is turned over, and an EMI plating layer is plated on the periphery of a plastic package body of the stacked assembly.

Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.

Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.

The invention relates to the technical field of semiconductor equipment, and provides vertical epitaxy equipment and an epitaxy method. The apparatus comprises: a vertical reaction chamber; the wafer boat is used for vertically loading a plurality of wafers at intervals; the driving device is used for driving the boat to enter / exit the vertical reaction cavity; the material supply assembly comprises a process supply pipeline and a switching unit; the process material source comprises a cleaning material source for removing an oxide layer on the surface of the wafer and an epitaxial material source for executing an epitaxial process; the process monitoring device is used for monitoring process end points of the cleaning process and the epitaxial process; and the control device is in communication connection with the switching unit and the process monitoring device, and controls the switching unit to switch the supply of the material source according to the monitoring result of the process monitoring device. According to the vertical epitaxial equipment, the epitaxial process can be continuously executed without transferring the wafers after the oxide removal process of the plurality of wafers is executed in situ in the equipment, so that the output rate and the yield of the equipment are improved, the cost is reduced, and the fragment and pollution risks are reduced.

A semiconductor device includes a foundation layer and a transistor layer. The foundation layer is based on single-crystalline silicon carbide and includes a current propagation region of a first conductivity type and a non-depletable shielding structure of a second conductivity type. The transistor layer is based on epitaxially grown single-crystalline silicon carbide and includes a transistor cell (TC) configured to control a current through the current propagation region. The transistor layer is formed on the foundation layer after formation of the shielding structure in the foundation layer such that an epitaxial interface forms between the transistor foundation layer and the layer. The current propagation region extends from the epitaxial interface between neighboring partial regions of the shielding structure. Along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration changes by at least 1e17 1 / cm3 per 0.1 μm at the position of the pn junction.

A semiconductor package has a first semiconductor package which includes a first redistribution structure, a first semiconductor chip on a lower surface of the first redistribution structure, a first encapsulant on at least a portion of the first semiconductor chip, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant; and a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a second semiconductor chip on the third redistribution structure, and a second encapsulant on at least a portion of the second semiconductor chip, wherein the first encapsulant integrally covers each of a lower surface and a side surface of the first semiconductor chip.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

A semiconductor device may include a semiconductor substrate including a horizontal portion and a vertical portion protruding upward from the horizontal portion, a bit line on the semiconductor substrate and extending in a first direction parallel to a bottom surface of the semiconductor substrate, a word line on the bit line and extending in a second direction parallel to the bottom surface of the semiconductor substrate that is different from the first direction, a semiconductor pattern on the vertical portion of the semiconductor substrate and extending in a third direction perpendicular to the bottom surface of the semiconductor substrate, and a metal silicide pattern between the semiconductor pattern and the bit line. The semiconductor pattern may include a source / drain region adjacent to the bit line and a channel region on the source / drain region, and the metal silicide pattern may be in contact with the source / drain region and the bit line.

The invention belongs to the field of photovoltaic technology, and discloses a mountain photovoltaic array load analysis method considering a shielding effect, which comprises the following steps of: performing transient analysis (numerical method) on a photovoltaic array under the action of wind load, and then emphatically analyzing a first row of photovoltaic windward side and photovoltaic panels on the outermost periphery of the array; the pulsating pressure under the wind load is obtained, then whether the photovoltaic supports in the areas are intensified or not is evaluated and analyzed on the basis of the end, and the fatigue effect of the supports is mainly considered; and the other one is the influence of the shielding effect of the first row of photovoltaic panels on the back row of photovoltaic panels on the windward side of the array, so that the mountain photovoltaic array load can be accurately analyzed.

A semiconductor module includes a first semiconductor die, a second semiconductor die on the first semiconductor die, and a first corner die adjacent the second semiconductor die on the first semiconductor die and including a first corner die first side, a first corner die second side and a first corner die corner side connecting the first corner die first side and the first corner die second side, wherein the first corner die is located over a side of the first semiconductor die.

The invention provides a preparation method of a back contact solar cell. The preparation method comprises the following steps: equally cutting a diffused and etched cell into at least two fragments; performing surface texturing on the cut fragments; performing a passivation process on the back surface and the front surface of the fragment, and forming passivation layers on the back surface, the front surface and the cutting surface of the fragment in the passivation process; patterning the fragments on which the passivation layers are formed so as to define alternative P-type regions and N-type regions on the back surfaces of the fragments; and preparing metalized electrodes corresponding to the P-type region and the N-type region on the back surface of the fragment. The problems that in the prior art, the efficiency loss is large, the repairing cost is high, and the whole piece is scrapped due to local defects caused by battery piece cutting can be solved.

Embodiments of the present application provide an electronic device, a manufacturing method thereof and an electronic device, and relate to the technical field of semiconductors. The electronic device can be used for growing nanowires in a plane. The electronic device can include a substrate and at least one nanowire. The substrate has at least one groove. The nanowire is embedded in the groove. The groove has at least one groove wall. The nanowire extends along one groove wall of the groove and is in contact with the groove bottom. The groove wall has a guiding effect, so that the nanowire can grow in the plane of the groove bottom along the extension direction of the groove wall, which is conducive to large-scale manufacturing of the electronic device. The plane of the groove bottom can be parallel to the surface of the circuit board for carrying the electronic device. Therefore, when the nanowire grows in the plane of the groove bottom, it is conducive to large-scale integration of the electronic device on the circuit board.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

The invention provides a low-on-resistance shield gate trench MOSFET fault diagnosis method and system, and relates to the technical field of MOSFET fault diagnosis, and the method comprises the steps: applying preset transient electrical excitation to a contact interface of a probe and a wafer bonding pad and an MOSFET before the steady-state on resistance of the MOSFET is measured; according to the obtained electrical response information of the contact interface and the MOSFET under each transient electrical excitation effect, constructing a transient feature vector; analyzing the transient feature vector according to a preset discrimination rule for contact part abnormity and a discrimination rule for device structure defects to determine whether an abnormity source is the contact part abnormity or the device structure defects; according to the determined abnormal source, the measured on-resistance value is adjusted, and the problem that the test system misjudges that the on-resistance of the device is abnormally increased due to instantaneous fluctuation of the contact resistance caused by the change of the microscopic geometrical shape of the tip of the probe is solved.

An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of the electronic device includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a through hole penetrating the substrate, a side wall of the through hole connected with the first surface and the second surface; providing a first conductive layer on the substrate, the first conductive layer extending into the through hole; providing a second conductive layer on the first conductive layer, the second conductive layer extending into the through hole and having an original thickness; performing a thinning step to remove at least a portion of the second conductive layer; and performing an inspection step to obtain a first inspection result, and determining whether to continue subsequent steps according to the first inspection result.

A wafer-level assembly of chiplets comprising a plurality of groups of chiplets including a first group of chiplets and a second group of chiplets, wherein the first group of chiplets is organized as a first fully-connected configuration, wherein the second group of chiplets is organized as a second fully-connected configuration. The wafer-level assembly of chiplets further comprises a plurality of interconnects including a first interconnect and a second interconnect, wherein the first interconnect couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second interconnect couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, and wherein the plurality of interconnects is arranged in a mesh configuration.

The present invention relates to an electrical connector comprising a first metal layer and a second metal layer, wherein the electrical connector comprises: a plurality of beam portions consisting of the first metal layer, wherein the second metal layer is not provided between the first metal layers in the thickness direction such that the first metal layers are spaced apart from each other in the thickness direction and elastically deformed by an external force applied in the length direction; and a connecting portion in which the first metal layer and the second metal layer are stacked in the thickness direction and which connects the plurality of beam portions, thereby providing an electrical connector with an increased surface area and improved current carrying capacity (CCC).

In one example, a semiconductor device includes a first semiconductor, a second semiconductor, and a third semiconductor that are stacked in a vertical direction. The second semiconductor is disposed between the first semiconductor and the third semiconductor and includes a conversion circuit that converts an electrical characteristic or a physical characteristic. The technology can be applied to, for example, solid-state imaging devices or the like.

Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.