31087 results about "Engineering physics" patented technology

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

A method for surface defect inspection can comprise obtaining topographical data from one or more portions of a semiconductor element. The semiconductor element can have a surface comprising a dielectric and a plurality of metal pads. The method can further comprise processing the topographical data of the one or more portions of the semiconductor element to determine at least a first property of the plurality of metal pads, computing at least one variability value for the first property, and identifying candidate defects in the one or more portions of the semiconductor element based at least in part on the at least one variability value.

Provided is an energy storage container. The energy storage container comprises a container body (1); in three directions, i.e., a first direction, a second direction, and an up-down direction, the sizes of the container body (1) in two directions among the three directions are the same as the size of a standard container having a preset size, and the size of the container body (1) in the remaining direction is smaller than the size of the standard container having the preset size, wherein the preset size is 10 chi, 20 chi, 30 chi, 40 chi or 45 chi, and the first direction, the second direction, and the up-down direction are perpendicular to each other. Under the condition that the size of the container body (1) is not greatly changed, the weight of the container body (1) can be reduced, and the energy storage container can be matched with conventional transportation apparatuses, thereby satisfying the transportation requirements of land transportation and / or ocean shipping, etc.

The invention provides a back contact battery and a photovoltaic module, and relates to the field of photovoltaic technology. The back contact battery provided by the invention comprises a battery body, a plurality of first fine grids and a plurality of second fine grids, wherein the first fine grids and the second fine grids extend along a first direction; the plurality of first fine grids and the plurality of second fine grids are sequentially and alternately arranged on the first surface of the battery body at intervals in the second direction; the first surface comprises a first area and comprises a first edge and a second edge which are oppositely arranged in the second direction; in the first region, the first fine grid and the second fine grid are provided with a plurality of first sub-bonding pads and a plurality of second sub-bonding pads; the area of the first sub-pad is smaller than that of the second sub-pad. According to the back contact battery provided by the invention, the stability of the welding strip in the welding process can be improved, and the current collection reliability is ensured.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

A job-site tool in one aspect of the present disclosure includes: a display; a flexible printed circuit; and a control circuit. The display is visible tool from outside and includes at least one surface light emitter. The flexible printed circuit includes conductive traces. The at least one surface light emitter is on the flexible printed circuit and is electrically connected to the conductive traces. The control circuit is electrically connected to the display via the conductive traces.

An IC stack includes: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures. The thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.

A semiconductor device includes semiconductor elements and conductors. The conductors include a first upper conductor connected to an upper electrode of the first semiconductor element through a first upper solder, a first lower conductor connected to a lower electrode of the first semiconductor element through a first lower solder, a second upper conductor connected to an upper electrode of the second semiconductor element through a second upper solder, a second lower conductor connected to a lower electrode of the second semiconductor element through a second lower solder, and a joint conductor connecting the first upper conductor and the second lower conductor through a relay solder. Each solder contains Cu and Sn. Each solder connection target has an Ni layer. A grain size of at least one of the first upper solder, second upper solder, or relay solder is smaller than a grain size of the first and second lower solders.

In one instance, a dynamic slab gate valve is disclosed for use in controlling fluid flow through pipelines and other tubulars, wherein the dynamic slab gate valve has a dynamic seat assembly and a dynamic skirt assembly. The dynamic seat assembly is urged toward a gate of the dynamic slab gate valve by an energizer to maintain a seal between a seat and the gate. The dynamic skirt assembly is urged toward the gate of the dynamic slab gate valve by an energizer to maintain a seal with the gate. Improved seals are provided. Other valves are disclosed herein.

An electronic device has a substrate, a signal wiring and a heat radiating wiring. The substrate has one surface and the other surface opposite to the one surface. The signal wiring is formed on an insulating layer of the substrate. The heat radiating wiring is formed on the insulating layer and thermally connected to the signal wiring on a same plane as the signal wiring.

The present disclosure relates generally to an arthropod trapping device, more particularly, to a compact and portable trapping device comprising a housing and an insert, where the insert is also attachable to or insertable into a handheld trapping implement.

The invention relates to the technical field of semiconductors, and discloses a glass-based three-dimensional interconnection structure and a packaging framework based on the glass-based three-dimensional interconnection structure, the glass-based three-dimensional interconnection structure comprises a glass plate core, two opposite sides of the glass plate core are respectively a first surface and a second surface; the front rewiring layer is arranged on the first surface; the back rewiring layer is arranged on the second surface; the glass through hole penetrates through the glass plate core, and a base metal interconnection layer is filled in the glass through hole; the base metal interconnection layer extends to the first surface and is electrically connected with the front rewiring layer; and the base metal interconnection layer extends to the second surface and is electrically connected with the back rewiring layer. According to the technical scheme provided by the invention, the technical effects of vertical integration capability, thermal management efficiency, electromagnetic performance and the like can be remarkably improved in a high-frequency and high-integration scene.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

A wearable electronic device can include a sidewall housing defining an internal volume and a band slot configured to receive a securement band. The sidewall housing can include a radio-frequency (RF)-transparent window defining the band slot, a rear cover coupled to the sidewall housing with the rear cover including metal, an antenna resonator disposed in the internal volume adjacent the RF-transparent window, and a conductor electrically coupling the rear cover to the antenna resonator.

A universal ring wafer support apparatus that includes at least one raised support to securely support different size wafers above and separated from the main body to enable dust, particles and contaminants to flow away from a wafer and through the main body to a back side thereof. The universal ring wafer support apparatus and the at least one raised support is formed of a highly conductive material while a top surface of the at least one raised support includes contact material(s) or pucks having a high gripping force to grip and securely support a wafer thereon.

The invention relates to the technical field of diodes, and particularly discloses a high-temperature superconducting diode structure model which is used for solving the problems that an integrated circuit is high in power consumption and low in speed, and a traditional semiconductor technology is difficult to meet requirements. The semiconductor diode has the problems of power consumption and time delay, the research of the existing superconducting diode mostly focuses on low-temperature superconducting, low working temperature hinders the application and contradicts with the original intention of low power consumption, and the high-temperature superconducting diode which can work in a liquid nitrogen environment is urgently needed, including geometric, material and physical models. The geometric model is provided with a substrate with a superconductive microbridge strip with an asymmetric structure and metal films at two ends, the physical model contains an external magnetic field and current, and electromagnetic transport characteristics are analyzed through simulation modeling; through geometric structure and material selection and physical model setting, electromagnetic transport characteristics are analyzed by using the corrected RCSJ model, the geometric structure of the superconducting micro-bridge strip is optimized, and the problems of power consumption and speed of an integrated circuit are solved.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention relates to the technical field of electronic information materials, in particular to a metal foil with a carrier, a metal-clad laminated board and a circuit board. The invention discloses a metal foil with a carrier, a metal-clad laminated board and a circuit board, the metal foil with the carrier is characterized in that the metal foil with the carrier comprises a carrier layer and a functional layer, the functional layer is arranged on one side face of the carrier layer, and the functional layer is arranged on the other side face of the carrier layer. And the ratio of the thermal expansion coefficient a of the functional layer to the thermal expansion coefficient b of the carrier layer satisfies 40% < = a / b < = 120%. The thermal expansion coefficient ratio of the carrier layer to the functional layer of the metal foil with the carrier is in a proper range, so that the stripping stability of the metal foil with the carrier during use can be improved, and the processing efficiency is improved.

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.

A doorbell device includes a housing, an optical module, a circuit board, and a button assembly disposed in an opening of the housing. The optical module is disposed in the housing and is controllable to power up to photograph an environmental image and outputs an image signal; the circuit board is disposed in the housing and has several electronic components, a thermally conductive circuit, and a sensing switch on an outer surface of the circuit board; the electronic components includes an auxiliary function component and a primary function component electrically connected to the sensing switch, the optical module, and the auxiliary function component; the thermally conductive circuit is laid out on the outer surface, is electrically connected to the electronic components, and has an extending segment located in a sensing area of the circuit board; a pressing board corresponds to the sensing area and the sensing switch.

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

A plurality of systems of protection circuits are supported without changing a layout in a switching element. A semiconductor device includes a main switching element including a MOSFET and a sense switching element having a smaller area in plan view than the main switching element and for detecting current flowing through the main switching element. A first gate terminal that is a gate terminal of the sense switching element is arranged between a second gate terminal that is a gate terminal of the main switching element and a source terminal of the sense switching element.

This is directed to an electronic device enclosure. The enclosure includes an outer periphery member forming an outer surface of a device, and to which an internal platform is connected. Electronic device components can be assembled to one or both surfaces of the internal platform. The enclosure can include front and back cover assemblies assembled to the opposite surfaces of the outer periphery member to retain electronic device components. One or both of the cover assemblies can include a window through which display circuitry can provide content to a user of the device.

A protective case and mounting system for a handheld electronic device is provided. The protective case can include a removable mounting system comprised of an interlocking member and a plurality of mounting bases. The protective case may further include a non-slip member to prevent the device from slipping on a surface and a magnet for attaching the device to a magnetic surface.

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

Smart glasses and an electronic device are provided. The smart glasses include a glasses frame, a glasses temple, and an electronic component. The glasses frame is connected to the glasses temple, and the electronic component is disposed in the glasses temple. The glasses temple may include a bending adjustment portion, and the bending adjustment portion includes a flexible housing and a flexible metal member. The flexible housing is of a low-pressure integrated structure and is provided with a hollow accommodation cavity. The flexible metal member is embedded in the accommodation cavity. The bending adjustment portion in the smart glasses is bendable.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

Semiconductor structures including stacked transistors are provided. The semiconductor structures can include a pair of stacked forksheet transistors that have a shared second (top) gate electrode, or the structures can include a pair of stacked forksheet transistors that have non-shared second (top) gate electrodes. In either of these embodiments, the second (top) gate electrode is separated from a first (bottom) gate electrode by a frontside gate cut structure.