621 results about "Metal interconnect" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers having formed therein interposer metal interconnect structures, A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers having formed therein router metal interconnect structures and a router substrate having formed therein router through-substrate via structures therein. A backside of the router substrate may be thinned to expose end surfaces of the router through-substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. Bonding pads of the memory dies are electrically connected to the router through-substrate via structures.

The invention discloses a semiconductor chip, a preparation method of a metal interconnection layer and the metal interconnection layer. The semiconductor chip comprises a semiconductor substrate, and a plurality of device structures are formed on the semiconductor substrate; the metal interconnection layer is located above the semiconductor substrate and used for connecting a plurality of device structures, and the metal interconnection layer at least comprises a first titanium layer located above the semiconductor substrate, a second titanium layer located above the semiconductor substrate and a third titanium layer located above the semiconductor substrate; a first titanium nitride layer over the first titanium layer; a metal layer over the first titanium nitride layer; the at least two groups of composite barrier layers are positioned above the metal layer; each group of composite barrier layers comprises a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each group of composite barrier layers is smaller than a first preset thickness; and the sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than a second preset thickness. According to the semiconductor chip, the metal residue defect on the surface of the semiconductor substrate is reduced while the thickness requirement is met.

The invention relates to a preparation method of a surface acoustic wave filter integrated with a CMOS (Complementary Metal Oxide Semiconductor) process, which comprises the following steps of: preparing a CMOS radio-frequency signal processing circuit by using a silicon or silicon carbide substrate, combining a dielectric buffer layer with a piezoelectric material, and then depositing a metal interdigital structure on the surface of the piezoelectric material to prepare the surface acoustic wave filter. A passivation layer is deposited on the surface of the filter to protect the filter structure, finally a metal interconnection line and the passivation layer are prepared above the filter, and in order to not affect the performance of the filter, an air cavity is prepared between the passivation layer and the metal interconnection layer of the filter, so that the passivation layer and the metal interconnection layer are effectively isolated. According to the preparation method, the surface acoustic wave filter and the CMOS radio frequency circuit can be integrated, the problem that radio frequency front-end and rear-end signal processing cannot be integrated at the same time at present is solved, and the preparation method plays an important role in promoting development of a radio frequency chip in the directions of high integration, low cost, miniaturization and the like; and the radio frequency chip has wide practical value and economic value in the radio frequency chip application field.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed. A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers in which router metal interconnect structures are formed and a router substrate in which router substrate via structures are formed. A backside of the router substrate may be thinned to expose end surfaces of the router substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. The bonding pads of the memory dies are electrically connected to the router substrate via structures.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Interposer substrate with integrated step die cavity, and related integrated circuit (IC) packages and related fabrication methods. A die cavity integrated in an outer layer(s) of the interposer substrate provides room for a die to extend into the interposer substrate (e.g., to facilitate increased die height). Forming the die cavity in the outer layer(s) facilitates metal interconnects in an outer metallization layer of the interposer substrate being located adjacent to the die cavity can also enhance heat dissipation for the die extending into the die cavity. Forming the die cavity in the outer layer(s) of the interposer substrate also facilitates reduced distance between the interposer substrate and package substrate to facilitate reduced height vertical interconnects coupling the interposer substrate to the package substrate. This facilitates vertical interconnects with reduced aspect ratio and reduced pitch that can support dies with higher input / output (I / O) connection density.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

An electronic device having a substrate employing reduced area, added metal pad(s) to a metal interconnect(s) to reduce air voids in a solder joint and related fabrication methods are disclosed. The electronic device includes a die that has die interconnects coupled to a first metal pad(s) of a respective metal interconnect(s) of a metallization layer of the substrate through a second, additional metal pad(s). To facilitate a reduction in air voids in the solder joint between the die and the first metal pad(s) and consequently the amount of solder between the first metal pad and the die, the second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is above and adjacent to the first metal pad(s). A solder joint(s) is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate.

The invention relates to the technical field of semiconductors, and discloses an electro-optical modulator and a preparation method thereof, and the preparation method comprises the steps: forming a waveguide core and a plurality of electrodes on a part of the surface of one side, opposite to a first substrate, of a first cladding, and dividing the waveguide core into an internal waveguide core and an external waveguide core; at least part of the electrode further goes deep into the first cladding of partial thickness; forming a second wrapping layer wrapping the electrode and the waveguide core on the surface of the first wrapping layer; forming a plurality of metal interconnection lines on the surface of the second cladding, wherein each metal interconnection line also penetrates through the second cladding and is connected with one electrode; forming a bonding groove penetrating into the partial thickness of the second cladding; forming an electro-optical thin film layer comprising an equal-thickness region and a thickness gradient region in the bonding groove; the projection of the equal-thickness area completely covers the internal waveguide core, and the projection of the thickness gradient area at least covers part of the external waveguide core. The CMOS technology compatibility of the device can be improved, the insertion loss of the device is reduced, and the integration level and the space utilization rate of an optical chip are improved.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Aspects disclosed include an integrated circuit (IC) package comprising a substrate and a solder joint coupled to a corner interconnect structure of the substrate to improve the reliability of the package. Related apparatus and methods are also disclosed. The substrate includes the corner interconnect structure in a corner of the substrate. The corner interconnect structure includes a first metal interconnect adjacent to the corner of the substrate and a plurality of second metal interconnects adjacent to the first metal interconnect. The IC package includes a solder joint coupled to at least two of the metal interconnects in the corner interconnect structure improving the mechanical reliability of the IC package. In so doing, a plurality of third metal interconnects adjacent to the corner interconnect structure may be utilized for input / output (I / O) communication paths increasing the input / output of the IC package without growing the size of the package.

The invention relates to the technical field of hybrid bonding, in particular to a laser-assisted hybrid bonding interconnection method, which comprises the following steps of: S1, processing the surface of a wafer to enable the to-be-bonded surface of the wafer to be flat; s2, cleaning a to-be-bonded surface of the wafer, and removing organic pollutants and an oxide layer; s3, aligning and fitting the surfaces to be bonded of the two wafers; s4, enabling the to-be-bonded surfaces to comprise dielectric layers and metal interconnection points, irradiating the dielectric layers with infrared laser, and carrying out the interconnection of the dielectric layers of the two to-be-bonded surfaces; and S5, the metal interconnection points are heated by blue laser, and the metal interconnection points of the two surfaces to be bonded are interconnected. In the hybrid bonding stage, the infrared laser and the blue laser are used for bonding the dielectric layer and the metal interconnection point respectively, partitioned irradiation and differentiated heating of the metal interconnection point and the dielectric layer are achieved, the problems of interface warping, microcracks and other thermal damage are effectively avoided, and the interconnection quality and the packaging reliability are improved.

A preparation method of an SOFC or SOEC with a long-life sealing interface is formed by allowing a sealing layer, a cell and a metal interconnector to be mutually contacted. In the present disclosure, with spinel as a coating material of the metal interconnector, staged thermal treatment is employed to form a high-density and strong-adhesion spinel coating to improve the endurance and entire performance of the metal interconnector. The present disclosure also optimizes the material system of the sealing layer, namely, uses the SiO2—MgO—Al2O3—SrO—V2O5 system to prepare the sealing layer, which not only improves the resistivity of the sealing layer but also increases its hardness and fracture strength. Further, under the condition of ensuring the airtightness, the coefficient of thermal expansion of the sealing layer is matched with the coefficients of thermal expansion of the metal interconnector and the cell, improving the endurance of the sealing interface.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention relates to the technical field of semiconductors, in particular to a device based on an advanced technological process and a preparation method thereof, and the method comprises the steps: providing an initial device structure which comprises a substrate and at least one interconnection layer located on the substrate, and forming a functional element of a semiconductor device in the substrate, the at least one interconnection layer is located between the top metal layer and the substrate, and the interconnection layer is prepared based on an advanced technological process and comprises a metal layer, a metal interconnection structure and a dielectric layer; forming a deep groove in the initial device structure, wherein the deep groove penetrates through the at least one interconnection layer and then goes deep into the substrate; and performing isolation material filling on the deep trench to form a filling material layer which fills the deep trench and is laminated on the at least one interconnection layer, and reusing an area, laminated on the at least one interconnection layer, of the filling material layer by a next interconnection layer adjacent to the at least one interconnection layer. According to the invention, the preparation process of the DTI can be integrated into the preparation process of the interconnection layer of devices such as the BCD, and the integration process is simplified.

The invention provides an optical proximity correction method, electronic equipment and a storage medium, and the method comprises the steps: carrying out the initial correction processing of an initial mask layout, obtaining a corrected mask layout, determining a first mask pattern and a second mask pattern, which violate a standard mask rule, in the corrected mask patterns, and determining the rollback distance of the first mask pattern and the second mask pattern according to the violation information, the first contact hole, the first through hole, the second contact hole and the second through hole and the violation information between the first mask pattern and the second mask pattern, and moving the first mask pattern and the second mask pattern based on the rollback distance to obtain a target mask layout. By considering the distance between the mask pattern through hole and the contact hole, the coverage rate and the electrical property of the metal interconnection layer to the contact hole and the through hole are ensured.

The invention discloses a GaN HEMT / MOSFET monolithic integrated cascade device and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a GaN HEMT device and a GaN MOSFET device, wherein the GaN HEMT device and the GaN MOSFET device are electrically connected through a metal interconnection structure; the GaN MOSFET device is prepared above the vertical structure of the GaN HEMT device, and the projection position of the GaN MOSFET device is located between the grid electrode and the drain electrode of the GaN HEMT device; isolation grooves are arranged among different GaN HEMT / MOSFET cascade devices distributed along the transverse direction of the substrate, and electrical isolation among the different cascade devices is realized through the isolation grooves. The interface defect is reduced through one-time epitaxial growth, the chip area is reduced through vertical integration, the voltage resistance and high-frequency performance of the device are improved, and the device is suitable for the field of efficient power conversion.

A packaged integrated circuit (IC) including a semiconductor die having a metallization layer, the metallization layer including first metal interconnects in a first insulation material. The IC includes a first substrate on the metallization layer, the first substrate including second metal interconnects in a second insulation material different from the first insulation material, at least one of the second metal interconnects being electrically coupled to at least one of the first metal interconnects. The IC further includes a second substrate on the first substrate, the second substrate including an isolation circuit and third metal interconnects in a third insulation material different from the first insulation material, the isolation circuit being electrically coupled to the at least one of the first metal interconnects via the at least one of the second metal interconnects and at least one of the third metal interconnects.

The invention belongs to the technical field of surface engineering, and relates to a preparation method of a protective coating for a metal connector of a solid oxide battery. A compact transition metal oxide inner layer is deposited on a metal substrate in a reactive sputtering mode, then a transition metal alloy outer layer is deposited in a metal sputtering mode, a transition metal oxide / transition metal alloy composite coating is formed, and a spinel protective layer is formed after annealing treatment. According to the method, a transition metal oxide inner layer is used as a diffusion barrier layer, diffusion of elements such as Cr from a substrate to a coating and diffusion of oxygen to the substrate in the high-temperature annealing and long-term service process are effectively inhibited, and therefore the thickness of a reaction layer and the thickness of a thermal growth oxide layer are remarkably reduced. The composite coating is compact in structure, stable in component, good in matching with the thermal expansion coefficient of the substrate, excellent in oxidation resistance and low in surface specific resistance, and capable of effectively improving the long-term operation stability and prolonging the service life of the SOC connector.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

The invention relates to the technical field of semiconductors, in particular to a semiconductor device structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor structure which comprises a device substrate and a metal interconnection layer located on the device substrate, and the device substrate is provided with a functional element of a semiconductor device; forming a deep groove in the semiconductor structure, wherein the deep groove penetrates through the metal interconnection layer and then extends into the device substrate; and depositing an isolation material to form an isolation material layer which is laminated on the metal interconnection layer and is filled with the deep trench, forming a deep trench isolation structure in the region, filled with the deep trench, in the isolation material layer, and forming a passivation opening layer in the region, laminated on the metal interconnection layer, in the isolation material layer. According to the invention, the deep trench etching is carried out after the preparation process of the metal interconnection layer is completed, so that the DTI process is integrated into the back-end process of a BCD device and the like, and the device damage risk and the preparation cost caused by DTI integration are reduced.

The present invention discloses an automated ESD protection device layout design and layout-driven simulation method. A parameterized ESD protection device unit layout is compiled using the Skill Script language based on device characteristics. The device layout is used as a photolithography mask to define the device geometry. The three-dimensional device is simulated in combination with process parameters prepared using a semiconductor process to complete device extraction for the front-end process (FEoL). The metal layer wiring of the back-end of line (BEoL) is extracted into a capacitance model or capacitance matrix using a wiring capacitance parameter extraction method. After the preparatory work is completed, the device layer and metal interconnect layer models are simulated using a Mix-Mode simulation method to further guide the design of an ESD protection device with excellent performance. The method of the present invention allows for automated design of ESD protection devices, and accurate extraction and simulation of models, significantly reducing the complexity of design optimization in the development of ESD protection devices and significantly shortening the development cycle.

The application discloses a semiconductor device and a curve processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by a plurality of boundary lines with different directions and connected by transition lines; the transition line between two adjacent boundary lines is a curve determined according to the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. The end points of the related lines forming the metal interconnection layer are taken as processing objects, and the transition lines are used for transition at the positions where the related lines change direction, so that the overall coverage adjustment of each angle is realized, the inradius of all concave corner positions is increased as much as possible, the stress distribution concentration effect at each concave corner is weakened, the crack formation is avoided, the metal electromigration, the connected lines or the broken lines and other phenomena are eliminated, the product quality is obviously improved, and the chip life is prolonged.