1046 results about "Metal interconnect" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A semiconductor integrated-circuit (IC) chip includes: a first transistor, a second transistor at a same horizontal level as the first transistor, a first oxide layer at the same horizontal level as the first and second transistors, horizontally around the first and second transistors and having a portion horizontally between the first and second transistors; a frontside interconnection scheme under the first and second transistors and first oxide layer, a backside interconnection scheme over the first and second transistor and first oxide layer, and a metal interconnect vertically in the portion of the first oxide layer and coupling the frontside interconnection scheme to the backside interconnection scheme.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die / bump connections to the package substrate.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The utility model discloses a semiconductor device. The semiconductor device comprises a first wire, a first insulating layer, a second wire and a metal interconnection structure, the first wire is arranged in a first dielectric layer, the first insulating layer is arranged on the first dielectric layer and covers the first wire, the second wire is arranged in a second dielectric layer and partially overlaps the first wire, and the metal interconnection structure is arranged on the second dielectric layer. A metal interconnect structure is disposed within the second dielectric layer and the first insulating layer and physically contacts a top surface of the first conductive line, a top surface of the second conductive line, and a sidewall on one side of the second conductive line. Therefore, by means of the arrangement of the metal interconnection structure, the efficiency and the reliability of the wiring structure are improved on the premise that the space is saved, and the semiconductor device achieves more optimized operation performance.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers having formed therein interposer metal interconnect structures, A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers having formed therein router metal interconnect structures and a router substrate having formed therein router through-substrate via structures therein. A backside of the router substrate may be thinned to expose end surfaces of the router through-substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. Bonding pads of the memory dies are electrically connected to the router through-substrate via structures.

According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

The invention discloses a semiconductor chip, a preparation method of a metal interconnection layer and the metal interconnection layer. The semiconductor chip comprises a semiconductor substrate, and a plurality of device structures are formed on the semiconductor substrate; the metal interconnection layer is located above the semiconductor substrate and used for connecting a plurality of device structures, and the metal interconnection layer at least comprises a first titanium layer located above the semiconductor substrate, a second titanium layer located above the semiconductor substrate and a third titanium layer located above the semiconductor substrate; a first titanium nitride layer over the first titanium layer; a metal layer over the first titanium nitride layer; the at least two groups of composite barrier layers are positioned above the metal layer; each group of composite barrier layers comprises a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each group of composite barrier layers is smaller than a first preset thickness; and the sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than a second preset thickness. According to the semiconductor chip, the metal residue defect on the surface of the semiconductor substrate is reduced while the thickness requirement is met.

The invention belongs to the technical field of semiconductor processing, and particularly relates to a method for improving 3D wafer stacking electric leakage and a semiconductor structure. A wafer is provided, the wafer comprises a substrate layer and an oxide layer, one side of the oxide layer is a bonding surface, and one side of the substrate layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, a through hole is formed in the oxide layer from the bonding surface side, and the through hole is communicated with the metal interconnection structure and is filled with a conductor layer; the bonding surfaces of one wafer and the other wafer are opposite, and the conductor layers of the two wafers are communicated; a TSV through hole is formed in the bottom face of any wafer in the direction of the metal interconnection structure, and the TSV through hole is communicated with the metal interconnection structure; depositing an oxidation deposition layer in the TSV through hole, wherein the oxidation deposition layer at least covers the side wall of the TSV through hole; and depositing a TSV through hole conductor layer in the TSV through hole, wherein the TSV through hole conductor layer is communicated with the metal interconnection structure. Through a simple process, the problem of electric leakage of the TSV is solved, and the reliability of the semiconductor device can be improved.

The invention relates to a preparation method of a surface acoustic wave filter integrated with a CMOS (Complementary Metal Oxide Semiconductor) process, which comprises the following steps of: preparing a CMOS radio-frequency signal processing circuit by using a silicon or silicon carbide substrate, combining a dielectric buffer layer with a piezoelectric material, and then depositing a metal interdigital structure on the surface of the piezoelectric material to prepare the surface acoustic wave filter. A passivation layer is deposited on the surface of the filter to protect the filter structure, finally a metal interconnection line and the passivation layer are prepared above the filter, and in order to not affect the performance of the filter, an air cavity is prepared between the passivation layer and the metal interconnection layer of the filter, so that the passivation layer and the metal interconnection layer are effectively isolated. According to the preparation method, the surface acoustic wave filter and the CMOS radio frequency circuit can be integrated, the problem that radio frequency front-end and rear-end signal processing cannot be integrated at the same time at present is solved, and the preparation method plays an important role in promoting development of a radio frequency chip in the directions of high integration, low cost, miniaturization and the like; and the radio frequency chip has wide practical value and economic value in the radio frequency chip application field.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

A semiconductor package includes a substrate, a semiconductor die, metal interconnects, the semiconductor die being mounted to the substrate via the metal interconnects, an inductor mounted to the substrate, a magnetic material encapsulating the semiconductor die, the inductor, and the metal interconnects, the magnetic material including metal particles suspended in a first insulation material, and a second insulation material covering the magnetic material, wherein the second insulation material is substantially free of metal particles.

Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (“die”) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

Hybrid package substrates employing film metallization layers with outer pre-impregnated (PPG) region(s) to support high density bump and wire bond connections for respective bump and wire bond connected dies in the IC package, and related hybrid integrated circuit (IC) packages and fabrication methods are disclosed. The package substrate includes film metallization layers of a softer, flexible material that can more easily be patterned to support formation of high density, reduced pitch metal interconnects to support finer bump pitch connections to a bottom, first die(s) in a die region of the package substrate. The package substrate also includes one or more PPG regions a PPG metallization layer(s) adjacent to the die region of the package substrate that reinforces the film metallization layers and also supports the formation of wire bond pads for wire bond connections to an upper, second die(s) in the hybrid IC package.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

A device structure includes: an interposer including interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads; at least one semiconductor die having formed therein in-die bonding pads that are bonded to a respective one of the die-side interposer bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die. The composite die frame includes a molding compound die frame portion including a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and including a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed. A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers in which router metal interconnect structures are formed and a router substrate in which router substrate via structures are formed. A backside of the router substrate may be thinned to expose end surfaces of the router substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. The bonding pads of the memory dies are electrically connected to the router substrate via structures.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

This application provides a test structure and a method for calibrating gate parasitic capacitance. A first test structure can calibrate a dimension and thickness table related to a first metal layer in an ITF file. A second test structure is formed by an MOS structure after removing contact holes in source / drain regions, and this structure is used for calibrating gate dimension and thickness values in the ITF file. A third test structure is formed by the MOS structure after removing metal interconnect lines in source / drain regions, removing shallow doped source / drain regions composed of first conductive type lightly-doped regions, and this structure is used for calibrating tables related to capacitance Cco and Cf in the ITF file. A fourth test structure is an MOS structure, and its actual capacitance test result is compared with a simulation result to ensure that the gate parasitic capacitance conforms to the model simulation.

A semiconductor package includes a substrate having a top surface and a bottom surface, and a vertical sidewall extending between the top surface and the bottom surface; an integrated circuit die mounted within a device region on the top surface of the substrate; a metal interconnect structure embedded within the device region of the substrate, wherein the integrated circuit die is electrically connected to the metal interconnect structure; and a peripheral shielding ring embedded within a peripheral region of the substrate. The peripheral region surrounds the device region. A lid is mounted on the top surface of the substrate. The lid is electrically connected with the peripheral shielding ring.

A method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.

A flip-chip bonded photonic device and methods of fabrication are described. The device has a spot size converter and an antireflective coating on a sidewall of the spot size converter. The device has a semiconductor layer comprising a stack of quantum wells and an etch stop semiconductor layer beneath the layer comprising a stack of quantum wells. The device has a vertical sidewall for optical coupling and a sloped sidewall for metal interconnects. The device has a substrate and an optical waveguide residing above substrate. A mirror is coupled to the optical waveguide that bends light from the optical waveguide and transmits the light through the substrate. The light expands as it passes through the substrate. A collimating lens receives the light transmitted through the substrate and is lithographically aligned with the mirror. An optical engine has a flip-chip integrated electro-absorption modulated laser (EML) on a substrate.

Flexible under-bump metallization sizes and patterning, and related integrated circuit packages and fabrication methods are disclosed. First under-bump metallizations (UBMs) of a first, larger size and pitch are provided in the die and coupled to corresponding metal interconnects in the package substrate. One or more second UBMs of a second, reduced size UBMs can also be located in the core area of the die. This provides greater flexibility in the design and layout of the die, because different circuits within the die (e.g., I / O related circuits) may only require coupling to smaller size UBMs for performance requirements and thus can be more flexibility located in the die. Also, to further reduce pitch of the second, smaller size UBMs, one or more of the second, smaller size UBMs can be formed as oblong-shaped UBMs, which can still maintain a minimum separation based on metal interconnect pitch limitations in the package substrate.

The invention provides a preparation method and device of a semiconductor metal interconnection structure and electronic equipment, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: carrying out the photoetching of a preset semiconductor device, forming a metal interconnection substrate, and forming a groove in the surface of the metal interconnection substrate; and depositing metal tungsten and metal aluminum on the surface of the metal interconnection substrate in sequence to obtain the target semiconductor metal interconnection structure. The groove is filled by using the metal tungsten and the metal aluminum in a combined manner, so that the semiconductor device is prevented from being damaged while the filling performance is improved.