414 results about "Metal interconnect" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention discloses a semiconductor chip, a preparation method of a metal interconnection layer and the metal interconnection layer. The semiconductor chip comprises a semiconductor substrate, and a plurality of device structures are formed on the semiconductor substrate; the metal interconnection layer is located above the semiconductor substrate and used for connecting a plurality of device structures, and the metal interconnection layer at least comprises a first titanium layer located above the semiconductor substrate, a second titanium layer located above the semiconductor substrate and a third titanium layer located above the semiconductor substrate; a first titanium nitride layer over the first titanium layer; a metal layer over the first titanium nitride layer; the at least two groups of composite barrier layers are positioned above the metal layer; each group of composite barrier layers comprises a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each group of composite barrier layers is smaller than a first preset thickness; and the sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than a second preset thickness. According to the semiconductor chip, the metal residue defect on the surface of the semiconductor substrate is reduced while the thickness requirement is met.

An electronic device having a substrate employing reduced area, added metal pad(s) to a metal interconnect(s) to reduce air voids in a solder joint and related fabrication methods are disclosed. The electronic device includes a die that has die interconnects coupled to a first metal pad(s) of a respective metal interconnect(s) of a metallization layer of the substrate through a second, additional metal pad(s). To facilitate a reduction in air voids in the solder joint between the die and the first metal pad(s) and consequently the amount of solder between the first metal pad and the die, the second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is above and adjacent to the first metal pad(s). A solder joint(s) is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate.

Aspects disclosed include an integrated circuit (IC) package comprising a substrate and a solder joint coupled to a corner interconnect structure of the substrate to improve the reliability of the package. Related apparatus and methods are also disclosed. The substrate includes the corner interconnect structure in a corner of the substrate. The corner interconnect structure includes a first metal interconnect adjacent to the corner of the substrate and a plurality of second metal interconnects adjacent to the first metal interconnect. The IC package includes a solder joint coupled to at least two of the metal interconnects in the corner interconnect structure improving the mechanical reliability of the IC package. In so doing, a plurality of third metal interconnects adjacent to the corner interconnect structure may be utilized for input / output (I / O) communication paths increasing the input / output of the IC package without growing the size of the package.

The invention relates to the technical field of hybrid bonding, in particular to a laser-assisted hybrid bonding interconnection method, which comprises the following steps of: S1, processing the surface of a wafer to enable the to-be-bonded surface of the wafer to be flat; s2, cleaning a to-be-bonded surface of the wafer, and removing organic pollutants and an oxide layer; s3, aligning and fitting the surfaces to be bonded of the two wafers; s4, enabling the to-be-bonded surfaces to comprise dielectric layers and metal interconnection points, irradiating the dielectric layers with infrared laser, and carrying out the interconnection of the dielectric layers of the two to-be-bonded surfaces; and S5, the metal interconnection points are heated by blue laser, and the metal interconnection points of the two surfaces to be bonded are interconnected. In the hybrid bonding stage, the infrared laser and the blue laser are used for bonding the dielectric layer and the metal interconnection point respectively, partitioned irradiation and differentiated heating of the metal interconnection point and the dielectric layer are achieved, the problems of interface warping, microcracks and other thermal damage are effectively avoided, and the interconnection quality and the packaging reliability are improved.

The invention discloses a GaN HEMT / MOSFET monolithic integrated cascade device and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a GaN HEMT device and a GaN MOSFET device, wherein the GaN HEMT device and the GaN MOSFET device are electrically connected through a metal interconnection structure; the GaN MOSFET device is prepared above the vertical structure of the GaN HEMT device, and the projection position of the GaN MOSFET device is located between the grid electrode and the drain electrode of the GaN HEMT device; isolation grooves are arranged among different GaN HEMT / MOSFET cascade devices distributed along the transverse direction of the substrate, and electrical isolation among the different cascade devices is realized through the isolation grooves. The interface defect is reduced through one-time epitaxial growth, the chip area is reduced through vertical integration, the voltage resistance and high-frequency performance of the device are improved, and the device is suitable for the field of efficient power conversion.

A packaged integrated circuit (IC) including a semiconductor die having a metallization layer, the metallization layer including first metal interconnects in a first insulation material. The IC includes a first substrate on the metallization layer, the first substrate including second metal interconnects in a second insulation material different from the first insulation material, at least one of the second metal interconnects being electrically coupled to at least one of the first metal interconnects. The IC further includes a second substrate on the first substrate, the second substrate including an isolation circuit and third metal interconnects in a third insulation material different from the first insulation material, the isolation circuit being electrically coupled to the at least one of the first metal interconnects via the at least one of the second metal interconnects and at least one of the third metal interconnects.

The invention belongs to the technical field of surface engineering, and relates to a preparation method of a protective coating for a metal connector of a solid oxide battery. A compact transition metal oxide inner layer is deposited on a metal substrate in a reactive sputtering mode, then a transition metal alloy outer layer is deposited in a metal sputtering mode, a transition metal oxide / transition metal alloy composite coating is formed, and a spinel protective layer is formed after annealing treatment. According to the method, a transition metal oxide inner layer is used as a diffusion barrier layer, diffusion of elements such as Cr from a substrate to a coating and diffusion of oxygen to the substrate in the high-temperature annealing and long-term service process are effectively inhibited, and therefore the thickness of a reaction layer and the thickness of a thermal growth oxide layer are remarkably reduced. The composite coating is compact in structure, stable in component, good in matching with the thermal expansion coefficient of the substrate, excellent in oxidation resistance and low in surface specific resistance, and capable of effectively improving the long-term operation stability and prolonging the service life of the SOC connector.

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

The application discloses a semiconductor device and a curve processing method of a semiconductor device layout. The semiconductor device comprises a metal interconnection layer; a metal coverage area of the metal interconnection layer is a closed area formed by a plurality of boundary lines with different directions and connected by transition lines; the transition line between two adjacent boundary lines is a curve determined according to the intersection relationship of the two boundary lines, and the opening direction of the curve and the intersection point of the two boundary lines are located on the two sides of the curve. The end points of the related lines forming the metal interconnection layer are taken as processing objects, and the transition lines are used for transition at the positions where the related lines change direction, so that the overall coverage adjustment of each angle is realized, the inradius of all concave corner positions is increased as much as possible, the stress distribution concentration effect at each concave corner is weakened, the crack formation is avoided, the metal electromigration, the connected lines or the broken lines and other phenomena are eliminated, the product quality is obviously improved, and the chip life is prolonged.

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first conductor, a first insulating layer, a second conductor and a metal interconnection structure. The first conductor is arranged in a first dielectric layer. The first insulating layer is arranged on the first dielectric layer and covers the first conductor. The second conductor is arranged in a second dielectric layer and partially overlaps the first conductor. The metal interconnection structure is arranged in the second dielectric layer and the first insulating layer and physically contacts a top surface of the first conductor, a top surface of the second conductor and a sidewall on one side of the second conductor. Thus, the performance and reliability of the wiring structure are improved by arranging the metal interconnection structure under the premise of saving space, so that the semiconductor device achieves more optimized operation performance.

The invention discloses a wafer bearing structure, a preparation method, a processing device, a control system and a method for compensating wafer morphology, the structure is characterized in that a CMOS (Complementary Metal Oxide Semiconductor) control circuit is integrated on a semiconductor substrate, micro-cavities arranged in an array are manufactured in an interlayer insulating layer above the CMOS control circuit, and the micro-cavities are filled with micro-driving units consisting of conductive layers and piezoelectric material layers; and a supporting body for supporting the wafer is arranged above the unit. And the micro-driving unit is connected with the CMOS circuit through the metal interconnection layer exposed at the bottom of the cavity. The manufacturing method comprises the steps of photoetching and trepanning in the insulating layer, depositing a functional material, planarizing and the like. The control system is composed of an external height detection module, a main control module, a digital-to-analog conversion module and a CMOS driving circuit in the structure in a cooperative manner, and can independently and accurately control each micro-driving unit to generate nanoscale deformation through the CMOS circuit according to real-time morphology data of a wafer, so that local micro fluctuation of the wafer is compensated in real time, and photoetching defocus is effectively prevented.

The invention relates to OLED micro-display, in particular to a silicon-based OLED micro-display device based on a magnetic random access memory and a driving method of the silicon-based OLED micro-display device based on the magnetic random access memory. The CMOS driving circuit receives the instruction and the frame data sent by the main controller, transmits the instruction and the frame data to the metal interconnection layer, and reads the stored frame data from the metal interconnection layer to drive the OLED light-emitting layer; the metal interconnection layer judges that the CMOS driving circuit reads the stored frame data or directly uses the frame data sent by the main controller to carry out display driving according to the system state, and carries out MRAM frame caching on the frame data sent by the main controller; the OLED light-emitting layer is attached to the surface of the metal interconnection layer, adopts a pixel array structure, and emits light under the action of the CMOS driving circuit to realize picture display; according to the technical scheme provided by the invention, the defects of low starting speed, high power consumption and complex system structure in the prior art can be effectively overcome.

Provided in the present disclosure are a preparation method for a semiconductor device, the semiconductor device and an electronic apparatus. The preparation method for a semiconductor device comprises: forming an active structure on a substrate; forming a first semiconductor structure; bonding the first semiconductor structure and a first carrier wafer and flipping same over; removing the substrate to expose a second active structure; forming a second semiconductor structure; bonding the second semiconductor structure and a second carrier wafer and flipping same over; removing the first carrier wafer to expose the first semiconductor structure; forming a first gate structure in the first semiconductor structure; forming first source-drain metal on a first source-drain structure; forming a first metal interconnect structure on a first transistor; bonding the first metal interconnect structure and a third carrier wafer and flipping same over; removing the second carrier wafer to expose the second semiconductor structure; and forming a second metal interconnect structure.

The invention relates to an electrical property testing device and an electrical property testing method of a silicon substrate chip. The device comprises a wafer-level chip to be tested and a test platform, the wafer-level chip to be tested comprises a plurality of core particles and a plurality of test areas; the core particles are connected based on interconnection lines; a metal interconnection structure is pre-buried on the core particle; each test area covers the crossed area of the four core particles; the crossed region comprises a part of metal interconnection structure; and the test platform is used for controlling the probe card to be in contact with the metal interconnection structures in the test areas to carry out an electrical test on the wafer-level chip to be tested. According to the electrical property testing device, a wafer level interconnection electrical property testing method based on a window translation mode can be realized, and a whole set of testing solution which can cover the whole wafer, can be reused and can be traced is designed aiming at the reliability problem of a cross-region interconnection structure in a large-scale photomask splicing process.

A semiconductor structure includes a back-end-of-line region including a first level of metal interconnects and a second level of metal interconnects separated by at least one interlayer dielectric layer, and a laser debonding test structure disposed in the back-end-of-line region. The laser debonding test structure includes a testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects, a set of test pads, and a set of vias, at least a subset of the set of vias extending from at least one test pad in the set of test pads to the testable metal plate layer disposed within the at least one interlayer dielectric layer between the first level of metal interconnects and the second level of metal interconnects.

A structure includes boron nitride nanotubes, wherein the structure (i) is an extension region in a field-effect transistor or (ii) comprises a metallic interconnect to reduce the dielectric constant and therefore the RC-delay in the device. Also, a field-effect transistor structure includes a low-k spacer layer between metallic interconnects, wherein the low-k spacer layer includes boron nitride nanotubes. In addition, a method for reducing RC delay in an integrated circuit includes forming a component of the integrated circuit from boron nitride nanotubes.

The invention discloses a post-etching processing method for improving copper loss in a through hole array region in a semiconductor device, which is particularly suitable for a back-end metal interconnection dual damascene process. In order to solve the problem of copper loss at the bottom of a through hole caused by insufficient conventional post-etching treatment after integrated etching and before wet stripping, an enhanced post-etching treatment step is executed after a through hole structure for exposing lower-layer copper metal is formed by integrated etching and before wet stripping. The key point of the enhancement step is to treat the exposed copper surface with a reducing plasma comprising hydrogen (H2), optionally further comprising nitrogen N2. The treatment can passivate a copper surface and / or reduce a copper compound formed in etching, so that copper loss and related through hole abnormal defects are remarkably reduced, and a process window of subsequent wet stripping is expanded, so that the reliability and the manufacturing yield of the device are improved, and the effect is particularly remarkable for a high-density through hole array.

A device structure may be manufactured by forming metal interconnect structures embedded in dielectric material layers over a substrate; forming active metal connection structures, primary dummy metal structures, and miniature dummy metal structures over a topmost dielectric material layer selected from the dielectric material layers, wherein the miniature dummy metal structures have a lesser height than the active metal connection structures and the primary dummy metal structures; and forming bonding pads over the active metal connection structures, the primary dummy metal structures, and the miniature dummy metal structures, wherein the active metal connection structures and the primary dummy metal structures are contacted by the bonding pads, and the miniature dummy metal structures are not contacted by any of the bonding pads.

The invention discloses a semiconductor device which comprises a substrate, a gate structure, a plurality of insulating intervals, a plurality of first bonding pads, an insulating layer and a high-dielectric-constant material layer. The insulating spacers and the gate structures are alternately disposed on the substrate. The first pad is disposed on the insulating space. The insulating layer covers the insulating interval and the gate structure, and the insulating layer covering the gate structure is provided with a recess. The high dielectric constant material layer is disposed in the recess, and the bottommost surface of the high dielectric constant material layer is lower than the topmost surface of the first pad. Therefore, by means of the arrangement of the high-dielectric-constant material layer and / or the insulating layer, the structural defect of the top of the gate structure is improved, and the problem of possible short circuit between the gate structure and the metal interconnection line arranged above is avoided.

A method of manufacturing a semiconductor device includes providing a semiconductor substrate layer including a metal interconnect feature embedded in the semiconductor substrate layer and depositing a liner layer on the metal interconnect feature. The method further includes depositing an etching stop layer on the liner layer and the semiconductor substrate layer and forming a dielectric layer on the etching stop layer with a via trench to expose the etching stop layer. The method also includes etching the etching stop layer and the liner layer to form a via structure to expose the metal interconnect feature, wherein the via structure has an hourglass-shaped profile.

A phase change material switching circuit may be provided by forming a semiconductor circuit including a power amplifier and a low noise amplifier on a substrate; forming metal interconnect structures embedded in first dielectric material layers over the power amplifier and the low noise amplifier; forming a first phase change material (PCM) switch and a second PCM switch over the first dielectric material layers, wherein the first PCM switch includes a first electrode and a second electrode, and the second PCM switch includes a third electrode and a fourth electrode, wherein the second electrode is electrically connected to the third electrode to form a common electrical node; and electrically connecting a radio-frequency (RF) antenna to the common electrical node.

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

The invention provides a preparation method of a metal interconnection structure and the metal interconnection structure, and the method comprises the steps: forming a first dielectric layer and a plurality of through holes in the first dielectric layer on a substrate on which a semiconductor device layer and a first metal wiring layer are formed, and then employing a flowable organic material as a second dielectric layer on the first dielectric layer, and a plurality of metal grooves are formed in the second dielectric layer, and after the remaining second dielectric layer is cured, the through holes and the metal grooves are filled with second metal to form a metal interconnection structure. The preparation process of the through hole and the metal wire is divided into independent parts according to the sequence, so that the depth-to-width ratio of through hole etching is reduced during preparation of the through hole, and the etching process window is increased; in addition, a curable organic matter is adopted as a dielectric layer of the metal wire, the thickness of photoresist is reduced during preparation of the metal wire, a photoetching process window is increased, and meanwhile, due to the low dielectric constant of the organic matter, the parasitic capacitance between the metal interconnection wires is effectively reduced.

Aspects of utilizing formate shells for metal structures on integrated circuit components include an integrated circuit device component including one or more metal interconnect structures and a formate shell on each of the one or more metal interconnect structures.

The present disclosure provides an integrated circuit device in which a capacitor is connected between two vias through a passivation stack to couple a power supply contact to a metal interconnect structure. By providing enough high capacitance and enough low equivalent series resistance for the capacitor, the noise in the power supply can be effectively filtered. The capacitor may have a trench capacitance structure as part of a solution for providing sufficiently high capacitance. Placing all or part of the capacitor within the passivation stack allows the capacitor to be implemented without moving the wiring or device in the metal interconnect structure.

Package substrate with a core having metallization layers to facilitate signal routing within the core, and related fabrication methods and integrated circuit (IC) packages. The core includes multiple core metallization layers that can be formed separately and coupled to each other to provide signal routing within the core. Metal interconnects in the multiple core metallization layers are coupled to each other through coupling of the core metallization layers to each other in the core to provide signal routing paths through the core. Including separate core metallization layers in the core provides flexibility in patterning location of the metal interconnects therein for routing flexibility within the core. This is opposed to only including singular body, vertical interconnects extending through the entire height of the core. Metal interconnects can also be patterned to extend laterally within a respective core metallization layer to provide lateral signal routing paths within a core metallization layer.

Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

The invention discloses an acquisition and stimulation in-situ integrated capacitive coupling type active neural electrode array and a preparation method thereof. The electrode array comprises a flexible substrate and a plurality of neural electrode units on the flexible substrate, the neural electrode unit comprises two silicon nano films, a gate dielectric layer, a metal layer and a capacitive coupling dielectric layer, wherein the two silicon nanometer films are located on the flexible substrate, the gate dielectric layer covers the silicon nanometer films, and the metal layer comprises electrode metal, a metal bonding pad and a metal interconnection line; the electrode metal is matched with the two silicon nanometer films, the gate dielectric layer and the flexible substrate to form a selection transistor and a driving transistor, and the metal bonding pad is matched with the capacitance coupling dielectric layer to form an electrode contact; metal interconnects electrically connect the select transistors, the drive transistors, and the electrode contacts. The selection transistor and the driving transistor form an acquisition and stimulation closed-loop control unit, so that synchronous electroneurographic signal acquisition and electrical stimulation are realized, the experiment and treatment efficiency is improved, and the loss and interference in the signal transmission process are reduced.

This invention discloses a semiconductor device and its fabrication method. The method for fabricating the semiconductor device involves first forming a magnetic tunneling junction (MTJ) in an MRAM region on a substrate, then forming a first intermetallic dielectric layer around the MTJ, forming a patterned mask in a logic region on the substrate, performing a nitriding process to convert a portion of the first intermetallic dielectric layer into a nitrided layer on the MTJ, forming a first metal interconnect in the logic region, forming a stop layer on the first intermetallic dielectric layer, forming a second intermetallic dielectric layer on the stop layer, and finally forming a second metal interconnect in the second intermetallic dielectric layer and connecting it to the MTJ.