767 results about "Metal interconnect" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers having formed therein interposer metal interconnect structures, A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers having formed therein router metal interconnect structures and a router substrate having formed therein router through-substrate via structures therein. A backside of the router substrate may be thinned to expose end surfaces of the router through-substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. Bonding pads of the memory dies are electrically connected to the router through-substrate via structures.

According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

The invention discloses a semiconductor chip, a preparation method of a metal interconnection layer and the metal interconnection layer. The semiconductor chip comprises a semiconductor substrate, and a plurality of device structures are formed on the semiconductor substrate; the metal interconnection layer is located above the semiconductor substrate and used for connecting a plurality of device structures, and the metal interconnection layer at least comprises a first titanium layer located above the semiconductor substrate, a second titanium layer located above the semiconductor substrate and a third titanium layer located above the semiconductor substrate; a first titanium nitride layer over the first titanium layer; a metal layer over the first titanium nitride layer; the at least two groups of composite barrier layers are positioned above the metal layer; each group of composite barrier layers comprises a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each group of composite barrier layers is smaller than a first preset thickness; and the sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than a second preset thickness. According to the semiconductor chip, the metal residue defect on the surface of the semiconductor substrate is reduced while the thickness requirement is met.

The invention belongs to the technical field of semiconductor processing, and particularly relates to a method for improving 3D wafer stacking electric leakage and a semiconductor structure. A wafer is provided, the wafer comprises a substrate layer and an oxide layer, one side of the oxide layer is a bonding surface, and one side of the substrate layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, a through hole is formed in the oxide layer from the bonding surface side, and the through hole is communicated with the metal interconnection structure and is filled with a conductor layer; the bonding surfaces of one wafer and the other wafer are opposite, and the conductor layers of the two wafers are communicated; a TSV through hole is formed in the bottom face of any wafer in the direction of the metal interconnection structure, and the TSV through hole is communicated with the metal interconnection structure; depositing an oxidation deposition layer in the TSV through hole, wherein the oxidation deposition layer at least covers the side wall of the TSV through hole; and depositing a TSV through hole conductor layer in the TSV through hole, wherein the TSV through hole conductor layer is communicated with the metal interconnection structure. Through a simple process, the problem of electric leakage of the TSV is solved, and the reliability of the semiconductor device can be improved.

The invention relates to a preparation method of a surface acoustic wave filter integrated with a CMOS (Complementary Metal Oxide Semiconductor) process, which comprises the following steps of: preparing a CMOS radio-frequency signal processing circuit by using a silicon or silicon carbide substrate, combining a dielectric buffer layer with a piezoelectric material, and then depositing a metal interdigital structure on the surface of the piezoelectric material to prepare the surface acoustic wave filter. A passivation layer is deposited on the surface of the filter to protect the filter structure, finally a metal interconnection line and the passivation layer are prepared above the filter, and in order to not affect the performance of the filter, an air cavity is prepared between the passivation layer and the metal interconnection layer of the filter, so that the passivation layer and the metal interconnection layer are effectively isolated. According to the preparation method, the surface acoustic wave filter and the CMOS radio frequency circuit can be integrated, the problem that radio frequency front-end and rear-end signal processing cannot be integrated at the same time at present is solved, and the preparation method plays an important role in promoting development of a radio frequency chip in the directions of high integration, low cost, miniaturization and the like; and the radio frequency chip has wide practical value and economic value in the radio frequency chip application field.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed. A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers in which router metal interconnect structures are formed and a router substrate in which router substrate via structures are formed. A backside of the router substrate may be thinned to expose end surfaces of the router substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. The bonding pads of the memory dies are electrically connected to the router substrate via structures.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A flip-chip bonded photonic device and methods of fabrication are described. The device has a spot size converter and an antireflective coating on a sidewall of the spot size converter. The device has a semiconductor layer comprising a stack of quantum wells and an etch stop semiconductor layer beneath the layer comprising a stack of quantum wells. The device has a vertical sidewall for optical coupling and a sloped sidewall for metal interconnects. The device has a substrate and an optical waveguide residing above substrate. A mirror is coupled to the optical waveguide that bends light from the optical waveguide and transmits the light through the substrate. The light expands as it passes through the substrate. A collimating lens receives the light transmitted through the substrate and is lithographically aligned with the mirror. An optical engine has a flip-chip integrated electro-absorption modulated laser (EML) on a substrate.

Interposer substrate with integrated step die cavity, and related integrated circuit (IC) packages and related fabrication methods. A die cavity integrated in an outer layer(s) of the interposer substrate provides room for a die to extend into the interposer substrate (e.g., to facilitate increased die height). Forming the die cavity in the outer layer(s) facilitates metal interconnects in an outer metallization layer of the interposer substrate being located adjacent to the die cavity can also enhance heat dissipation for the die extending into the die cavity. Forming the die cavity in the outer layer(s) of the interposer substrate also facilitates reduced distance between the interposer substrate and package substrate to facilitate reduced height vertical interconnects coupling the interposer substrate to the package substrate. This facilitates vertical interconnects with reduced aspect ratio and reduced pitch that can support dies with higher input / output (I / O) connection density.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

Provided in the present invention is a silicon bridge module integrated with a passive device. The silicon bridge module comprises a substrate, a first insulating layer, which is arranged on a first surface of the substrate, a capacitor, which is arranged on a surface of the first insulating layer, a second insulating layer, which is arranged on a surface of the capacitor and exposes at least part of an electrode of the capacitor, a first metal interconnection layer, which is arranged on a surface of the second insulating layer and is electrically connected to the capacitor, and an external pad, which is arranged on the outermost layer of the first metal interconnection layer and is electrically connected to the first metal interconnection layer, wherein the first metal interconnection layer comprises one or more layers of conductive lines and an insulating medium arranged between the conductive lines, and an inductive device is integrated in the first metal interconnection layer. The silicon bridge module achieves the integration of an inter-chip interconnection line and a passive device, integrates processing functions for signals or power distribution networks and achieves high-speed signal transmission, improves the integration degree of a system, reduces the packaging volume, and can be applied in the field of heterogeneous integrated products, e.g., chiplets.

Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).

An electronic device having a substrate employing reduced area, added metal pad(s) to a metal interconnect(s) to reduce air voids in a solder joint and related fabrication methods are disclosed. The electronic device includes a die that has die interconnects coupled to a first metal pad(s) of a respective metal interconnect(s) of a metallization layer of the substrate through a second, additional metal pad(s). To facilitate a reduction in air voids in the solder joint between the die and the first metal pad(s) and consequently the amount of solder between the first metal pad and the die, the second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is above and adjacent to the first metal pad(s). A solder joint(s) is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate.

The invention relates to the technical field of semiconductors, and discloses an electro-optical modulator and a preparation method thereof, and the preparation method comprises the steps: forming a waveguide core and a plurality of electrodes on a part of the surface of one side, opposite to a first substrate, of a first cladding, and dividing the waveguide core into an internal waveguide core and an external waveguide core; at least part of the electrode further goes deep into the first cladding of partial thickness; forming a second wrapping layer wrapping the electrode and the waveguide core on the surface of the first wrapping layer; forming a plurality of metal interconnection lines on the surface of the second cladding, wherein each metal interconnection line also penetrates through the second cladding and is connected with one electrode; forming a bonding groove penetrating into the partial thickness of the second cladding; forming an electro-optical thin film layer comprising an equal-thickness region and a thickness gradient region in the bonding groove; the projection of the equal-thickness area completely covers the internal waveguide core, and the projection of the thickness gradient area at least covers part of the external waveguide core. The CMOS technology compatibility of the device can be improved, the insertion loss of the device is reduced, and the integration level and the space utilization rate of an optical chip are improved.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention discloses a vertically-stacked 2T0C DRAM (Dynamic Random Access Memory) unit based on an oxide semiconductor ring gate transistor and a preparation method of the vertically-stacked 2T0C DRAM unit. According to the 2T0C DRAM unit, a first metal interconnection layer, a read transistor layer, a second metal interconnection layer, an isolation layer, a write transistor layer and a third metal interconnection layer are sequentially stacked on a substrate from bottom to top, a read transistor and a write transistor are oxide semiconductor transistors of a vertical ring gate structure, and the two transistors are vertically stacked. Compared with a planar transistor, the DRAM unit has more excellent electrical performance, the working voltage and the characteristic size of the DRAM unit are effectively reduced, and the integration density is improved. By adopting the ring gate structure, the gate control capability can be effectively improved, the same charging current as that of a planar transistor can be realized under a relatively low power supply voltage, and the charge leakage in a holding state is reduced, so that the DRAM gives consideration to both ultra-fast writing and ultra-long data holding time. And meanwhile, the vertically stacked structure reduces the area overhead of the DRAM unit and reduces the wiring difficulty.

Aspects disclosed include an integrated circuit (IC) package comprising a substrate and a solder joint coupled to a corner interconnect structure of the substrate to improve the reliability of the package. Related apparatus and methods are also disclosed. The substrate includes the corner interconnect structure in a corner of the substrate. The corner interconnect structure includes a first metal interconnect adjacent to the corner of the substrate and a plurality of second metal interconnects adjacent to the first metal interconnect. The IC package includes a solder joint coupled to at least two of the metal interconnects in the corner interconnect structure improving the mechanical reliability of the IC package. In so doing, a plurality of third metal interconnects adjacent to the corner interconnect structure may be utilized for input / output (I / O) communication paths increasing the input / output of the IC package without growing the size of the package.

The invention relates to the technical field of hybrid bonding, in particular to a laser-assisted hybrid bonding interconnection method, which comprises the following steps of: S1, processing the surface of a wafer to enable the to-be-bonded surface of the wafer to be flat; s2, cleaning a to-be-bonded surface of the wafer, and removing organic pollutants and an oxide layer; s3, aligning and fitting the surfaces to be bonded of the two wafers; s4, enabling the to-be-bonded surfaces to comprise dielectric layers and metal interconnection points, irradiating the dielectric layers with infrared laser, and carrying out the interconnection of the dielectric layers of the two to-be-bonded surfaces; and S5, the metal interconnection points are heated by blue laser, and the metal interconnection points of the two surfaces to be bonded are interconnected. In the hybrid bonding stage, the infrared laser and the blue laser are used for bonding the dielectric layer and the metal interconnection point respectively, partitioned irradiation and differentiated heating of the metal interconnection point and the dielectric layer are achieved, the problems of interface warping, microcracks and other thermal damage are effectively avoided, and the interconnection quality and the packaging reliability are improved.

The invention discloses a low-temperature hybrid bonding interconnection structure and a manufacturing method thereof. The low-temperature hybrid bonding interconnection structure comprises a first substrate with an embedded metal structure, a second substrate with an embedded metal structure, an etching barrier layer, an amorphous dielectric layer, a bonding auxiliary layer, a first bonding layer, a second bonding layer, a first bonding layer and a second bonding layer, and the interconnection metal is embedded in the bonding auxiliary layer, the amorphous dielectric layer and the etching barrier layer, and the interconnection metal has a conductive diffusion barrier and a seed layer on a contact interface with the bonding auxiliary layer, the amorphous dielectric layer and the etching barrier layer. The interconnect metal forms an electrical connection with the embedded metal structure of the first substrate and the embedded metal structure of the second substrate. The ultra-vacuum oxygen-free surface activation bonding technology is adopted, the amorphous media are bonded together through the polycrystalline bonding auxiliary layer, and mixed bonding with lower metal interconnection resistance can be achieved at low temperature or even room temperature.

A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.