119 results about "Ball grid array" patented technology

The invention discloses BGA (Ball Grid Array) packaging intelligent wobble plate equipment, which comprises a rack, and is characterized in that the rack is provided with a loading station, a feeding station, a loading station, an overturning station, a stacking station and a discharging station; the feeding frame is arranged on the feeding station, and a feeding driving mechanism is arranged on the feeding frame; the stacking box is arranged at the discharging station, and a discharging driving mechanism is arranged on the rack; the clamping and transferring mechanism is used for clamping and transferring a loading template from a stacking box to the loading station or clamping and transferring a packaged finished product from the loading station to the stacking box for stacking treatment, and the overturning station is located on a transferring path of the clamping and transferring mechanism; the loading mechanism is arranged at the loading station; and the turnover mechanism is arranged at the turnover station, a turnover space is formed between the turnover mechanism and the clamping and transferring mechanism, and a jacking driving mechanism is arranged on the rack. According to the automatic tray placing and overturning device, automatic tray placing and overturning operation is achieved, and the production efficiency is effectively improved.

The invention discloses a BGA packaging defect detection method and system based on deep learning. The method comprises the steps that a to-be-detected image of a to-be-detected ball grid array chip is acquired; reasoning the to-be-detected image by adopting a first deep learning model so as to identify and position key components on each to-be-detected ball grid array chip; carrying out anomaly detection on the geometric parameters of the key component to obtain a geometric parameter detection result; carrying out surface defect detection on the to-be-detected image in parallel by adopting a second deep learning model group so as to identify various surface defects on the surface of the substrate of the to-be-detected ball grid array chip, and obtaining a surface defect detection result; and determining a defect detection result of the to-be-detected ball grid array chip based on the geometric parameter detection result and the surface defect detection result, thereby realizing a self-adaptive, high-beat and comprehensive BGA packaging defect detection method.

An electronic device including an IC having a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the IC package. The IC package includes a substrate comprising an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The pillar has a top surface and a bottom surface. The pillar extends through the package mold layer with the top surface coupled to the metal pad and the bottom surface coupled to the solder cap. In contrast to conventional package interconnects, such as ball grid arrays (BGA), for example, deploying the solder cap on the bottom surface of the pillar advantageously results in using less solder and tighter pitch between adjacent package interconnects because the width of the pillar is less than a solder ball in a BGA.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

A method of manufacturing a printed circuit board (PCB) includes arranging a first trace segment of a trace on a substrate of the PCB, the substrate being composed of fiber glass strands that define a fiber glass weave pattern, and arranging a second trace segment of the trace on the substrate at a position that is fractionally offset from the first trace segment along an axis by a distance that is less than a ball grid array (BGA) pitch of a BGA based on the fiber glass weave pattern. The BGA pitch is a separation distance along the axis between a center of a first via of the BGA of the PCB and a center of a second via of the BGA.

The application discloses a quantum device and an electronic device and a preparation method thereof, and belongs to the field of quantum information. The quantum device comprises a quantum chip, a signal transmission element formed on the quantum chip, and a connecting part electrically connected with the signal transmission element; a packaging substrate, a lead-out part formed on the packaging substrate, and a lead-out signal line for electrically connecting with a signal connector, the lead-out signal line being electrically connected with the lead-out part; and a ball grid array electrically connecting the corresponding connecting part and the lead-out part. The ball grid array electrically connects the connecting part and the lead-out part corresponding to the signal transmission attribute, thereby realizing the electrical connection between the quantum chip and the transmission line, and further leading out the connecting part to the external signal connector. In the application, the ball grid array does not generate a complex field effect, and the electrical connection of the corresponding connecting part and the lead-out part by the ball grid array can avoid the interference caused by the bonded aluminum wire.

The invention discloses a Ka wave band four-channel transceiving SiP module based on silicon-based packaging and a manufacturing method thereof, the SiP module adopts a silicon-based packaging material and comprises an upper layer sub-packaging and a lower layer sub-packaging, and the upper layer sub-packaging and the lower layer sub-packaging are vertically interconnected through a ball grid array (BGA); the lower-layer sub-package comprises three layers of silicon adapter plates with a first thickness, a cavity for mounting a three-port transceiver chip is etched on the middle-layer silicon adapter plate, and a TSV with a first diameter is manufactured on each layer of silicon adapter plate; the upper layer sub-package comprises three layers of silicon adapter plates, the upper layer silicon adapter plate and the lower layer silicon adapter plate have a first thickness and are provided with TSVs with a first diameter, the middle layer silicon adapter plate is etched with a cavity used for mounting a silicon-based amplitude-phase multifunctional chip and a power supply modulation chip, the middle layer silicon adapter plate has a second thickness and is provided with TSVs with a second diameter, and the middle layer silicon adapter plate is etched with a cavity used for mounting a silicon-based amplitude-phase multifunctional chip and a power supply modulation chip. Wherein the second thickness is greater than the first thickness and the second diameter is greater than the first diameter. According to the invention, the requirements of miniaturization, integration and high performance of a radar system can be met.

The application discloses a kind of ball grid array package chip solder ball bubble defect automatic detection method and system, it is related to chip intelligent detection technical field, the method is guided by designing semantic cross-layer fusion framework, realizes multi-scale feature balanced fusion in neck network by introducing feature alignment and redistribution module, strengthens small target details and semantic information using local semantic enhancement module, and the positioning accuracy of bubble is optimized in combination with smooth geometry positioning loss function.The application significantly improves the detection capability of small, fuzzy and occluded bubbles, has strong robustness and generalization, and can be widely used in solder ball bubble, material porosity and surface defect industrial vision detection scene.

The invention discloses a water-soluble soldering flux capable of being used for high-temperature ball mounting, which belongs to the technical field of electronic packaging, and comprises the following components in percentage by mass: 70-95% of ionic liquid, 5-30% of organic acid, 5-30% of cosolvent and 0.1-10% of other functional components, and the sum of the mass percentages of the components is 100%. The water-soluble soldering flux is prepared by heating, mixing, stirring and cooling. The soldering flux can be applied to electronic soldering tin welding processes such as a surface mounting process and a ball grid array (BGA) ball mounting process. The high-temperature-resistant ionic liquid and the high-temperature-resistant organic acid are used for manufacturing the high-temperature-resistant scaling powder, meanwhile, the high decomposition temperature of the high-temperature-resistant ionic liquid and the high-temperature-resistant organic acid is used for increasing the active window of the scaling powder, the situation that the active temperature window is too low due to use of a traditional solvent is avoided, and the high-temperature-resistant scaling powder can be used for high-temperature or high-

The invention discloses a geometric-process comprehensive parameter optimization method, system and equipment for BGA welding spot reflow soldering. Designing a geometric model of the BGA welding spot, and storing data as a form as a data set based on a preset geometric-process parameter level; performing finite element simulation of the reflow process by using an orthogonal test method to obtain a deformation value of the welding spot; the method comprises the following steps: carrying out range analysis to obtain a geometric-process parameter level corresponding to the minimum deformation of a welding spot after reflow soldering, carrying out finite element simulation to obtain the minimum deformation, carrying out weight analysis to obtain parameters with obvious influence, and sorting the parameters, so that the geometric structure and reflow process parameters of the welding spot are quickly optimized under the finite simulation results, and the optimization efficiency is improved. According to the method, the deformation value of a welding spot after reflow soldering is reduced, meanwhile, each geometric-process can be evaluated, the weight of each geometric-process parameter is obtained, the key optimized parameter is determined, and therefore a certain reference significance is provided for the actual reflow soldering process.

The invention discloses a three-dimensional stacked frequency conversion SIP (Session Initiation Protocol), which comprises a bottom BGA (Ball Grid Array), three-dimensional stacked middle layer solder balls, a ceramic bottom plate, a kovar enclosure frame, a cover plate and a reconfigurable upper-layer multi-layer printed board, the ceramic bottom plate, the kovar enclosure frame and the cover plate jointly form a ceramic shell; a reconfigurable upper-layer multilayer printed board is stacked on the ceramic bottom plate through three-dimensional stacked middle-layer solder balls, an inner cavity of the ceramic shell is divided into a lower cavity body and an upper cavity body, the lower cavity body is provided with a bottom-layer chip installation area on the upper surface of the ceramic bottom plate, and the bottom-layer chip installation area is used for installing a universal functional chip. The upper cavity is provided with an upper-layer reconfigurable chip mounting area on the upper surface of the reconfigurable upper-layer multi-layer printed board, and the upper-layer reconfigurable chip mounting area is used for mounting a reconfigurable functional chip; a bottom BGA ball grid array is arranged on the lower surface of the ceramic bottom plate and used for leading out radio frequency, power supply and control signals. Through a three-dimensional stacking structure and a reconfigurable technology, a high-flexibility and high-reliability packaging solution is realized, and the customization cost is reduced.

The invention relates to the technical field of microwave radio frequency components, in particular to a BGA delay driving component based on an HTCC process. According to the technical scheme, the device comprises a shell and further comprises a cover plate used for improving the sealing performance of the device, the cover plate is arranged on the outer side of the shell, an HTCC multi-layer circuit substrate is arranged at the lower position in the shell, a four-bit time delay unit MMIC chip is arranged at the middle position of the HTCC multi-layer circuit substrate, and the four-bit time delay unit MMIC chip is arranged at the lower position of the HTCC multi-layer circuit substrate. And a wave control chip is arranged on the right side of the four-bit time delay unit MMIC chip. Through the characteristics of the HTCC process, the assembly has the advantages of high mechanical strength, high wiring density, stable chemical performance, high heat dissipation coefficient, low material cost and the like, and meanwhile, the ball grid array packaging (BGA) technology is applied to an integrated circuit, so that the BGA packaging has low insertion loss, excellent signal integrity, compact size, high integration level and high reliability. Therefore, the high-speed performance is better.

A sub-pixel-level detection method and application for ball grid arrays (BGAs) of packaged chips is disclosed. The method includes: acquiring a binary image of the solder ball array of the BGA; extracting all solder ball regions from the binary image and filtering to obtain all solder balls; extracting edge pixels of each solder ball and determining the sub-pixel edge points of each solder ball based on the grayscale value difference between each edge pixel and its adjacent pixels; obtaining the center coordinates and radius of each solder ball based on its sub-pixel edge points; rotating the binary image using an affine transformation method to calculate the transformed center coordinates of each solder ball in a two-dimensional coordinate system; and determining the row and column positions of each solder ball based on its transformed center coordinates and radius to complete the sub-pixel-level detection of the BGA. This application achieves sub-pixel-level detection of ball grid arrays, solving the problem of low recognition accuracy in existing ball grid array components.

The invention provides a multifunctional ball grid array packaging device soldering paste printing device which comprises a device positioning assembly, the device positioning assembly is installed on a base, the positioning assembly comprises a device tray, a positioning push plate and a driving module, the positioning push plate and the driving module are arranged on the device tray, and the device tray is provided with a plurality of device grooves; the positioning push plate is provided with a plurality of device grooves, the plurality of device grooves and the plurality of device grooves are arranged in a one-to-one correspondence manner, preset points are arranged on the edges of the device grooves, and the driving module drives the positioning push plate to move so as to drive the ball grid array packaging device to move and enable the ball grid array packaging device to be in contact with the preset points; the steel mesh assembly is arranged above the device positioning assembly, the steel mesh assembly comprises a steel mesh frame and a steel mesh installed in the steel mesh frame, and the steel mesh is selected from one of a printing steel mesh and a ball mounting steel mesh; the demolding assembly is installed on the base and used for driving the steel mesh assembly to be away from or close to the positioning assembly; and a base.

This application relates to a PCB circuit board, a layout method, and a chip. The PCB circuit board includes a board body and vias. The board body includes multiple layers connected by vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal via and an adjacent ground via, and the spacing between each signal via and other adjacent signal vias, are defined as a first spacing. The spacing between each ground via and other ground vias is defined as a second spacing. Both the first and second spacings are less than a reference spacing and greater than or equal to a minimum process spacing. The reference spacing is the spacing between solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board. Using this PCB circuit board can reduce signal line crosstalk.

Disclosed are semiconductor packages. A semiconductor package may include a first die encapsulated by a mold, and a second die directly on the mold. One or more conductive posts may be formed in the mold. A frontside redistribution layer (RDL) may be provided on a lower surface of the mold. Electrical signals between the first and second dies may be carried through the posts and the frontside RDL. There is no need for backside RDL and backside ball grid array. This can significantly reduce the height of the semiconductor package.

A circuit card with interstitial surface mounted components. In an example, the circuit card includes a first surface; a second surface opposite the first surface; and an array of pads disposed on the first surface. The pads are configured to provide electrical coupling of the circuit card to a ball grid array of an electronic device. The circuit card also includes one or more interstitial electrical components mounted between the pads of the array on the first surface of the circuit card. The circuit card further includes one or more additional electrical components mounted on the second surface of the circuit card and on the first surface of the circuit card outside of a region comprising the array of pads. The electrical components may include capacitors, bypass capacitors, inductors, and / or resistors. The electronic device may be an integrated circuit or a field programmable gate array.

The invention provides a laminated packaging method for an integrated circuit. The laminated packaging method comprises the following steps: step 1, laminating; step 2, cutting a single particle; step 3, electroplating; 4, etching is carried out; step 5, ball grid array (BGA) ball mounting; according to the integrated circuit stack packaging method, a plurality of integrated circuits of the same model are packaged in a stack mode, when the plurality of same integrated circuits are used in parallel, only one-time welding is needed, welding spots are reduced, and therefore the service life and reliability risks caused by welding quality are greatly reduced. Meanwhile, due to lamination packaging and stacking of a plurality of integrated circuits, the requirement for the area of the PCB is reduced, the whole PCBA can be miniaturized, the overall size and weight are reduced, the use field of the PCBA can be expanded, and space is provided for function expansion or miniaturization of the whole equipment.

Method for applying double-sided reinforcing (DSR) material to a fixture during an assembly process, the method comprising: Printing solder paste material onto a substrate of a printed circuit board; Mounting a ball grid array device with a pick-and-place machine; Immersion of the device in a pressure flux package-on-package (PoP) machine; Arrange the device on a solder paste pad on the substrate; Applying heat to the substrate to remelt the device in order to attach the device to the substrate; and Filling a gap between the device and the substrate with curable DSR material; wherein the DSR material comprises epoxy and curing agent; and wherein the combination of epoxy and curing agent triggers a crosslinking reaction only at elevated temperatures once the solder melts.

The invention belongs to the technical field of glass substrates, and particularly relates to a preparation method of a high-drawing-strength glass substrate BGA bonding pad. A substrate is selected as a glass substrate, a BGA bonding pad needs to be manufactured on the glass substrate, a photosensitive film covers or coats the substrate to form a photosensitive layer, patterns are exposed on the photosensitive layer, the patterns are circular rings and disks, the disks arranged regularly are designed in the BGA bonding pad area outside the circular rings, development and chemical etching are carried out after exposure, the circular rings and the disks are sunken and sunken, and the BGA bonding pad is formed. Respectively forming a micro circular ring and a micro circular disc, and removing the residual photosensitive layer to obtain a substrate after film stripping; and carrying out plasma treatment on the stripped substrate, printing conductive slurry, curing to form a coating, and carrying out post-treatment to obtain the glass substrate BGA bonding pad with high drawing strength. According to the invention, the binding force between the coating and the glass substrate is improved, thermal stress is not easy to generate, and the cost is reduced.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

The invention discloses an optical phased array chip based on silicon through hole interconnection and ball grid array packaging, which comprises a silicon adapter plate and a PCB (Printed Circuit Board) which are arranged in an up-and-down layered manner, a silicon-based optical phased array is provided with a plurality of phase control electrodes, a silicon through hole array is vertically arranged in the silicon adapter plate, and a plurality of phase control electrodes are arranged in the silicon through hole array. The through silicon via array comprises a single through silicon via, a plurality of groups of first through silicon via pairs and a plurality of groups of second through silicon via pairs, a plurality of groups of switching wire pairs are arranged on the PCB, and the lower end of each group of first through silicon via pair is connected with the first wiring end of the corresponding switching wire pair; the second wiring end of each group of switching wire pair is connected with the lower end of the corresponding second silicon through hole pair, the upper end of each group of first silicon through hole pair is used for being connected with a phase output terminal pair of an electrode control circuit, and the upper end of each group of second silicon through hole pair is used for being connected with the two ends of a phase control electrode. Through the silicon through hole and ball grid array packaging technology, the photoelectric co-packaging type optical phased array chip is realized, and higher-density function integration is realized.

To provide a flux that has excellent water-cleanability for flux residue and can suppress the occurrence of head-in-pillow defects called HiP (Head in Pillow) in the mounting of BGA (Ball Grid Array), CSP (Chip Size Package), etc., and a solder paste containing the flux. SOLUTION: A water-cleanable flux is employed, which contains a water-soluble base agent selected from nonionic surfactants, an organic acid, and a solvent, and the organic acid includes a dimer acid and an organic sulfonic acid.

The utility model discloses a fiber coiling tool for fixing optical fibers of a ball grid array optical assembly, which comprises a tool body and the optical assembly with the optical fibers, the optical assembly is adhered on the tool body, the tool body adopts polyether-ether-ketone engineering plastics, the tool body comprises a base and an extending part, the extending part is arranged on the side wall of the base, and the extending part is arranged on the side wall of the base. A bonding part of the optical assembly is arranged below the base, a coiling shaft is arranged above the base, an extending part is provided with a turning groove used for turning an optical fiber by 180 degrees, and the extending part is further provided with an end fixing hole of the optical fiber; the optical component coiling tool has the advantages that the bonding part is matched with the coiling shaft, so that connection between the tool body and the optical component can be realized, light is coiled and pre-fixed and is fixed through the end fixing holes, and subsequent technological processes can be conveniently carried out; the direction changing groove can enable the optical fiber to realize 180-degree direction changing, so that the optical fiber can be coiled and pre-fixed conveniently; the tool body is made of polyether-ether-ketone engineering plastic materials and can be used for a long time at the temperature of 250 DEG C, and the problem of high-temperature-resistant reflow soldering is solved.

The invention relates to the technical field of intelligent detection, and discloses a visual quality inspection method and system for a BGA chip, and the method comprises the steps: irradiating the BGA chip through a multispectral light source array, and obtaining an initial reflection image of the BGA chip; based on geometric distribution characteristics of the solder balls in the chip, performing region segmentation on the initial reflection image to obtain independent imaging regions of the solder balls; collecting multi-view difference images of the same solder ball area in the independent imaging area, and fusing the multi-view difference images into a three-dimensional topological graph; separating a deformation characteristic graph of the solder ball in the three-dimensional topological graph, and applying a virtual thermal stress field to the deformation characteristic graph to obtain a thermal expansion coefficient distribution cloud graph of the solder ball; marking abnormal solder ball coordinates in the BGA chip according to a comparison result of the thermal expansion coefficient distribution cloud picture and a standard threshold interval; generating a quality inspection report of the BGA chip according to the abnormal solder ball coordinates and the thermal expansion coefficient distribution cloud picture; according to the invention, the accuracy of visual quality inspection of the BGA chip can be improved.

The utility model relates to the field of ball grid array packaging, in particular to a ball grid array packaging ball mounting jig which comprises a clamp base and an upper die, the clamp base comprises a base table and a chip table, the chip table is fixed at the upper end of the base table, a chip groove is formed in the middle of the chip table, and the upper die comprises a frame body, a steel mesh and a transparent cover plate. The frame body is connected to the upper end of the base table in a clamped mode, a groove is formed in the upper end of the frame body, a first magnetic attraction strip is embedded in the groove, second magnetic attraction strips magnetically connected with the first magnetic attraction strip are fixed to the two sides of the transparent cover plate, the transparent cover plate is arranged in the groove, and the steel mesh is arranged at the lower end of the frame body. The lower end face of the steel mesh is in contact with the upper end face of the chip table, tin balls cannot fall out due to the existence of the transparent cover plate, meanwhile, the condition of the tin balls can be observed through the transparent cover plate, the structure is simple, and the risk problem that the tin balls fall out is effectively solved.

The utility model relates to computer technology field, concretely relates to a DDR memory slot maintenance device, including frame, the frame is equipped with maintenance platform, the frame is equipped with upper heating air gun at the top of maintenance platform, the frame is equipped with lower heating air gun at the bottom of maintenance platform, upper heating air gun and lower heating air gun are opposite setting, the frame is equipped with left guide strip and right guide strip, left guide strip is equipped with left limit block, right guide strip is equipped with right limit block. The utility model in the light of the ball grid array package characteristics of DDR memory slot, through the opposite setting of upper heating air gun and lower heating air gun, realize the synchronous heating of DDR memory slot upper and lower two sides, solved the problem that traditional tin melting furnace cannot adapt to this structure, in addition the temperature and range of upper heating air gun and lower heating air gun can be accurate control, avoid partial overheating to lead to computer mainboard other sensitive element damage, reduce the maintenance risk.

A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit and the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.

Semiconductor devices, packages, and structures are described. A semiconductor structure can include a plurality of BGA pads, where a plurality of BGA balls are attached to a first surface of the plurality of BGA pads. The semiconductor structure can further include a layer of dielectrics deposited on a second surface of the plurality of BGA pads. The second surface can be opposite from the first surface. The semiconductor structure can further include at least one floating structure deposited on the layer of dielectrics. The at least one floating structure and at least two of the plurality of BGA pads can form at least two capacitors that are connected within the interposer.

The invention discloses a method and a system for detecting a BGA (Ball Grid Array) device. The method and the system are used for detecting surface defects of solder balls in the BGA device. Obtaining an initial detection range of the to-be-detected BGA device according to the real-time image of the to-be-detected BGA device, and further obtaining an actual detection range of the to-be-detected BGA device; obtaining a detection area of each solder ball according to the actual detection range; a plurality of regions of interest in the detection region of each solder ball are obtained so as to carry out solder ball defect detection on the solder ball, and the solder ball defect detection comprises contrast detection and solder ball quality detection; wherein a contrast detection result is obtained according to the representative point of each region of interest; and according to the bad pixel points in each region of interest of each solder ball, obtaining the solder ball quality tolerance of the region of interest, and further obtaining a solder ball quality detection result. According to the method, each solder ball is divided into a plurality of regions of interest, and through extraction of representative points in each region of interest and identification of bad pixel points, rapid detection of complex defects on the surface of the solder ball is realized.