368 results about "Ball grid array" patented technology

The invention provides a low-warpage underfill adhesive for FC-BGA packaging, a preparation method thereof and a flip chip. The underfill adhesive comprises the following components in percentage by mass: 50%-60% of silicon dioxide, 24%-29% of epoxy resin, 16%-20% of a curing agent, 0.1%-0.2% of carbon black and 0.1%-0.2% of an accelerant. Wherein the epoxy resin is composed of high-purity bisphenol A epoxy resin, polyurethane modified epoxy resin and phenolic aldehyde modified epoxy resin. By adjusting the proportion of the high-purity bisphenol A epoxy resin, the polyurethane modified epoxy resin and the phenolic aldehyde modified epoxy resin and combining the curing agent and the accelerant, the stress of the underfill adhesive is integrally reduced, and the underfill adhesive with good fluidity and low warpage is obtained; therefore, the packaging yield and the packaging efficiency of chip packaging are improved.

The invention discloses a board-level fan-out type packaging structure and a preparation method thereof, the board-level fan-out type packaging structure comprises a first passivation layer, a chip or a rimless device is inversely arranged on the first passivation layer, the chip or the rimless device and the first passivation layer are externally coated with a plastic packaging layer, a first rewiring layer is arranged on the first passivation layer, a rewiring structure is arranged on the first rewiring layer, and a second rewiring layer is arranged on the second passivation layer. And a ball grid array structure for external interconnection is arranged on the rewiring structure. According to the invention, the forming step of the first passivation layer is advanced before the flip mounting of the chip or the passive device, and the chip or the passive device is firmly fixed by using the adhesion of the first passivation layer, so that additional auxiliary adhesive materials or process steps such as dispensing in the prior art can be replaced, the offset problem of the chip or the passive device is solved, and the production efficiency is improved. And no new process step is introduced, the product production cycle is not influenced, the product yield is guaranteed, the cost is low, and the method is suitable for industrial popularization and application.

The invention relates to the technical field of welding, in particular to an automatic laser solder ball welding method and related equipment for a ball grid array packaging chip, and the method comprises the steps: obtaining a target coordinate of a nozzle corresponding to a nozzle welding position; judging whether the target coordinate meets a preset coordinate requirement or not; if the target coordinate meets the preset coordinate requirement, whether the nozzle welding height needs to be calculated or not is judged; if the welding height of the nozzle needs to be calculated, the welding height of the nozzle is obtained, and the nozzle is lowered to the welding height of the nozzle; based on the target coordinate, controlling the solder ball to fall into a nozzle, and controlling a laser to emit light for welding; judging whether the welding result meets a preset welding requirement or not; and if the welding result meets the preset welding requirement, the current welding process is ended. According to the invention, the welding effect can be improved.

The invention discloses a broadband multi-level three-dimensional vertical interconnection structure based on an HTCC technology, and belongs to the field of radio frequency front-end system integration. The structure comprises a PCB mother board, a ball grid array and an SiP module which are sequentially arranged from bottom to top, in the SiP module, the chips are distributed among different levels, and a connection mode of the chips among the different levels is set; a radio frequency signal is transmitted upwards through the PCB mother board, and after flowing through the lower-layer bare chip, the radio frequency signal is orderly transmitted upwards through the strip line and the signal via hole in the HTCC and finally transmitted to the surface-layer chip, so that a complete and efficient vertical interconnection signal transmission system is formed. According to the invention, the layout flexibility of interconnection lines among the chips is improved, the wiring crosstalk among the chips is reduced, the three-dimensional integration scene of bare chips in the HTCC is greatly widened, high-density SiP packaging is realized, and the strict technical requirements on radio frequency signal transmission, processing and chip interconnection under a complex circuit architecture can be met.

Methods and apparatus for implementing an arrangement of antennas in an apparatus are described. The combining of antennas and related components using Ball Grid Array (BGA) technology and various spacing / heat routing techniques allows for a group of antennas and related ICs to be implemented as a printed circuit board mountable package. Multiple antenna packages can be mounted on a printed circuit board to allow for different numbers of antennas to be included in a device depending on communications needs. The antenna package is well suited for mm-wave applications.

The invention discloses an automatic detection system and method for BGA packaging circuit quality, and the method comprises the steps: randomly selecting X BGA packaging circuits from a qualified workshop as evaluation samples for thermal performance detection, and carrying out the detection and analysis of the thermal performance parameters of each evaluation sample, obtaining a thermal performance evaluation index of the BGA packaging circuit of the current production batch, and presetting three groups of index value ranges corresponding to the thermal performance evaluation index Gtr; and matching the thermal performance evaluation index of the BGA packaging circuit of the current production batch with the preset three groups of index value ranges, thereby obtaining the thermal performance grade of the BGA packaging circuit of the current production batch, and solving the problems that in the prior art, when quality detection is carried out on the BGA packaging circuit, evaluation on the thermal performance of the BGA packaging circuit is lacked, and the quality detection efficiency is poor. Therefore, the problem of quality detection singleness is solved.

The invention relates to the technical field of solder ball array optimization, in particular to a low-warpage solder ball array optimization method and system in FC-BGA packaging of a glass substrate, and the method comprises the steps: determining the glass substrate and a plurality of solder balls, designing a preliminary array layout, creating a three-dimensional geometric model, carrying out the thermal loading simulation of the three-dimensional geometric model, and obtaining a plurality of thermal stress distribution nephograms; and executing the following operations on each thermal stress distribution cloud picture in the plurality of thermal stress distribution cloud pictures: obtaining a maximum thermal stress region from the thermal stress distribution cloud picture, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout, summarizing the optimal array layout, and obtaining the thermal stress distribution cloud picture. A plurality of thermal stress distribution cloud pictures are obtained, a plurality of optimal array layouts corresponding to the thermal stress distribution cloud pictures are obtained, the optimal array layout is obtained, the voidage of the welding spots is calculated based on the optimal array layout, and optimization of the low-warpage welding ball array in FC-BGA packaging of the glass substrate is completed based on the voidage of the welding spots. According to the invention, the optimization precision and efficiency of the solder ball layout can be improved.

The invention discloses a packaging structure and a packaging method of a SiP module based on a ceramic material, the packaging structure takes the ceramic material as a packaging shell, the position of a substrate part of the shell is designed to be a concave staggered layer structure, so that the assembly of chips and passive devices with different sizes and different heights is facilitated, and because the internal circuit of the SiP module is complicated and the number of interface pins is large, the packaging cost is low. Therefore, a ball grid array pin mode is adopted outside the shell, a metallization layout design is carried out on the ceramic substrate to realize chip assembly bonding pad and partial circuit wiring, and meanwhile, through hole metallization slurry filling is designed between substrates to realize connection of an internal metallization bonding pad and an external ball grid array pin. And a specific chip and a passive device are assembled at different positions, and lead bonding interconnection is assisted, so that a complete packaging process of a specific circuit SiP module is realized. The power distribution cabinet has the advantages of being good in insulation performance, ultrahigh in integration level, ultra-light in weight, fast in heat dissipation, high in reliability and the like, and has very high popularization value.

The invention provides an improved YOLOv10-based solder ball defect detection method for a BGA packaged chip, and the method comprises the steps: collecting a solder ball image of the BGA packaged chip, carrying out the morphological preprocessing, and carrying out the analysis and classification of defects; carrying out defect generation on solder ball burr defects with less data; performing similarity measurement on the generated defects and the real defects, and selecting defect data with relatively high similarity to construct a pre-training data set; a YOLOv10 deep learning network is improved, a C2f module in the network is improved, an up-sampling module is replaced with a lightweight dynamic up-sampling operator DySample, an original loss function is replaced with a Focal-EIoU loss function, the improved network is used for pre-training, and a defect detection model is obtained; performing real-time defect detection on the solder ball of the BGA packaging chip by using the defect detection model to obtain defect information; according to the invention, the detection precision and speed of the solder ball defect of the BGA packaging chip are effectively improved.

The invention provides a wafer-level layering failure analysis and sample preparation method of a chip, which comprises the following steps of: preprocessing a chip sample, positioning crystal grains, grinding and thinning according to the plane projection of the crystal grains to carry out primary processing, cutting a target sample, continuously carrying out plane grinding to remove a ball grid array (BGA) solder ball, and preparing the wafer-level layering failure analysis and sample preparation method of the wafer-level layering failure analysis and sample preparation method of the chip. The method comprises the following steps of: adding the raw materials into a first chemical reagent, a second chemical reagent and a third chemical reagent in sequence to react so as to release the residual stress of the packaging structure to the greatest extent, reduce the damage to failure morphology in a sample preparation process and obtain separated bare crystal grains, and finally scanning and analyzing the bare crystal grains by using an ultrasonic acoustic microscope. The method is used for determining whether the advanced technology chip has potential poor layering of the low-dielectric-constant insulating layer and determining the specific position of the poor layering. According to the invention, the technical problem of sample damage caused by external stress in the analysis process can be effectively improved, and subsequent accurate focused ion beam FIB and other physical destructive analysis can be conveniently carried out on the failure position.

A chip package includes a ball-grid-array (BGA) substrate; a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin; a field programmable chip package over and coupling to the ball-grid-array (BGA) substrate, wherein the field programmable chip package comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip therein and a second metal bump at a bottom of the field programmable chip package and bonded to a top of the ball-grid-array (BGA) substrate; and a memory chip package under and coupling to the ball-grid-array (BGA) substrate, wherein the memory chip package comprises a first non-volatile memory (NVM) integrated-circuit (IC) chip therein and a third metal bump at a top of the memory chip package and bonded to the bottom of the ball-grid-array (BGA) substrate.

The invention relates to the technical field of communication, and relates to a high-integration airtight packaging phased-array antenna and a preparation method thereof. Comprising an HTCC antenna, a kovar enclosure frame, an HTCC control panel and a heat dissipation enclosure frame, the HTCC antenna is connected with the HTCC control panel through the metal ball grid array; the radio frequency chip is installed on the HTCC antenna through the metal ball grid array and is connected with the HTCC control board through the metal ball grid array. A low-frequency connector is integrated on the HTCC control board; the radio frequency chip is in contact with the HTCC control panel through a fuzz button spring needle; the fuzz button spring needle is welded on the heat dissipation enclosure frame; the HTCC antenna, the HTCC control panel and the kovar enclosure frame are welded through a first soldering lug; and the HTCC antenna is welded with the heat dissipation enclosure frame through a second soldering lug. According to the invention, high integration level, miniaturization and high reliability of the antenna are realized, and the antenna can stably work for a long time in severe environments such as salt mist, damp and hot environments and the like.

The invention discloses a ball grid array package solder ball injection device and an application method, which belongs to the field of microelectronic packaging, solder ball preparation and circuit printing, and includes a power system, a heat dissipation bracket, a crucible mechanism, a heating device, a nozzle, an inert gas supply system and a signal generating unit; the power system is used to drive the nozzle to reciprocate up and down, including a piezoelectric ceramic stack and a striker, the striker is fixedly connected to the nozzle, the signal generating unit includes a signal generator and a power amplifier, which is used to drive the piezoelectric ceramic stack to expand and contract, and then drive the nozzle to move up and down quickly; the crucible mechanism and the heating device are used to heat and melt the solder wire in the crucible; the heat dissipation bracket is used to reduce the heat transferred to the power system; the inert gas supply system is used to make the high-temperature liquid solder droplets ejected from the nozzle in an inert gas environment to prevent the high-temperature liquid solder droplets from oxidizing. The invention has various functions, is easy to use, has low cost and high reliability.

The invention discloses BGA (Ball Grid Array) packaging intelligent wobble plate equipment, which comprises a rack, and is characterized in that the rack is provided with a loading station, a feeding station, a loading station, an overturning station, a stacking station and a discharging station; the feeding frame is arranged on the feeding station, and a feeding driving mechanism is arranged on the feeding frame; the stacking box is arranged at the discharging station, and a discharging driving mechanism is arranged on the rack; the clamping and transferring mechanism is used for clamping and transferring a loading template from a stacking box to the loading station or clamping and transferring a packaged finished product from the loading station to the stacking box for stacking treatment, and the overturning station is located on a transferring path of the clamping and transferring mechanism; the loading mechanism is arranged at the loading station; and the turnover mechanism is arranged at the turnover station, a turnover space is formed between the turnover mechanism and the clamping and transferring mechanism, and a jacking driving mechanism is arranged on the rack. According to the automatic tray placing and overturning device, automatic tray placing and overturning operation is achieved, and the production efficiency is effectively improved.

The invention discloses a BGA (Ball Grid Array) area flatness PCB (Printed Circuit Board) and a preparation method thereof in the technical field of PCB production processes, and aims to solve the problem that the flatness cannot meet the actual production requirement in the prior art. The preparation method comprises the following steps: obtaining a carrier, a prepreg and a peelable copper foil; sequentially laminating the carrier, the prepreg and the peelable copper foil to form an upper, middle and lower laminated structure; laminating and pre-curing the upper, middle and lower laminated structure by adopting a laminating machine to form a false layer; laminating the false layer with a preset inner-layer core plate, a press steel plate and a buffer material to form a multi-layer PCB structure; and stripping the strippable copper foil from the multi-layer PCB structure, and removing the false layer to obtain the BGA area PCB with the preset flatness. According to the method, the flatness range of the BGA area can be controlled within 50 # imgabs0 #.

The invention provides automatic laser solder ball welding equipment for a ball grid array packaging chip, two jig driving assemblies are mounted on a mounting platform, and two chip jigs are mounted on the two jig driving assemblies respectively and move along a first direction under the driving of the jig driving assemblies. The welding device is installed on the welding driving assembly and driven by the welding driving assembly to move in the second direction. The detection driving assembly is installed on the installation platform, and the positioning assembly and the detection assembly are both installed on the detection driving assembly and are driven by the detection driving assembly to move in the second direction or the third direction. According to the automatic laser solder ball welding equipment for the ball grid array packaging chip, welding and detection can be synchronously carried out through the two jig driving assemblies and the two chip jigs, and compared with the related technology, continuous welding can be carried out, the welding efficiency is greatly improved, and the automation degree is high.

The differential via hole structure comprises at least one differential group, the differential group comprises a first differential pair and a second differential pair, a first connecting line of two differential via holes in the first differential pair is perpendicular to a second connecting line of two differential via holes in the second differential pair, and one differential via hole in the first differential pair is located on the second connecting line; according to the embodiment of the invention, the two differential pairs in one differential group are vertically arranged, and one differential pair is located on the vertical line, passing through one differential via hole, of the other differential pair, so that the differential crosstalk can be reduced, the system margin can be improved, and the signal integrity of a link can be improved on the premise of not influencing the straight-through bandwidth. The invention further provides a solder ball array packaging assembly, a printed circuit board and communication equipment.

The invention discloses a BGA packaging defect detection method and system based on deep learning. The method comprises the steps that a to-be-detected image of a to-be-detected ball grid array chip is acquired; reasoning the to-be-detected image by adopting a first deep learning model so as to identify and position key components on each to-be-detected ball grid array chip; carrying out anomaly detection on the geometric parameters of the key component to obtain a geometric parameter detection result; carrying out surface defect detection on the to-be-detected image in parallel by adopting a second deep learning model group so as to identify various surface defects on the surface of the substrate of the to-be-detected ball grid array chip, and obtaining a surface defect detection result; and determining a defect detection result of the to-be-detected ball grid array chip based on the geometric parameter detection result and the surface defect detection result, thereby realizing a self-adaptive, high-beat and comprehensive BGA packaging defect detection method.

Example implementations described herein involve a media adaptor configured to provide electrical / optical and optical / electrical conversion for a multi-mode waveguide (MMWG) interconnect, the media adaptor involving one or more ball grid arrays; and a tail-cut fiber array block (tcFAB) connected to a first array of photodiodes and a second array of laser diodes from direct optical wire (DOW) bonding.

The invention provides an automatic testing system and method for a BGA packaging assembly, and relates to the field of radar assembly testing. According to the invention, the automatic test system comprises a component test system and an automatic screening system which are in communication connection, and is used for cooperatively completing component test work. The component testing system is connected with the workshop MES system, information such as component testing index requirements and measuring instrument configuration parameters is obtained, instruments and meters are autonomously controlled to complete testing tasks for different components, and the accuracy is high; meanwhile, the automatic screening system efficiently completes the operations of picking and placing the components before and after packaging by adopting devices such as machine vision identification and positioning, high-precision motion control and a flexible picking and placing module, so that the labor burden is reduced. In addition, a network cooperation test scheme of the assembly test system and the automatic screening system further meets high-efficiency and high-accuracy test requirements of different types of radar transmit-receive assemblies, and is very suitable for a multi-variety to batch production mode of the phased array radar transmit-receive assemblies.

The invention discloses a high-flatness BGA (Ball Grid Array) circuit board and a manufacturing method thereof. The high-flatness BGA circuit board comprises a plurality of layers of circuit carriers, a glass plate is attached between the first layer and the second layer of the multi-layer circuit carrier through an adhesive material; a through hole is formed in the glass plate, and a bonding material is injected into the through hole; and a plated-through hole is formed in the adhesive material in the through hole and is communicated with the first layer and the second layer of the multi-layer circuit carrier. According to the invention, the glass plate is installed between the first layer and the second layer of the multi-layer circuit carrier through the bonding material, so that the surface flatness problem of the HDI and the multi-layer circuit board is solved; the metalized layers of the through holes in the glass and the metalized holes in the metalized layers form a signal net-shaped shielding layer similar to a coaxial cable, a central conductor and an inner insulating layer, so that when signals are transmitted, electromagnetic interference is resisted, signal quality is kept, and signal loss is reduced.

A semiconductor structure, a fabricating method thereof, and a chip packing structure are provided. The disclosed semiconductor structure includes a printed circuit board, a chip packing structure, and a ball grid array connected between the printed circuit board and the chip packing structure. The ball grid array includes first solder balls each having a first lateral size, and second solder balls each having a second lateral size greater than the first lateral size. The second solder balls are located at corners of the ball grid array, respectively.

An electronic device including an IC having a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the IC package. The IC package includes a substrate comprising an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The pillar has a top surface and a bottom surface. The pillar extends through the package mold layer with the top surface coupled to the metal pad and the bottom surface coupled to the solder cap. In contrast to conventional package interconnects, such as ball grid arrays (BGA), for example, deploying the solder cap on the bottom surface of the pillar advantageously results in using less solder and tighter pitch between adjacent package interconnects because the width of the pillar is less than a solder ball in a BGA.

The invention discloses a W-band airtight multistage transition structure based on an HTCC. The W-band airtight multistage transition structure comprises a WR-10 waveguide, an FR-4 substrate, a ball grid array, a multistage vertical SIW, a quarter-wave short road surface and a planar transmission structure. An FR-4 substrate is arranged above the WR-10 waveguide, an FR-4 substrate air cavity is formed after cavity digging and side wall metallization are carried out in the FR-4 substrate, and the size of the WR-10 waveguide is the same as that of the FR-4 substrate air cavity. A ball grid array is distributed above the FR-4 substrate, and the ball grid array is distributed around the air cavity of the FR-4 substrate. The multi-stage vertical SIW is arranged above the ball grid array, and the impedance matching effect is achieved through multi-stage gradual change. The quarter-wave short road surface and the planar transmission structure are placed on the multi-stage vertical SIW, and electromagnetic energy is coupled to the microstrip line.

The invention discloses a semiconductor packaging structure and a manufacturing method thereof. The semiconductor package structure includes a substrate having a top side and a bottom side; the first ball grid array is arranged on the bottom side of the substrate, the first ball grid array is provided with a plurality of first balls, and the first ball grid array has a signal connection function between the substrate and an external printed circuit board; and the second ball grid array is arranged on the bottom side of the substrate, the second ball grid array is provided with a plurality of second balls, and the second balls are arranged in transverse gaps among the first balls on the bottom side.

An electronic apparatus includes an integrated circuit board on, over, or in which a USB circuit block is provided; a first USB interface; a second USB interface; a printed circuit board on which a source clock circuit configured to output a source clock is provided; and a ball grid array that includes first, second, and third ball grids for electric coupling between the integrated circuit board and the printed circuit board. The first ball grid electrically couples the USB circuit block and the first USB interface to each other. The second ball grid electrically couples the USB circuit block and the second USB interface to each other. The third ball grid electrically couples the source clock circuit and the USB circuit block to each other. The third ball grid is located between the first ball grid and the second ball grid.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

A method of manufacturing a printed circuit board (PCB) includes arranging a first trace segment of a trace on a substrate of the PCB, the substrate being composed of fiber glass strands that define a fiber glass weave pattern, and arranging a second trace segment of the trace on the substrate at a position that is fractionally offset from the first trace segment along an axis by a distance that is less than a ball grid array (BGA) pitch of a BGA based on the fiber glass weave pattern. The BGA pitch is a separation distance along the axis between a center of a first via of the BGA of the PCB and a center of a second via of the BGA.

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Provided is a laminate having high adhesion to a metal layer. Further provided are a laminated board, a printed wiring board, a semiconductor package, an interposer, and a ball grid array (BGA) substrate that are obtained using the laminate. The laminate includes a glass substrate having a through-hole, and has a layer of a resin composition on a surface of the glass substrate and a side wall of the through-hole. The resin composition contains (A) an epoxy resin having a biphenyl-diyl group and (B) an ester-based curing agent. The content of the component (A) is 10-80 mass% with respect to the total amount of the resin component.