195 results about "Ball grid array" patented technology

The invention relates to the technical field of solder ball array optimization, in particular to a low-warpage solder ball array optimization method and system in FC-BGA packaging of a glass substrate, and the method comprises the steps: determining the glass substrate and a plurality of solder balls, designing a preliminary array layout, creating a three-dimensional geometric model, carrying out the thermal loading simulation of the three-dimensional geometric model, and obtaining a plurality of thermal stress distribution nephograms; and executing the following operations on each thermal stress distribution cloud picture in the plurality of thermal stress distribution cloud pictures: obtaining a maximum thermal stress region from the thermal stress distribution cloud picture, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout, summarizing the optimal array layout, and obtaining the thermal stress distribution cloud picture. A plurality of thermal stress distribution cloud pictures are obtained, a plurality of optimal array layouts corresponding to the thermal stress distribution cloud pictures are obtained, the optimal array layout is obtained, the voidage of the welding spots is calculated based on the optimal array layout, and optimization of the low-warpage welding ball array in FC-BGA packaging of the glass substrate is completed based on the voidage of the welding spots. According to the invention, the optimization precision and efficiency of the solder ball layout can be improved.

The invention discloses a packaging structure and a packaging method of a SiP module based on a ceramic material, the packaging structure takes the ceramic material as a packaging shell, the position of a substrate part of the shell is designed to be a concave staggered layer structure, so that the assembly of chips and passive devices with different sizes and different heights is facilitated, and because the internal circuit of the SiP module is complicated and the number of interface pins is large, the packaging cost is low. Therefore, a ball grid array pin mode is adopted outside the shell, a metallization layout design is carried out on the ceramic substrate to realize chip assembly bonding pad and partial circuit wiring, and meanwhile, through hole metallization slurry filling is designed between substrates to realize connection of an internal metallization bonding pad and an external ball grid array pin. And a specific chip and a passive device are assembled at different positions, and lead bonding interconnection is assisted, so that a complete packaging process of a specific circuit SiP module is realized. The power distribution cabinet has the advantages of being good in insulation performance, ultrahigh in integration level, ultra-light in weight, fast in heat dissipation, high in reliability and the like, and has very high popularization value.

A chip package includes a ball-grid-array (BGA) substrate; a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin; a field programmable chip package over and coupling to the ball-grid-array (BGA) substrate, wherein the field programmable chip package comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip therein and a second metal bump at a bottom of the field programmable chip package and bonded to a top of the ball-grid-array (BGA) substrate; and a memory chip package under and coupling to the ball-grid-array (BGA) substrate, wherein the memory chip package comprises a first non-volatile memory (NVM) integrated-circuit (IC) chip therein and a third metal bump at a top of the memory chip package and bonded to the bottom of the ball-grid-array (BGA) substrate.

The invention discloses BGA (Ball Grid Array) packaging intelligent wobble plate equipment, which comprises a rack, and is characterized in that the rack is provided with a loading station, a feeding station, a loading station, an overturning station, a stacking station and a discharging station; the feeding frame is arranged on the feeding station, and a feeding driving mechanism is arranged on the feeding frame; the stacking box is arranged at the discharging station, and a discharging driving mechanism is arranged on the rack; the clamping and transferring mechanism is used for clamping and transferring a loading template from a stacking box to the loading station or clamping and transferring a packaged finished product from the loading station to the stacking box for stacking treatment, and the overturning station is located on a transferring path of the clamping and transferring mechanism; the loading mechanism is arranged at the loading station; and the turnover mechanism is arranged at the turnover station, a turnover space is formed between the turnover mechanism and the clamping and transferring mechanism, and a jacking driving mechanism is arranged on the rack. According to the automatic tray placing and overturning device, automatic tray placing and overturning operation is achieved, and the production efficiency is effectively improved.

The differential via hole structure comprises at least one differential group, the differential group comprises a first differential pair and a second differential pair, a first connecting line of two differential via holes in the first differential pair is perpendicular to a second connecting line of two differential via holes in the second differential pair, and one differential via hole in the first differential pair is located on the second connecting line; according to the embodiment of the invention, the two differential pairs in one differential group are vertically arranged, and one differential pair is located on the vertical line, passing through one differential via hole, of the other differential pair, so that the differential crosstalk can be reduced, the system margin can be improved, and the signal integrity of a link can be improved on the premise of not influencing the straight-through bandwidth. The invention further provides a solder ball array packaging assembly, a printed circuit board and communication equipment.

The invention discloses a BGA packaging defect detection method and system based on deep learning. The method comprises the steps that a to-be-detected image of a to-be-detected ball grid array chip is acquired; reasoning the to-be-detected image by adopting a first deep learning model so as to identify and position key components on each to-be-detected ball grid array chip; carrying out anomaly detection on the geometric parameters of the key component to obtain a geometric parameter detection result; carrying out surface defect detection on the to-be-detected image in parallel by adopting a second deep learning model group so as to identify various surface defects on the surface of the substrate of the to-be-detected ball grid array chip, and obtaining a surface defect detection result; and determining a defect detection result of the to-be-detected ball grid array chip based on the geometric parameter detection result and the surface defect detection result, thereby realizing a self-adaptive, high-beat and comprehensive BGA packaging defect detection method.

An electronic device including an IC having a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the IC package. The IC package includes a substrate comprising an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The pillar has a top surface and a bottom surface. The pillar extends through the package mold layer with the top surface coupled to the metal pad and the bottom surface coupled to the solder cap. In contrast to conventional package interconnects, such as ball grid arrays (BGA), for example, deploying the solder cap on the bottom surface of the pillar advantageously results in using less solder and tighter pitch between adjacent package interconnects because the width of the pillar is less than a solder ball in a BGA.

The invention discloses a W-band airtight multistage transition structure based on an HTCC. The W-band airtight multistage transition structure comprises a WR-10 waveguide, an FR-4 substrate, a ball grid array, a multistage vertical SIW, a quarter-wave short road surface and a planar transmission structure. An FR-4 substrate is arranged above the WR-10 waveguide, an FR-4 substrate air cavity is formed after cavity digging and side wall metallization are carried out in the FR-4 substrate, and the size of the WR-10 waveguide is the same as that of the FR-4 substrate air cavity. A ball grid array is distributed above the FR-4 substrate, and the ball grid array is distributed around the air cavity of the FR-4 substrate. The multi-stage vertical SIW is arranged above the ball grid array, and the impedance matching effect is achieved through multi-stage gradual change. The quarter-wave short road surface and the planar transmission structure are placed on the multi-stage vertical SIW, and electromagnetic energy is coupled to the microstrip line.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

A method of manufacturing a printed circuit board (PCB) includes arranging a first trace segment of a trace on a substrate of the PCB, the substrate being composed of fiber glass strands that define a fiber glass weave pattern, and arranging a second trace segment of the trace on the substrate at a position that is fractionally offset from the first trace segment along an axis by a distance that is less than a ball grid array (BGA) pitch of a BGA based on the fiber glass weave pattern. The BGA pitch is a separation distance along the axis between a center of a first via of the BGA of the PCB and a center of a second via of the BGA.

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Provided is a laminate having high adhesion to a metal layer. Further provided are a laminated board, a printed wiring board, a semiconductor package, an interposer, and a ball grid array (BGA) substrate that are obtained using the laminate. The laminate includes a glass substrate having a through-hole, and has a layer of a resin composition on a surface of the glass substrate and a side wall of the through-hole. The resin composition contains (A) an epoxy resin having a biphenyl-diyl group and (B) an ester-based curing agent. The content of the component (A) is 10-80 mass% with respect to the total amount of the resin component.

To improve signal loss in ball grid array (BGA) waveguide interfaces.SOLUTION: A package-waveguide interface 300 includes a package substrate 320 that encapsulates solder balls 314, 318 and an integrated circuit die 305 and that includes signal transmitters 325, 330 that transmit or receive signals on the surface of the package substrate. A BGA includes a set of grounded solder balls arranged as a boundary around the signal transmitters. The interface further includes a printed circuit board (PCB) 310 having a waveguide interface side opposite a secondary waveguide side (3D antenna 360 side), and PCB through-holes 345, 350 that extend from the waveguide interface side to the secondary waveguide side and are perpendicular to the plane of the PCB. The BGA couples the package substrate to the waveguide interface side such that the surface of the package substrate faces the PCB through-holes and the signal transmitters and the PCB through-holes are substantially aligned.SELECTED DRAWING: Figure 3

A ball grid array package according to an embodiment of the present invention comprises: a first circuit board; the second circuit board is arranged above the first circuit board; a first solder ball and a second solder ball disposed between the first circuit board and the second circuit board so as to be spaced apart from each other; a first adhesive disposed between the first circuit board and the second circuit board so as to extend from an upper surface of the first circuit board to a lower surface of the second circuit board along a first side surface of the first solder ball; and a second adhesive disposed between the first circuit board and the second circuit board so as to extend from an upper surface of the first circuit board to a lower surface of the second circuit board along a second side surface of the second solder ball. A first side surface of the first solder ball and a second side surface of the second solder ball are disposed to face each other. The first binder and the second binder form a channel region between the first circuit board and the second circuit board. An area of the channel region corresponds to 30%-70% of an area of a gap between a first side surface of the first solder ball and a second side surface of the second solder ball.

The application discloses a quantum device and an electronic device and a preparation method thereof, and belongs to the field of quantum information. The quantum device comprises a quantum chip, a signal transmission element formed on the quantum chip, and a connecting part electrically connected with the signal transmission element; a packaging substrate, a lead-out part formed on the packaging substrate, and a lead-out signal line for electrically connecting with a signal connector, the lead-out signal line being electrically connected with the lead-out part; and a ball grid array electrically connecting the corresponding connecting part and the lead-out part. The ball grid array electrically connects the connecting part and the lead-out part corresponding to the signal transmission attribute, thereby realizing the electrical connection between the quantum chip and the transmission line, and further leading out the connecting part to the external signal connector. In the application, the ball grid array does not generate a complex field effect, and the electrical connection of the corresponding connecting part and the lead-out part by the ball grid array can avoid the interference caused by the bonded aluminum wire.

The invention discloses a Ka wave band four-channel transceiving SiP module based on silicon-based packaging and a manufacturing method thereof, the SiP module adopts a silicon-based packaging material and comprises an upper layer sub-packaging and a lower layer sub-packaging, and the upper layer sub-packaging and the lower layer sub-packaging are vertically interconnected through a ball grid array (BGA); the lower-layer sub-package comprises three layers of silicon adapter plates with a first thickness, a cavity for mounting a three-port transceiver chip is etched on the middle-layer silicon adapter plate, and a TSV with a first diameter is manufactured on each layer of silicon adapter plate; the upper layer sub-package comprises three layers of silicon adapter plates, the upper layer silicon adapter plate and the lower layer silicon adapter plate have a first thickness and are provided with TSVs with a first diameter, the middle layer silicon adapter plate is etched with a cavity used for mounting a silicon-based amplitude-phase multifunctional chip and a power supply modulation chip, the middle layer silicon adapter plate has a second thickness and is provided with TSVs with a second diameter, and the middle layer silicon adapter plate is etched with a cavity used for mounting a silicon-based amplitude-phase multifunctional chip and a power supply modulation chip. Wherein the second thickness is greater than the first thickness and the second diameter is greater than the first diameter. According to the invention, the requirements of miniaturization, integration and high performance of a radar system can be met.

The application discloses a kind of ball grid array package chip solder ball bubble defect automatic detection method and system, it is related to chip intelligent detection technical field, the method is guided by designing semantic cross-layer fusion framework, realizes multi-scale feature balanced fusion in neck network by introducing feature alignment and redistribution module, strengthens small target details and semantic information using local semantic enhancement module, and the positioning accuracy of bubble is optimized in combination with smooth geometry positioning loss function.The application significantly improves the detection capability of small, fuzzy and occluded bubbles, has strong robustness and generalization, and can be widely used in solder ball bubble, material porosity and surface defect industrial vision detection scene.

The invention discloses a water-soluble soldering flux capable of being used for high-temperature ball mounting, which belongs to the technical field of electronic packaging, and comprises the following components in percentage by mass: 70-95% of ionic liquid, 5-30% of organic acid, 5-30% of cosolvent and 0.1-10% of other functional components, and the sum of the mass percentages of the components is 100%. The water-soluble soldering flux is prepared by heating, mixing, stirring and cooling. The soldering flux can be applied to electronic soldering tin welding processes such as a surface mounting process and a ball grid array (BGA) ball mounting process. The high-temperature-resistant ionic liquid and the high-temperature-resistant organic acid are used for manufacturing the high-temperature-resistant scaling powder, meanwhile, the high decomposition temperature of the high-temperature-resistant ionic liquid and the high-temperature-resistant organic acid is used for increasing the active window of the scaling powder, the situation that the active temperature window is too low due to use of a traditional solvent is avoided, and the high-temperature-resistant scaling powder can be used for high-temperature or high-

The invention provides a packaging structure, an integrated circuit, a memory and electronic equipment, and belongs to the technical field of semiconductors. The packaging structure comprises: a packaging substrate; the first ball grid array is located on the first surface of the packaging substrate, the first ball grid array comprises first metal balls and second metal balls adjacent to the first metal balls, the first metal balls are electrically coupled to the first surface through first bonding pads, and the second metal balls are electrically coupled to the first surface through second bonding pads; a connection part electrically coupled with the first pad; the functional part is connected with the first metal ball through a connecting part, the functional part comprises a plurality of metal discs and a plurality of metal wires which are located above the second bonding pad, and every two adjacent metal discs are connected through one metal wire. According to the invention, when an electric signal is transmitted through the first metal ball, far-end crosstalk and impedance discontinuity between the first metal ball and the second metal ball can be reduced.

A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a carrier having a first surface and a second surface opposite to the first surface of the carrier. The carrier has a through hole filled with a first package body and extending between the first surface and the second surface of the carrier. The WBGA package also includes an electronic component disposed on the second surface of the carrier. The electronic component includes a first bonding pad and a second bonding pad. The WBGA package also includes a first bonding wire electrically connected between the first bonding pad and the second bonding pad.

The invention discloses a server, which relates to the technical field of servers, and is characterized in that a management control board is vertically fixed on a mainboard instead of arranging the management control board and the mainboard side by side on the same horizontal plane, so that the size of a server main board card in the length direction is only the size of the mainboard in the length direction; the overall size of the main board and the management control board after the main board and the management control board are overlapped in the length direction is not the overall size of the main board and the management control board after the main board and the management control board are overlapped in the length direction, due to the fact that pluggable packaging is larger than the packaging size of ball grid array packaging, one first flash memory and one second flash memory are arranged to be in pluggable packaging, and the other first flash memories and the other second flash memories are in ball grid array packaging. Therefore, the size of the management control board can be reduced as much as possible while the debugging requirement of the board card in the initial stage and the online burning requirement after complete later function development can be met, so that the purpose of integrally reducing the sizes of the server main body board card in multiple directions is achieved.

The invention discloses a geometric-process comprehensive parameter optimization method, system and equipment for BGA welding spot reflow soldering. Designing a geometric model of the BGA welding spot, and storing data as a form as a data set based on a preset geometric-process parameter level; performing finite element simulation of the reflow process by using an orthogonal test method to obtain a deformation value of the welding spot; the method comprises the following steps: carrying out range analysis to obtain a geometric-process parameter level corresponding to the minimum deformation of a welding spot after reflow soldering, carrying out finite element simulation to obtain the minimum deformation, carrying out weight analysis to obtain parameters with obvious influence, and sorting the parameters, so that the geometric structure and reflow process parameters of the welding spot are quickly optimized under the finite simulation results, and the optimization efficiency is improved. According to the method, the deformation value of a welding spot after reflow soldering is reduced, meanwhile, each geometric-process can be evaluated, the weight of each geometric-process parameter is obtained, the key optimized parameter is determined, and therefore a certain reference significance is provided for the actual reflow soldering process.

The invention discloses a three-dimensional stacked frequency conversion SIP (Session Initiation Protocol), which comprises a bottom BGA (Ball Grid Array), three-dimensional stacked middle layer solder balls, a ceramic bottom plate, a kovar enclosure frame, a cover plate and a reconfigurable upper-layer multi-layer printed board, the ceramic bottom plate, the kovar enclosure frame and the cover plate jointly form a ceramic shell; a reconfigurable upper-layer multilayer printed board is stacked on the ceramic bottom plate through three-dimensional stacked middle-layer solder balls, an inner cavity of the ceramic shell is divided into a lower cavity body and an upper cavity body, the lower cavity body is provided with a bottom-layer chip installation area on the upper surface of the ceramic bottom plate, and the bottom-layer chip installation area is used for installing a universal functional chip. The upper cavity is provided with an upper-layer reconfigurable chip mounting area on the upper surface of the reconfigurable upper-layer multi-layer printed board, and the upper-layer reconfigurable chip mounting area is used for mounting a reconfigurable functional chip; a bottom BGA ball grid array is arranged on the lower surface of the ceramic bottom plate and used for leading out radio frequency, power supply and control signals. Through a three-dimensional stacking structure and a reconfigurable technology, a high-flexibility and high-reliability packaging solution is realized, and the customization cost is reduced.

The invention relates to the technical field of microwave radio frequency components, in particular to a BGA delay driving component based on an HTCC process. According to the technical scheme, the device comprises a shell and further comprises a cover plate used for improving the sealing performance of the device, the cover plate is arranged on the outer side of the shell, an HTCC multi-layer circuit substrate is arranged at the lower position in the shell, a four-bit time delay unit MMIC chip is arranged at the middle position of the HTCC multi-layer circuit substrate, and the four-bit time delay unit MMIC chip is arranged at the lower position of the HTCC multi-layer circuit substrate. And a wave control chip is arranged on the right side of the four-bit time delay unit MMIC chip. Through the characteristics of the HTCC process, the assembly has the advantages of high mechanical strength, high wiring density, stable chemical performance, high heat dissipation coefficient, low material cost and the like, and meanwhile, the ball grid array packaging (BGA) technology is applied to an integrated circuit, so that the BGA packaging has low insertion loss, excellent signal integrity, compact size, high integration level and high reliability. Therefore, the high-speed performance is better.

A sub-pixel-level detection method and application for ball grid arrays (BGAs) of packaged chips is disclosed. The method includes: acquiring a binary image of the solder ball array of the BGA; extracting all solder ball regions from the binary image and filtering to obtain all solder balls; extracting edge pixels of each solder ball and determining the sub-pixel edge points of each solder ball based on the grayscale value difference between each edge pixel and its adjacent pixels; obtaining the center coordinates and radius of each solder ball based on its sub-pixel edge points; rotating the binary image using an affine transformation method to calculate the transformed center coordinates of each solder ball in a two-dimensional coordinate system; and determining the row and column positions of each solder ball based on its transformed center coordinates and radius to complete the sub-pixel-level detection of the BGA. This application achieves sub-pixel-level detection of ball grid arrays, solving the problem of low recognition accuracy in existing ball grid array components.

The invention provides a multifunctional ball grid array packaging device soldering paste printing device which comprises a device positioning assembly, the device positioning assembly is installed on a base, the positioning assembly comprises a device tray, a positioning push plate and a driving module, the positioning push plate and the driving module are arranged on the device tray, and the device tray is provided with a plurality of device grooves; the positioning push plate is provided with a plurality of device grooves, the plurality of device grooves and the plurality of device grooves are arranged in a one-to-one correspondence manner, preset points are arranged on the edges of the device grooves, and the driving module drives the positioning push plate to move so as to drive the ball grid array packaging device to move and enable the ball grid array packaging device to be in contact with the preset points; the steel mesh assembly is arranged above the device positioning assembly, the steel mesh assembly comprises a steel mesh frame and a steel mesh installed in the steel mesh frame, and the steel mesh is selected from one of a printing steel mesh and a ball mounting steel mesh; the demolding assembly is installed on the base and used for driving the steel mesh assembly to be away from or close to the positioning assembly; and a base.

This application relates to a PCB circuit board, a layout method, and a chip. The PCB circuit board includes a board body and vias. The board body includes multiple layers connected by vias. The vias include signal vias and ground vias. In the trace extension direction of the PCB circuit board, the spacing between each signal via and an adjacent ground via, and the spacing between each signal via and other adjacent signal vias, are defined as a first spacing. The spacing between each ground via and other ground vias is defined as a second spacing. Both the first and second spacings are less than a reference spacing and greater than or equal to a minimum process spacing. The reference spacing is the spacing between solder balls in the ball array layer of the ball grid array package structure corresponding to the PCB circuit board. Using this PCB circuit board can reduce signal line crosstalk.

Disclosed are semiconductor packages. A semiconductor package may include a first die encapsulated by a mold, and a second die directly on the mold. One or more conductive posts may be formed in the mold. A frontside redistribution layer (RDL) may be provided on a lower surface of the mold. Electrical signals between the first and second dies may be carried through the posts and the frontside RDL. There is no need for backside RDL and backside ball grid array. This can significantly reduce the height of the semiconductor package.

The invention provides a ball grid array lightweight radio frequency assembly based on impact resistance, and relates to the technical field of radio frequency. The radio frequency assembly comprises a substrate, a side plate, a support plate, an elastic member, a pop support ball, a chip silicon substrate and a BGA solder ball. The side plate is installed on the substrate, a plurality of supporting plates are arranged in the substrate, elastic pieces are arranged between the supporting plates and the substrate, every two adjacent supporting plates are connected through a pop supporting ball, the chip silicon substrate is installed on the supporting plates, and the substrate is connected with an external structure through a BGA welding ball. Through various structures, the stability of the radio frequency assembly is enhanced, and an anti-impact mechanical structure is utilized to construct a shielding structure, so that the weight and the manufacturing cost of the radio frequency assembly are reduced.

A circuit card with interstitial surface mounted components. In an example, the circuit card includes a first surface; a second surface opposite the first surface; and an array of pads disposed on the first surface. The pads are configured to provide electrical coupling of the circuit card to a ball grid array of an electronic device. The circuit card also includes one or more interstitial electrical components mounted between the pads of the array on the first surface of the circuit card. The circuit card further includes one or more additional electrical components mounted on the second surface of the circuit card and on the first surface of the circuit card outside of a region comprising the array of pads. The electrical components may include capacitors, bypass capacitors, inductors, and / or resistors. The electronic device may be an integrated circuit or a field programmable gate array.