22074 results about "Manufacturing technology" patented technology

The present invention provides methods, techniques, materials and devices and uses thereof for custom-fitting biocompatible implants, prosthetics and interventional tools for use on medical and veterinary applications. The devices produced according to the invention are created using additive manufacturing techniques based on a computer generated model such that every prosthesis or interventional device is personalized for the user having the appropriate metallic alloy composition and virtual validation of functional design for each use.

Embodiments of the invention provide treatment processes to reduce substrate contamination during a fabrication process within a vapor deposition chamber. A treatment process may be conducted before, during or after a vapor deposition process, such as an atomic layer deposition (ALD) process. In one example of an ALD process, a process cycle, containing an intermediate treatment step and a predetermined number of ALD cycles, is repeated until the deposited material has a desired thickness. The chamber and substrates may be exposed to an inert gas, an oxidizing gas, a nitriding gas, a reducing gas or plasmas thereof during the treatment processes. In some examples, the treatment gas contains ozone, water, ammonia, nitrogen, argon or hydrogen. In one example, a process for depositing a hafnium oxide material within a batch process chamber includes a pretreatment step, an intermediate step during an ALD process and a post-treatment step.

The present invention relates to a process and a product of forming polymer (especially PVC) nanocomposites with a variety of nanofillers. The present invention provides a method for forming a polymer nanocomposite, comprising powder mixing a composition comprising polymer resin, a nanofiller, and a coupling agent for a residence time of about 4 to about 8 minutes to form a dry blend and extruding the dry blend in an extrusion process. Additionally, the present invention relates to a polymer nanocomposite formed by a process, comprising powder mixing a polymer resin, a nanofiller, and a coupling agent for a residence time of about 4 to about 8 minutes to form a dry blend and extruding the dry blend in an extrusion process to achieve homogeneous dispersion of nanofillers in the polymer matrix.

To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip. It is possible to realize a unique connection structure having a high reliability in accordance with the caulking action using the plastic flow of a metallic bump in a very-low-cost short-TAT process and provide a three-dimensional inter-chip connection structure having a high practicability.

With non-contact and contact IC chips becoming common, it is necessary to mass-produce enormous amount of IC chips, which are utilizable for human beings, animals and plants, commercial products, banknotes, and the like, at low cost. For example, it is necessary to manufacture IC chips to be applied to commercial products, banknotes, and the like at a cost of 1 to several yen per IC chip, preferably, at a cost less than 1 yen, and it is desired to realize a structure of an IC chip that can be mass-produced at low cost and a manufacturing process of the IC chip. A method of-manufacturing a thin film integrated circuit device according to the present invention includes steps of forming a peel-off layer over a thermally oxidized silicon substrate, forming a plurality of thin film integrated circuit devices over the peel-off layer with a base film interposed therebetween, forming a groove between the plurality of thin film integrated circuit devices, and separating the plurality of thin film integrated circuit devices by introducing one of a gas and a liquid including halogen fluoride into the groove to remove the peel-off layer.

Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

An embolic coil which can be used for occlusive purposes in the vasculature is described. A mandrel for manufacturing a coiled structure, and method/process for manufacturing a coiled structure is described.

A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (W_fin), gate length (L_G) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.

Various techniques for the fabrication of highly accurate master molds with precisely defined microstructures for use in plastic replication using injection molding, hot embossing, or casting techniques are disclosed herein. Three different fabrication processes used for master mold fabrication are disclosed wherein one of the processes is a combination of the other two processes. In an embodiment of the first process, a two-step electroplating approach is used wherein one of the metals forms the microstructures and the second metal is used as a sacrificial support layer. Following electroplating, the exact height of the microstructures is defined using a chemical mechanical polishing process. In an embodiment of the second process, a modified electroforming process is used for master mold fabrication. The specific modifications include the use of Nickel-Iron (80:20) as a structural component of the master mold, and the use of a higher saccharin concentration in the electroplating bath to reduce tensile stress during plating and electroforming on the top as well as sides of the dummy substrate to prevent peel off of the electroform. The electroforming process is also well suited towards the fabrication of microstructures with non-rectangular cross sectional profiles. Also disclosed is an embodiment of a simple fabrication process using direct deposition of a curable liquid molding material combined with the electroforming process. Finally, an embodiment of a third fabrication process combines the meritorious features of the first two approaches and is used to fabricate a master mold using a combination of the two-step electroplating plus chemical mechanical polishing approach and the electroforming approach to fabricate highly accurate master molds with precisely defined microstructures. The microstructures are an integral part of the master mold and hence the master mold is more robust and well suited for high volume production of plastic MEMS devices through replication techniques such as injection molding.

The present invention provides a thin film amorphous silicon-crystalline silicon back heterojunction and back surface field device configuration for a heterojunction solar cell. The configuration is attained by the formation of heterojunctions on the back surface of crystalline silicon at low temperatures. Low temperature fabrication allows for the application of low resolution lithography and/or shadow masking processes to produce the structures. The heterojunctions and interface passivation can be formed through a variety of material compositions and deposition processes, including appropriate surface restructing techniques. The configuration achieves separation of optimization requirements for light absorption and carrier generation at the front surface on which the light is incident, and in the bulk, and charge carrier collection at the back of the device. The shadowing losses are eliminated by positioning the electrical contacts at the back thereby removing them from the path of the incident light. Back contacts need optimization only for maximum charge carrier collection without bothering about shading losses. A range of elements/alloys may be used to effect band-bending. All of the above features result in a very high efficiency solar cell. The open circuit voltage of the back heterojunction device is higher than that of an all-crystalline device. The solar cell configurations are equally amenable to crystalline silicon wafer absorber as well as thin silicon layers formed by using a variety of fabrication processes. The configurations can be used for radiovoltaic and electron-voltaic energy conversion devices.

A dental appliance having an integrally formed reservoir and/or an ornamental design integrated thereon. The ornamental design can be selected or customized by a patient. The design can be created by directing energy to the dental appliance to alter a material property of at least a portion of the appliance to create the design. Alternatively, a groove or recess can be formed on a surface of the appliance to either mechanically retain an ornamental design or the groove or recess can be filled with ink to form the design. The appliance, including the integrally formed reservoir, can be formed using direct fabrication techniques.

An optical lens is provided. The optical lens provides miniaturization and thin size, and reduces the cost and improves productivity by simplifying the structure and manufacturing process. The optical lens includes a light-transmitting substrate with a lens chamber and a fluidic chamber that are connected with each other. The optical lens also includes a light-transmitting elastic film which seals the lens chamber, a buffer elastic film which seals the fluidic chamber, and an actuator on the buffer elastic film which corresponds to the fluidic chamber, and varies the volume of the fluidic chamber to vary a pressure acting on the light-transmitting elastic film.

A dental appliance having an integrally formed reservoir and/or an ornamental design integrated thereon. The ornamental design can be selected or customized by a patient. The design can be created by directing energy to the dental appliance to alter a material property of at least a portion of the appliance to create the design. Alternatively, a groove or recess can be formed on a surface of the appliance to either mechanically retain an ornamental design or the groove or recess can be filled with ink to form the design. The appliance, including the integrally formed reservoir, can be formed using direct fabrication techniques.

Manufacturing semiconductor device by steps of:

• • a) providing substrate with antireflective coating or underlayer,
  • b) applying first photosensitive composition over substrate,
  • c) exposing first composition to radiation to produce first pattern,
  • d) developing exposed first composition to produce an imaged bilayer stack,
  • e) rinsing the stack,
  • f) applying fixer to the stack,
  • g) applying optional bake,
  • h) rinsing the stack,
  • i) applying second optional bake,
  • j) applying second photosensitive composition onto the stack to produce multilayer stack,
  • k) exposing second composition to produce second pattern offset from first pattern,
  • l) developing exposed second composition to produce multilayer stack, and
  • m) rinsing multilayer stack;

the photosensitive compositions have photoacid generator and substantially aqueous base insoluble polymer whose solubility increases upon treatment with acid and further comprises an anchor group, and the fixer is a polyfunctional compound reactive with anchor group, but does not contain silicon and the substrate stays within a lithographic cell from at least first coating step until at least after final exposure.

A method and an arrangement for producing a workpiece using additive manufacturing techniques involve in-process measurement in order to determine individual characteristics of one or more workpiece layers. In particular, dimensional and/or geometrical characteristics of a workpiece layer are measured before the next workpiece layer is produced. Advantageously, the measurement results are fed back into the production process in order to increase accuracy and precision of the production process.

Methods and systems of stereolithography for building cost-efficient and time-saving multi-material, multi-functional and multi-colored prototypes, models and devices configured for intermediate washing and curing/drying is disclosed including: laser(s), liquid and/or platform level sensing system(s), controllable optical system(s), moveable platform(s), elevator platform(s), recoating system(s) and at least one polymer retaining receptacle. Multiple polymer retaining receptacles may be arranged in a moveable apparatus, wherein each receptacle is adapted to actively/passively maintain a uniform, desired level of polymer by including a recoating device and a material fill/remove system. The platform is movably accessible to the polymer retaining receptacle(s), elevator mechanism(s) and washing and curing/drying area(s) which may be housed in a shielded enclosure(s). The elevator mechanism is configured to vertically traverse and rotate the platform, thus providing angled building, washing and curing/drying capabilities. A horizontal traversing mechanism may be included to facilitate manufacturing between components of SL cabinet(s) and/or alternative manufacturing technologies.

Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.

Some aspects provide a method of generating a support structure for an object, the support structure and the object to be fabricated via one or more additive fabrication techniques, comprising identifying one or more regions of the object as one or more regions to which mechanical support is to be provided, identifying one or more support points within at least a first region of the one or more regions, and generating the support structure for the object, the support structure comprising one or more support tips coupled to the object at the one or more support points, the support tips being generated based at least in part on a direction normal to the surface of the object at the respective support point.

A lower cost range-finding image sensor based upon measurement of reflection time of light with reduced fabrication processes compared to standard CMOS manufacturing procedures. An oxide film is formed on a silicon substrate, and two photo-gate electrodes for charge-transfer are provided on the oxide film. Floating diffusion layers for taking charges out from a photodetector layer are provided at the ends of the oxide film, and on the outside thereof are provided a gate electrode for resetting and a diffusion layer for providing a reset voltage.

A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.