676 results about "Amorphous silicon" patented technology

The invention discloses a back contact cell and a preparation method thereof, a laminated cell and a photovoltaic module, and belongs to the technical field of photovoltaics, the back contact cell comprises a substrate, the substrate comprises a first region, a second region and a spacer region located between the first region and the second region, and a tunneling oxide layer and a doped polycrystalline silicon layer are arranged in the first region and the spacer region. The doped polycrystalline silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the tunneling oxide layer, the amorphous silicon passivation layer and the doped amorphous silicon layer are arranged in the second region and the spacer region, and the doped amorphous silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the amorphous silicon passivation layer. And the amorphous silicon passivation layer in the spacer region is positioned on one side, deviating from the substrate along the thickness direction, of the doped polycrystalline silicon layer. The insulating layer is arranged between the amorphous silicon passivation layer and the doped polycrystalline silicon layer, the insulating layer comprises a first insulating part which extends in the thickness direction and is arranged at the junction position of the second region and the spacer region, the first insulating part can prevent the back contact cell from leaking electricity in the horizontal direction, and the overall electrical performance of the back contact cell is improved.

The invention belongs to the technical field of back contact photovoltaic cells, and particularly relates to a back contact photovoltaic cell with high-concentration co-doped regions and a manufacturing method and application thereof.The back contact photovoltaic cell with the high-concentration co-doped regions is characterized in that N-type doped regions and P-type doped regions which are alternately distributed are arranged on the backlight face of an intrinsic amorphous silicon layer, and the high-concentration co-doped regions are arranged between the N-type doped regions and the P-type doped regions; a doping source of the co-doped region comprises doping source phosphorus of the N-type doped region and doping source boron of the P-type doped region, the co-doped region, the doping source of the N-type doped region and the doping source of the P-type doped region form a specific concentration gradient structure, and the specific concentration gradient structure meets the condition that the doping concentration of phosphorus contained in the co-doped region is greater than that of phosphorus contained in the N-type doped region; the doping concentration of boron contained in the co-doped region is greater than the doping concentration of boron in the P-type doped region. The carrier transport and collection efficiency is optimized, the fill factor and open-circuit voltage are improved, the cell conversion efficiency and stability are improved, the preparation process is simple, and multiple times of opening etching are not needed.

The invention belongs to the field of heterojunction cells, and particularly discloses a heterojunction cell and a preparation method thereof, which are characterized in that heavily doped amorphous silicon is deposited in a corresponding area of a grid line electrode, so that high parasitic absorption, surface dangling bond and interface state density are reduced, and the open voltage and the efficiency of the heterojunction cell are improved. The main technical scheme of the invention is as follows: according to the heterojunction cell, grooves are formed in corresponding areas of grid line electrodes on the front surface and the back surface of an N-type silicon substrate; arranging an intrinsic amorphous silicon layer; the light doping P-type amorphous silicon layer is arranged on the front intrinsic amorphous silicon layer, the light doping N-type amorphous silicon layer is arranged on the back intrinsic amorphous silicon layer, the heavy doping P-type amorphous silicon layer is arranged in a groove corresponding area on the light doping P-type amorphous silicon layer, the heavy doping N-type amorphous silicon layer is arranged in a groove corresponding area on the light doping N-type amorphous silicon layer, and the light doping N-type amorphous silicon layer is arranged in a groove corresponding area on the light doping N-type amorphous silicon layer. The P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are respectively provided with a transparent conductive oxide layer, and the grid line electrodes are arranged on the transparent conductive oxide layers. The invention is mainly used for power generation.

The invention belongs to the technical field of photovoltaic cells, and particularly relates to a back contact photovoltaic cell, a back contact photovoltaic cell assembly and a preparation method, and the method comprises the steps: providing an N-type silicon wafer which is provided with a double-sided texturing structure, and the textured surface is of a pyramid structure after texturing; boron diffusion is carried out on the backlight surface of the silicon wafer to form a P + doping layer, and meanwhile, a lightly doped P-type region is formed on the illuminated surface of the silicon wafer through diffusion and dissipation; performing laser film opening on the backlight surface P + doping layer to form P region and N region structures which are distributed in a staggered manner; depositing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer in the N region, and annealing the tunneling oxide layer and the phosphorus-doped amorphous silicon layer to form an N + polycrystalline silicon layer; printing etching slurry on the surface of the P region, performing etching slurry film opening, removing phosphorosilicate glass and forming an isolation gap between the P region and the N region; and the film is opened by printing etching slurry, so that the suede cannot generate thermal damage.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell with a specific front surface structure and a cell assembly thereof, and the specific front surface structure comprises a tunneling oxide layer and a specific doped amorphous silicon layer which are sequentially arranged on the front surface of a silicon substrate, a low-doped amorphous silicon layer, a high-doped amorphous silicon layer and an oxygen-doped amorphous silicon layer are sequentially arranged in the specific doped amorphous silicon layer along the direction far away from the tunneling oxide layer, and the specific doped amorphous silicon layer is doped with a P element and contains an H element; the P doping concentration C1 of the low-doping amorphous silicon layer and the P doping concentration C3 of the oxygen-doping amorphous silicon layer are respectively smaller than the P doping concentration C2 of the high-doping amorphous silicon layer, and the specific front structure enables the back contact cell to absorb incident light within 400 nm, and the highest absorptivity exceeds 85%. The back contact battery disclosed by the invention can still keep good performance after being exposed to ultraviolet rays for a long time, the UV reliability of the battery is improved, meanwhile, high light transmittance is realized, and relatively high battery efficiency is also realized.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell capable of reducing the thickness difference between an N-type region and a P-type region and preparation and application of the back contact cell capable of reducing the thickness difference between the N-type region and the P-type region. Wherein the surface of one side, far away from the crystalline silicon substrate, of the amorphous silicon layer is provided with an N-type region and a P-type region which are alternately formed, the N-type region comprises an N-type doped base layer and an N-type transition layer, and the P-type region comprises a P-type doped base layer and a P-type transition layer; wherein the content ratio of phosphorus to silicon in the N-type doped base layer is smaller than 1, the content ratio of phosphorus to silicon in the N-type transition layer is larger than 1, the content ratio of boron to silicon in the P-type doped base layer is smaller than 1, and the content ratio of boron to silicon in the P-type transition layer is larger than 1. The vertical contact resistance can be obviously reduced while the thickness difference between the N-type region and the P-type region is reduced, the high cell conversion efficiency is obtained, the stability of the cell is improved, and the service life of the cell is prolonged; meanwhile, the risk of film explosion in the subsequent process is reduced, and the edge compounding problem is relieved.

The invention provides a preparation method of a surface structure of a back contact battery, which relates to the technical field of back contact batteries, and comprises the following steps: S1, carrying out double-sided polishing on the surface of a silicon wafer: firstly carrying out rough polishing, removing a damaged layer on the surface of the silicon wafer, then cleaning with acid and ozone, then carrying out fine polishing, then cleaning with a mixed solution of hydrogen peroxide and alkali, and then carrying out acid pickling with ozone, then cleaning with a mixed solution of acid and hydrogen peroxide, and finally washing and drying; sequentially depositing a tunneling oxide layer and amorphous silicon on a single surface at high temperature; and performing high-temperature diffusion on the surface to form a crystallized first semiconductor region and a mask layer BSG. According to the invention, the specific suede structure is formed on the front surface, and the polished surface is formed on the back isolation base region, so that high reflectivity of the back isolation base region is ensured, the specific suede structure on the front surface can be independently designed, and meanwhile, a double-surface ozone oxidation process is added; therefore, the open-circuit voltage and the short-circuit current of the cell are improved, and the photoelectric conversion efficiency of the cell is improved.

To provide a technology capable of reducing the occurrence of seams when filling a recessed portion with a silicon nitride film.SOLUTION: A film formation method according to an embodiment of the present disclosure includes the steps of (a) preparing a substrate having a recess on its surface, (b) forming a silicon nitride film in the recess, (c) forming an amorphous silicon film in the recess, (d) removing the amorphous silicon film, and (e) filling the recess with a silicon nitride film after step (d), and the amorphous silicon film is formed to have a lower step coverage than the silicon nitride film, and step (c) is performed one or more times during step (b).SELECTED DRAWING: Figure 10

The invention provides a solar cell and a preparation method thereof, a photovoltaic module and a laminated cell, and relates to the field of photovoltaic technology. The solar cell includes a silicon substrate; along the thickness direction of the silicon substrate, the silicon substrate comprises a light facing surface and a backlight surface which are opposite to each other; the light-facing face and the backlight face are each provided with a suede structure, and the average size of the suede structures of the light-facing face is smaller than that of the suede structures of the backlight face. The whole tunneling oxide layer and the doped polycrystalline silicon layer are sequentially stacked on the light-facing surface; the whole intrinsic amorphous silicon passivation layer and the whole doped amorphous silicon layer are sequentially arranged on the backlight face in a stacked mode. Good passivation effects and anti-reflection effects are obtained on the two sides of the silicon substrate.

The invention discloses a double-heating-system electronic-grade polycrystalline silicon reduction furnace and a process method thereof, and relates to the technical field of polycrystalline silicon production equipment, and the reduction furnace comprises a cooling liquid inlet and a cooling liquid outlet which are respectively formed in the upper part and the lower part of a microwave window; a microwave emission branch pipe is fixedly arranged on the outer side of each microwave window, and each microwave emission branch pipe is connected with the microwave emitter through a microwave transmission header pipe; the method comprises the following steps: S1, starting the furnace; s2, early growth stage of the silicon rod; s3, middle growth stage of the silicon rod; s4, later growth stage of the silicon rod; and S5, blowing out the furnace and cooling. The double-heating-system electronic-grade polycrystalline silicon reduction furnace has the beneficial effects that silicon rods with larger diameters can be produced, and the yield of a single furnace is remarkably increased; the quality of the silicon rod is improved, and the high quality requirement of electronic-grade polycrystalline silicon is met; according to the process method disclosed by the invention, the utilization rate of raw materials is increased to 89% or above, the generation amount of amorphous silicon powder is reduced to 7.2 kg / furnace or below, and the energy consumption of a unit silicon rod is reduced.

The invention provides a method for testing the contact resistance of a solar cell film, which comprises the following steps of: preparing a plurality of multi-layer stacked test samples with different thicknesses, and alternately depositing an amorphous silicon film and a transparent conductive oxide film on a glass substrate of each sample to form a horizontal laminated structure; respectively arranging silver electrodes on the left side and the right side of each sample for performing voltage-current volt-ampere test, and recording the total resistance of each sample in a specified voltage range and the change condition of the total resistance along with the thickness of the film layer; electrode contact resistance is measured and deducted; reversely deducing the resistance value when the thickness of the film layer is 0 through an extrapolation method to obtain the contact resistance between the film layers; and calculating the contact resistance of a single interface according to the number of contact interfaces of the amorphous silicon film and the transparent conductive oxide film in the sample. The method is suitable for a test system under different manufacture procedures and thickness changes, and quantitative extraction of the contact resistance between the amorphous silicon and the TCO is achieved.

The invention relates to a solar cell and a preparation method thereof, the solar cell comprises a semiconductor substrate, a first polarity structure, a second polarity structure and a mixed passivation structure, and the semiconductor substrate comprises a first surface with a first region and a second region which are adjacently arranged; the first and second polar structures are respectively positioned in the first and second regions; the mixed passivation structure comprises a dielectric passivation layer which is located in the first region and comprises a first part covering the top surface of the first polar structure and a second part covering the side wall, close to the second polar structure, of the first polar structure; the intrinsic passivation layer comprises a third part located between the semiconductor substrate and the second polar structure and a fourth part located on the side wall, close to the first polar structure, of the second polar structure, and the fourth part and the second part are in contact overlapping in the direction perpendicular to the semiconductor substrate. According to the solar cell and the preparation method thereof, the problem of insufficient boundary passivation in a whole-surface amorphous silicon deposition process is avoided, and the device performance is improved.

Disclosed are a semiconductor device having improved selector characteristics of a memory cell and a method for manufacturing the same. The semiconductor device includes a plurality of memory cells, where each of the memory cells includes: a memory layer; a selector layer formed in an upper portion or a lower portion of the memory layer to select the memory layer; and a buffer layer directly coupled to an upper portion or a lower portion of the selector layer, where the buffer layer includes an amorphous silicon layer including at least one dopant selected from a group including Group 13 elements, Group 14 elements, and Group 15 elements of the periodic table.

The invention discloses a method for realizing a multi-polarization high-numerical aperture Laplace differentiator based on a metasurface, and belongs to the technical field of micro-nano photonics, optical simulation calculation and light field regulation and control. The single-layer metasurface is composed of a cylindrical array which is made of an amorphous silicon material and has a hexagonal lattice period. Geometric parameters of a silicon cylinder are designed and selected, so that the metasurface excites resonance spectrums with large-angle dispersion capability under illumination of p polarized light and s polarized light in the same working wavelength range, and an optical transfer function required by optical Laplacian differential operation with broadband and high numerical aperture is realized in a real airspace; and Laplacian operation can be executed under non-polarized light and non-coherent light conditions. And generating a processing file of the corresponding metasurface according to the determined geometric dimension of the silicon cylinder unit. And processing the dielectric metasurface by adopting a micro-nano processing technology of electron beam etching. In a working wave band, the metasurface can directly obtain two-dimensional second-order edge contour information of a target image under various illumination conditions.

According to the LPCVD equipment for online cleaning of the quartz tube and the online cleaning method, a quartz boat is placed in the quartz tube, the quartz tube is embedded in the inner side of a heating furnace body, and the two ends of the quartz tube are connected with a furnace door and a furnace tail flange through a furnace opening door plate and a furnace tail door plate respectively; air inlet spraying pipes are arranged on the furnace mouth door plate and the furnace door; an exhaust pipe connected with a vacuum pump is arranged on the furnace tail flange; one end of the I CP electrode bar is fixed on the furnace tail flange and connected with the radio frequency power supply assembly, and the other end of the I CP electrode bar penetrates through the furnace tail flange and extends into the quartz tube, and a gap exists between the I CP electrode bar and the quartz boat; fluoride gas is introduced into the quartz tube, the radio frequency power supply assembly is turned on, under the action of the ICP electrode bar, the fluoride gas forms fluorine plasma in the quartz tube, the fluorine plasma reacts with amorphous silicon on the inner wall of the quartz tube and amorphous silicon on the quartz boat, and therefore synchronous online cleaning of the quartz tube and the quartz boat is achieved. The device has the advantages of compact structure, convenience in operation, high cleaning efficiency, low cost and the like.

The invention discloses an axial asymmetric micro-channel plate structure based on an amorphous silicon material and a preparation method of the axial asymmetric micro-channel plate structure. The axial asymmetric micro-channel plate structure comprises a plurality of micro-channels arranged in a penetrating mode in the thickness direction of a device; each micro-channel is provided with an inlet section and an outlet section along the axial direction of the micro-channel plate; the channel geometric parameters of the micro-channels are different on the inlet section and the outlet section; or the equivalent electric fields of the micro-channels are distributed on the inlet section and the outlet section in a different manner; the inlet section of each micro-channel is used for regulating and controlling the initial incidence condition of electrons and the first effective interaction between the inlet section and the inner wall of the channel; collaborative design is carried out on geometrical morphology, electrical characteristics and material characteristics of the microchannels in the axial direction according to different physical stages of the electronic multiplication process corresponding to the structural level of the microchannels. According to the structure, higher controllability and consistency are obtained in the multiplication and transmission process of electrons in the channel on the structural level, and the structural rationality and design flexibility of the micro-channel plate serving as an electron multiplier are improved.

The utility model is applicable to the field of photovoltaic technology, and provides an HBC battery, a battery pack and a photovoltaic system, the HBC battery comprises a silicon substrate, the silicon substrate is provided with a backlight surface and a light facing surface which are oppositely arranged, the backlight surface of the silicon substrate is provided with a first area and a second area, the first area and the second area are alternately arranged, and the first area and the second area are not overlapped; an amorphous silicon layer is arranged in the first region, a polycrystalline silicon layer is arranged in the second region, the amorphous silicon layer and the polycrystalline silicon layer are shaped, and the refractive index of the amorphous silicon layer is larger than that of the polycrystalline silicon layer. And the parasitic absorption of light of the amorphous silicon layer is reduced, the optical utilization rate is improved, the unnecessary energy loss is reduced, and finally, the photoelectric conversion efficiency and the performance of the HBC battery are comprehensively improved.

The invention belongs to the technical field of solar cells, and discloses a preparation method of a high-efficiency and low-cost copper electroplating heterojunction solar cell. The preparation method of the efficient low-cost copper electroplating heterojunction solar cell comprises the steps of texturing and cleaning, amorphous silicon thin film deposition, transparent conductive thin film deposition, surface patterning, copper grid line electroplating and the like. According to the preparation method, the usage amount of the indium tin oxide thin film can be effectively reduced, the optical absorption of the TCO thin film is reduced by using the laminated structure, and the conversion efficiency and the corrosion resistance of the cell are improved.

A negative electrode material (100) comprises a silicon-carbon core (10) and a coating layer (20) that coats the silicon-carbon core (10), wherein the silicon-carbon core (10) comprises a porous carbon matrix (11) and an amorphous silicon material (12) arranged in pores of the porous carbon matrix (11), the volume of micropores in the porous carbon matrix (11) accounting for 80-90% of the total pore volume of the porous carbon matrix (11); and the amorphous silicon material (12) is doped with nitrogen, the nitrogen accounting for 0.2-1% of the total mass of the negative electrode material (100). By means of the arrangement of the micropores and the doping of amorphous silicon, the formation and growth of a crystalline phase during a reaction of the negative electrode material (100) with a metal can be effectively inhibited, thereby improving the structural stability and cycling stability of the negative electrode material (100), which is conducive to improving the cycling performance of a negative electrode sheet (200) and prolonging the cycle life of a battery.

The present disclosure relates to the technical field of solar cells. Disclosed are a solar cell, a preparation method therefor and a use thereof. A P-type doped region and an N-type doped region are alternately arranged on the back surface of a crystalline silicon substrate; a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially formed in the P-type doped region; and a phosphorus-doped silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, a second passivation layer and a second anti-reflection layer are sequentially formed on the surface of the crystalline silicon substrate in the N-type doped region. The P regions of traditional TBC cells mostly adopt a two-step process of depositing intrinsic amorphous silicon and performing boron diffusion to form a polycrystalline silicon layer. However, the P region of the present disclosure does not contain a polycrystalline silicon layer, and can be prepared by a one-step boron diffusion process, which can reduce the process steps and shorten the process time. The interaction between laser and the polycrystalline silicon in the P region is also avoided, the difficulty of cell patterning is reduced, and the production yield of cells can be greatly improved.

An acoustic wave device according to the present invention includes a piezoelectric substrate including a piezoelectric layer, a functional electrode provided on the piezoelectric layer, a first support layer provided on the piezoelectric substrate so as to surround the functional electrode, a covering portion provided on or above the first support layer and including a first main surface positioned on the functional electrode side and a second main surface opposite to the first main surface, a silicon oxide layer provided on the first main surface side of the covering portion, and an inductor provided on the silicon oxide layer and made of a wire. The covering portion is made of silicon. The acoustic wave device further includes one of an amorphous silicon layer and a polysilicon layer provided between the covering portion and the silicon oxide layer.

The utility model is applicable to the field of photovoltaic technology, and provides an HBC battery, a battery assembly and a photovoltaic system, the HBC battery comprises a silicon substrate, a first area and a second area are arranged on the backlight surface of the silicon substrate, and the first area and the second area are alternately arranged; a first polar polycrystalline silicon layer is arranged in the first region, a second polar amorphous silicon layer is arranged in the second region, the first region and the second region are both covered with TCO film layers, isolation grooves are formed in the positions, adjacent to the first region and the second region, of the TCO film, and the isolation grooves penetrate through the TCO film layers; at least a first TCO residue group and a second TCO residue group are adjacently arranged in the isolation groove, the first TCO residue group comprises a plurality of first TCO residue square rings which are adjacently arranged along the extension direction of the isolation groove, and the second TCO residue group comprises a plurality of second TCO residue square rings which are adjacently arranged along the extension direction of the isolation groove; the adjacent vertex angles of the first TCO residual square ring and the second TCO residual square ring are staggered.

The invention discloses a semiconductor device and a manufacturing method thereof. A semiconductor device includes a plurality of memory cells, each memory cell including: a memory layer; a first selector layer formed in an upper portion or a lower portion of the memory layer to select the memory layer; a second selector layer for selecting a memory layer; and an interface layer disposed between the first selector layer and the second selector layer, in which the first selector layer and the second selector layer include an amorphous silicon layer including one or more dopants selected from the group including Group 13 elements, Group 14 elements, and Group 15 elements of the periodic table, and wherein the interface layer is selected from the group comprising silicon oxide, silicon carbonitride, silicon carbonitride, silicon nitride, tantalum nitride, titanium nitride, aluminum nitride, and hafnium nitride.

The invention relates to a back contact battery, a manufacturing method thereof and a photovoltaic module. The back contact battery comprises a substrate which comprises a first surface and a second surface which are oppositely arranged, and a side surface which is connected with the first surface and the second surface; the first surface is provided with first regions and second regions which are alternately arranged, and the conduction types of the first regions and the second regions are different; the first region comprises a tunneling layer, a first semiconductor doping layer and a first transparent conducting layer which are sequentially arranged away from the substrate; the second region comprises an amorphous silicon layer, a second semiconductor doping layer and a second transparent conducting layer which are sequentially arranged in the direction away from the substrate; the side surface comprises a first passivation layer and a second passivation layer which are sequentially arranged away from the substrate, and the first passivation layer is connected with the first semiconductor doping layer and makes contact with the first semiconductor doping layer. The carrier recombination of the side surface is effectively improved, the passivation effect of the side surface is improved, the open-circuit voltage, the filling factor and the photoelectric conversion efficiency of the back contact battery are further improved, and the power generation performance of the back contact battery is improved.

The embodiments of the present disclosure belong to the technical field of back-contact cells, and particularly relate to a hybrid-passivated back-contact cell having passivation blocking layers and the manufacturing and application thereof. The hybrid-passivated back-contact cell comprises first semiconductor layers and second semiconductor layers, which are alternately arranged on a back surface of a silicon wafer, wherein two ends of each of the second semiconductor layers each extend outward to cover the outside of part of a back surface of a first semiconductor layer adjacent thereto; and overlapping portions of the first semiconductor layers and the second semiconductor layers in the direction of thickness form overlapping regions. The hybrid-passivated back-contact cell further comprises passivation blocking layers, which are in the overlapping regions and are arranged between the first semiconductor layers and the second semiconductor layers, wherein no mask layer is provided between the passivation blocking layers and the second semiconductor layers, the passivation blocking layers are made of amorphous silicon, and the thickness ratio of the passivation blocking layers to first doped polycrystalline silicon layers to tunneling oxide layers is 2-8: 60-100: 1. The embodiments of the present disclosure can protect the tunneling oxide layers from being corroded, thereby synergistically enhancing a passivation effect, and increasing the conversion efficiency and production yield of the cell.

The invention discloses a method for optimizing the contour of a contact hole and a semiconductor structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: introducing a silicon-containing precursor gas and a carbon-containing precursor gas on a substrate, and depositing to form a first amorphous silicon layer serving as an etching deceleration layer; and depositing on the first amorphous silicon layer to form a second amorphous silicon layer by stopping introducing the carbon-containing precursor gas and continuing introducing the silicon-containing precursor gas. Through in-situ deposition of the laminated structure of the carbon-containing layer and the pure amorphous silicon layer, the intrinsic etching selection ratio is constructed by using the property difference of materials, and an additional ion implantation step is not needed. According to the method, the technological process is simplified, the cost and the thermal budget are reduced, the etching bias load effect can be effectively improved, the contour of the contact hole is optimized, the contact hole is closer to be vertical and is uniform up and down, and therefore the yield and the reliability of the device are improved.

The invention relates to the technical field of solar cells, and discloses a TBC cell and a preparation method thereof.The preparation method comprises the steps that a tunneling layer and an intrinsic amorphous silicon layer are prepared on the back face of a silicon wafer; a first barrier layer is locally prepared on the back surface of the intrinsic amorphous silicon layer; boron diffusion enables the intrinsic amorphous silicon layer in a non-first barrier layer region to be converted into a boron-doped polycrystalline silicon layer; removing the local first barrier layer through laser patterning to expose the intrinsic amorphous silicon layer in a laser area; performing wet etching to form a Gap region, and exposing the boron-doped polycrystalline silicon layer and the intrinsic amorphous silicon layer in a non-laser region; locally preparing a second barrier layer on the back surfaces of the Gap region silicon wafer and the boron-doped polycrystalline silicon layer; phosphorus diffusion enables the exposed intrinsic amorphous silicon layer to be converted into a phosphorus-doped polycrystalline silicon layer; removing the second barrier layer and performing texturing; according to the method, the Gap region can be easily formed, the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer have no height difference, the working procedures are few, the damage is little, the cost is low, and the battery efficiency can be improved.

The invention discloses a back contact solar cell and a preparation method thereof, and relates to the technical field of solar cells. The back contact solar cell comprises a silicon substrate, a plurality of first doped regions, a plurality of second doped regions and a plurality of edge doped regions are alternately arranged on the back surface of the silicon substrate, and each edge doped region comprises a first edge region and a second edge region; the first edge region is located between the first doped region and the second edge region; the tunneling passivation layer is arranged in the first doped region; the first hydrogenated amorphous silicon layer is arranged in the second doped region and extends to the second edge region and the first edge region from the second doped region; the doped polycrystalline silicon layer is arranged on the outer side of the tunneling passivation layer and extends to the part, corresponding to the first edge region, of the outer side of the first hydrogenated amorphous silicon layer from the first doped region; the first doped silicon-containing film is arranged on the outer side of the first hydrogenated amorphous silicon layer. According to the embodiment, an isolation region can be omitted, and the passivation effect is improved.

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device capable of improving selector characteristics of a memory cell and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of memory cells. Each memory cell includes: a memory layer; and a selector layer formed over or under the memory layer to select the memory layer. The selector layer includes an amorphous silicon layer having at least one dopant selected from a group including a group 13 element, a group 14 element, and a group 15 element of the periodic table.

Disclosed are a semiconductor device with improved selector characteristics of memory cells, and a method for fabricating the semiconductor device. A semiconductor device includes a plurality of memory cells wherein each of the memory cells includes a memory layer; a selector layer formed in an upper or lower portion of the memory layer to select the memory layer; and a buffer layer directly coupled to an upper or lower portion of the selector layer, wherein the buffer layer includes an amorphous silicon layer including at least one dopant selected from a group including group-13 elements, group-14 elements, and group-15 elements of the periodic table.