5181 results about "Amorphous silicon" patented technology

Embodiments of a gas distribution plate for distributing gas in a processing chamber are provided. In one embodiment, a gas distribution assembly for a plasma processing chamber comprises a diffuser plate with gas passages passing between its upstream and downstream sides and hollow cathode cavities at the downstream side of the gas passages. The downstream side of the diffuser plate has a curvature to improve the thickness uniformity and film property uniformity of thin films deposited by PECVD, particularly SiN and amorphous silicon films. The curvature is preferably described by an arc of a circle or ellipse, the apex thereof located at the center point of the diffuser plate. In one aspect, the hollow cathode cavity volume density, surface area density, or the cavity density of the diffuser increases from the center of the diffuser to the outer edge. Methods for manufacturing such a diffuser plate are also provided.

A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.

Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase metal compound into a process space where the glass substrate having the amorphous silicon formed thereon is disposed, to adsorb a metal nucleus contained in the metal compound into the amorphous silicon layer; a metal nucleus distribution region-forming step of forming a community region including a plurality of silicon particles every metal nucleus in a plane boundary region occupied by the metal compound by a self-limited mechanism due to the adsorption of the metal nucleus; and an excess gas removing step of purging and removing an excess gas which is not adsorbed in the metal nucleus distribution region-forming step.

A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.

Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550° C.; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600° C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700° C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods.

Disclosed is a heat treatment system for semiconductor devices. The heat treatment system is used in a heat treatment process for semiconductor devices, such as a crystallization process for an amorphous silicon thin film or a dopant activation process for a poly-crystalline silicon thin film formed on a surface of a glass substrate of a flat display panel including a liquid crystal display (LCD) or an organic light emitting device (OLED). The heat treatment system transfers a semiconductor device after uniformly preheating the semiconductor device in order to prevent deformation of the semiconductor device during the heat treatment process, rapidly performs the heat treatment process under the high temperature condition by heating the semiconductor device using a lamp heater and induction heat derived from induced electromotive force, and unloads the semiconductor device after uniformly cooling the semiconductor device such that the semiconductor device is prevented from being deformed when the heat treatment process has been finished. The heat treatment system rapidly performs the heat treatment process while preventing deformation of the semiconductor device by gradually heating or cooling the semiconductor device.

A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.

A process for producing electronic device (for example, high-performance MOS-type semiconductor device) structure having a good electric characteristic, wherein an SiO2 film or SiON film is used as an insulating film having an extremely thin (2.5 nm or less, for example) film thickness, and poly-silicon, amorphous-silicon, or SiGe is used as an electrode. In the presence of process gas comprising oxygen and an inert gas, plasma including oxygen and the inert gas (or plasma comprising nitrogen and an inert gas, or plasma comprising nitrogen, an inert gas and hydrogen) is generated by irradiating a wafer W including Si as a main component with microwave via a plane antenna member SPA. An oxide film (or oxynitride film) is formed on the wafer surface by using the thus generated plasma, and as desired, an electrode of poly-silicon, amorphous-silicon, or SiGe is formed, to thereby form an electronic device structure.

A system for x-ray fluoroscopic imaging of bodily tissue in which a scintillation screen and a charge coupled device (CCD) is used to accurately image selected tissue. An x-ray source generates x-rays which pass through a region of a subject's body, forming an x-ray image which reaches the scintillation screen. The scintillation screen re-radiates a spatial intensity pattern corresponding to the image, the pattern being detected by the CCD sensor. In a preferred embodiment the imager uses four 8×8-cm three-side buttable CCDs coupled to a CsI:T1 scintillator by straight (non-tapering) fiberoptics and tiled to achieve a field of view (FOV) of 16×16-cm at the image plane. Larger FOVs can be achieved by tiling more CCDs in a similar manner. The imaging system can be operated in a plurality of pixel pitch modes such as 78, 156 or 234-μm pixel pitch modes. The CCD sensor may also provide multi-resolution imaging. The image is digitized by the sensor and processed by a controller before being stored as an electronic image. Other preferred embodiments may include each image being directed on flat panel imagers made from but not limited to, amorphous silicon and / or amorphous selenium to generate individual electronic representations of the separate images used for diagnostic or therapeutic applications.

A thin film device fabrication method in which a thin film device formed on a substrate are transferred to a primary destination-of-transfer part and then the thin film device is transferred to a secondary destination-of-transfer part. A first separation layer (120) made of such a material as amorphous silicon is provided on a substrate (100) which allows passage of laser. A thin film device (140) such as TFTs are formed on the substrate (100). Further, a second separation layer (160) such as a hot-melt adhesive layer is formed on the thin film devices (140), and a primary destination-of-transfer part (180) is mounted thereon. The bonding strength of the first separation layer is weakened by irradiation with light, and the substrate (100) is removed. Thus, the thin film device (140) is transferred to the primary destination-of-transfer part. Then, a secondary destination-of-transfer part (200) is attached onto the bottom of an exposed part of the thin film device (140) via an adhesive layer (190). Thereafter, the bonding strength of the second separation layer is weakened by such means as thermal fusion, and the primary destination-of-transfer part is removed. In this manner, the thin film device (140) can be transferred to the secondary destination-of-transfer part (200) while maintaining layering relationship with respect to the substrate (100).

A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).

A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

A radiation therapy system that includes a radiation source that moves about a path and directs a beam of radiation towards an object and a cone-beam computer tomography system. The cone-beam computer tomography system includes an x-ray source that emits an x-ray beam in a cone-beam form towards an object to be imaged and an amorphous silicon flat-panel imager receiving x-rays after they pass through the object, the imager providing an image of the object. A computer is connected to the radiation source and the cone beam computerized tomography system, wherein the computer receives the image of the object and based on the image sends a signal to the radiation source that controls the path of the radiation source.

An organic light emitting diode (OLED) display includes at least one shield electrode between a cathode layer and an OLED drive circuit. The OLED drive circuit has at least one thin-film transistor (TFT), and the shield electrode is disposed to correspond to the thin-film transistor and closer to the cathode layer, covering an entire region between the source and drain of the thin-film transistor. The shield electrode is either grounded or tied to the gate of the thin-film transistor, to thereby minimize parasitic capacitances in the pixels of the display to enhance the display performance. The presented architecture enables high density drive circuit integration in amorphous silicon or other technologies, yet preserving a high display aperture ratio.

A silicon solar cell has doped amorphous silicon contacts formed on a tunnel silicon oxide layer on a surface of a silicon substrate. High temperature processing is unnecessary in fabricating the solar cell.

Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homogenized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beam let corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

A method for selectively depositing an amorphous silicon film on a substrate comprising a metallic nitride surface and a metallic oxide surface is disclosed. The method may include; providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, contacting the substrate with silicon iodide precursor, and selectively depositing the amorphous silicon film on the metallic nitride surface relative to the metallic oxide surface. Semiconductor device structures including an amorphous silicon film deposited by selective deposition methods are also disclosed.

A method of improving the stability of organic light emitting diode (OLED) display devices driven by amorphous silicon thin-film transistors, in which the driving circuitry within each sub-pixel includes a driving transistor for driving organic light emitting diode (OLED), a scanning transistor and a storage capacitance. An end of the capacitance is connected to the signal resetting line, which a resetting time pulse of high potential and low potential are supplied. Since the resetting signals within the sub-pixels are synchronized, a single voltage of the resetting signal can control the positive and negative stresses for each transistor in the sub-pixels on the panel.

A method of fabricating a low temperature poly-silicon (LTPS). A plurality of semiconductor heat sinks are formed over a substrate. A buffer layer and an amorphous silicon layer are formed over the substrate and the semiconductor heat sinks. Following that, a laser crystallization process is performed to transform the amorphous silicon layer into a poly-silicon layer.

An electrode for a rechargeable lithium battery which includes a thin film composed of active material that expands and shrinks as it stores and releases lithium, e.g., a microcrystalline or amorphous silicon thin film, deposited on a current collector, characterized in that said current collector exhibits a tensile strength (=tensile strength (N / mm2) per sectional area of the current collector material×thickness (mm) of the current collector) of not less than 3.82 N / mm.

The thin-film transistor of the present invention has at least a semiconductor layer including: on a substrate, a source electrode, a drain electrode, and a channel region; a gate insulating film; and a gate electrode, wherein the semiconductor layer is an oxide semiconductor layer, and wherein the gate insulating film is amorphous silicon including at least O and N, and the gate insulating film has a distribution of an oxygen concentration in a thickness direction so that the oxygen concentration is high in the side of an interface with an oxide semiconductor layer and the oxygen concentration decreases toward the side of the gate electrode.

A method for reducing brightness uniformity variations in an active-matrix OLED display employing amorphous silicon thin-film transistors, by providing an active-matrix OLED display having amorphous silicon thin-film transistors; and deriving a first correction value from a measured or estimated value of light-emitting element performance. Subsequently groups of light-emitting elements are identified, whereupon one or more representative light-emitting elements are selected. Remaining steps include measuring total representative current used by the representative light-emitting elements for each predetermined group of light-emitting element; deriving an estimated second correction value from the first correction value, or the measured or estimated value of light-emitting element performance, and the measured total representative currents for each individual light-emitting elements; and employing the estimated second correction value to correct image signals for the changes in the output of the light-emitting elements and produce compensated image signals.

System and methods for processing an amorphous silicon thin film sample into a single or polycrystalline silicon thin film are disclosed. The system includes an excimer laser for generating a plurality of excimer laser pulses of a predetermined fluence, an energy density modulator for controllably modulating fluence of the excimer laser pulses, a beam homoginizer for homoginizing modulated laser pulses in a predetermined plane, a mask for masking portions of the homoginized modulated laser pulses into patterned beamlets, a sample stage for receivingthe patterned beamlets to effect melting of portions of any amorphous silicon thin film sample placed thereon corresponding to the beamlets, translating means for controllably translating a relative position of the sample stage with respect to a position of the mask and a computer for controlling the controllable fluence modulation of the excimer laser pulses and the controllable relative positions of the sample stage and mask, and for coordinating excimer pulse generation and fluence modulation with the relative positions of the sample stage and mask, to thereby process amorphous silicon thin film sample into a single or polycrystalline silicon thin film by sequential translation of the sample stage relative to the mask and irradiation of the sample by patterned beamlets of varying fluence at corresponding sequential locations thereon.

A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.