924 results about "Amorphous silicon" patented technology

The embodiment of the invention relates to the photovoltaic field, and provides a back contact cell and a manufacturing method thereof, a back contact laminated cell and a photovoltaic module, and the manufacturing method comprises the steps: providing a substrate with a first surface and a second surface which are opposite to each other, and the second surface comprises a first region and a second region which are alternately arranged along a second direction; forming a laminated structure comprising a tunneling layer, a doped polycrystalline silicon layer and a first protection layer which are stacked on the first region; forming an initial second passivation lamination layer which covers the second surface and comprises an intrinsic amorphous silicon film and a doped amorphous silicon film which are stacked; forming a second protection layer on one side, far away from the substrate, of the doped amorphous silicon film; etching the first region by adopting a first laser etching process; and taking the second protection layer on the second region as an etching barrier layer, taking the first protection layer as an etching stop layer, and removing the initial second passivation lamination layer or the second protection layer and the initial second passivation lamination layer remaining on the first region by adopting a first etching solution, thereby at least facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.

The invention discloses a back contact cell and a preparation method thereof, a laminated cell and a photovoltaic module, and belongs to the technical field of photovoltaics, the back contact cell comprises a substrate, the substrate comprises a first region, a second region and a spacer region located between the first region and the second region, and a tunneling oxide layer and a doped polycrystalline silicon layer are arranged in the first region and the spacer region. The doped polycrystalline silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the tunneling oxide layer, the amorphous silicon passivation layer and the doped amorphous silicon layer are arranged in the second region and the spacer region, and the doped amorphous silicon layer is arranged on the surface, deviating from the substrate in the thickness direction, of the amorphous silicon passivation layer. And the amorphous silicon passivation layer in the spacer region is positioned on one side, deviating from the substrate along the thickness direction, of the doped polycrystalline silicon layer. The insulating layer is arranged between the amorphous silicon passivation layer and the doped polycrystalline silicon layer, the insulating layer comprises a first insulating part which extends in the thickness direction and is arranged at the junction position of the second region and the spacer region, the first insulating part can prevent the back contact cell from leaking electricity in the horizontal direction, and the overall electrical performance of the back contact cell is improved.

The invention relates to the technical field of back contact solar cells, in particular to a back contact solar cell with a double-passivation structure and a preparation method thereof, and the front surface of the cell sequentially comprises an antireflection film, a suede structure and an N-type monocrystalline silicon wafer from outside to inside; a back field region on the back surface of the back contact solar cell sequentially comprises a metal electrode, an antireflection film, a second phosphorus-doped polycrystalline silicon layer, a second tunneling oxide layer, a first phosphorus-doped polycrystalline silicon layer, a first tunneling oxide layer and an N-type monocrystalline silicon wafer from outside to inside; the emitter region sequentially comprises a metal electrode, an antireflection film, a transparent conductive film, a boron-doped amorphous silicon layer, an intrinsic amorphous silicon layer and an N-type monocrystalline silicon wafer from outside to inside; the isolation area sequentially comprises an antireflection film, a suede structure and an N-type monocrystalline silicon wafer from outside to inside. A P-type TOPCon structure of an emitter region of the TBC battery is optimized into an intrinsic amorphous silicon + P-type amorphous silicon passivation structure with better passivation performance and contact performance, and the conversion efficiency is improved.

The invention belongs to the technical field of back contact photovoltaic cells, and particularly relates to a back contact photovoltaic cell with high-concentration co-doped regions and a manufacturing method and application thereof.The back contact photovoltaic cell with the high-concentration co-doped regions is characterized in that N-type doped regions and P-type doped regions which are alternately distributed are arranged on the backlight face of an intrinsic amorphous silicon layer, and the high-concentration co-doped regions are arranged between the N-type doped regions and the P-type doped regions; a doping source of the co-doped region comprises doping source phosphorus of the N-type doped region and doping source boron of the P-type doped region, the co-doped region, the doping source of the N-type doped region and the doping source of the P-type doped region form a specific concentration gradient structure, and the specific concentration gradient structure meets the condition that the doping concentration of phosphorus contained in the co-doped region is greater than that of phosphorus contained in the N-type doped region; the doping concentration of boron contained in the co-doped region is greater than the doping concentration of boron in the P-type doped region. The carrier transport and collection efficiency is optimized, the fill factor and open-circuit voltage are improved, the cell conversion efficiency and stability are improved, the preparation process is simple, and multiple times of opening etching are not needed.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact battery and a manufacturing method thereof, a laminated battery and a photovoltaic module, the back contact battery comprises a substrate, the substrate is provided with a first surface side and a second surface side which are opposite to each other along a first direction, and the second surface side comprises first regions and second regions which are alternately arranged along a second direction; the tunneling layer is at least located on the first region; the first doped semiconductor layer is located on the side, away from the substrate, of the tunneling layer; the first transparent conducting layer is located on the side, away from the substrate, of the first doped semiconductor layer, and the surface, away from the substrate, of the first transparent conducting layer is provided with multiple light trapping particles; the amorphous silicon layer is at least located on the second region; the second doped semiconductor layer is positioned on one side, far away from the substrate, of the amorphous silicon layer; the second transparent conductive layer is located on the side, away from the substrate, of the second doped semiconductor layer, a gap is formed between the first transparent conductive layer and the second transparent conductive layer, and at least the light trapping effect and the carrier collection efficiency of the back contact cell are improved.

The invention discloses a preparation method of a passivation contact cell with double tunneling polycrystalline silicon layers. A first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doping p-type amorphous silicon layer, a second tunneling oxide layer, a high-doping p-type amorphous silicon layer and a first silicon dioxide mask layer are sequentially deposited in a p region on the back surface of a silicon wafer; sequentially depositing a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doping n-type amorphous silicon layer, a fourth tunneling oxide layer, a high-doping n-type amorphous silicon layer and a second silicon dioxide mask layer in an n region on the back surface of the silicon wafer; and the p-type amorphous silicon and the n-type amorphous silicon are simultaneously converted into p-type polycrystalline silicon and n-type polycrystalline silicon through high-temperature annealing crystallization treatment, so that the preparation of the p-region and n-region dual-tunneling passivation contact structure of the TBC battery is realized. The doping level and passivation performance of the p-region p-type polycrystalline silicon and the n-region n-type polycrystalline silicon are improved, the conversion efficiency of the TBC battery is improved, the production steps are reduced, and the preparation cost is reduced.

A preparation method of a p-region double-tunneling passivation contact TBC battery comprises the steps that a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doping p-type amorphous silicon layer, a second tunneling oxide layer, a high-doping p-type amorphous silicon layer and a silicon dioxide mask layer are sequentially deposited in a P region on the back face of a silicon wafer, and then the p-type amorphous silicon layer is converted into p-type polycrystalline silicon through high-temperature annealing crystallization treatment. According to the invention, the preparation of the p-region double-tunneling passivation contact structure of the TBC battery is realized, the doping level and passivation performance of p-type polycrystalline silicon in the p region are improved, the conversion efficiency of the TBC battery is improved, and the preparation cost is reduced.

The invention belongs to the field of heterojunction cells, and particularly discloses a heterojunction cell and a preparation method thereof, which are characterized in that heavily doped amorphous silicon is deposited in a corresponding area of a grid line electrode, so that high parasitic absorption, surface dangling bond and interface state density are reduced, and the open voltage and the efficiency of the heterojunction cell are improved. The main technical scheme of the invention is as follows: according to the heterojunction cell, grooves are formed in corresponding areas of grid line electrodes on the front surface and the back surface of an N-type silicon substrate; arranging an intrinsic amorphous silicon layer; the light doping P-type amorphous silicon layer is arranged on the front intrinsic amorphous silicon layer, the light doping N-type amorphous silicon layer is arranged on the back intrinsic amorphous silicon layer, the heavy doping P-type amorphous silicon layer is arranged in a groove corresponding area on the light doping P-type amorphous silicon layer, the heavy doping N-type amorphous silicon layer is arranged in a groove corresponding area on the light doping N-type amorphous silicon layer, and the light doping N-type amorphous silicon layer is arranged in a groove corresponding area on the light doping N-type amorphous silicon layer. The P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are respectively provided with a transparent conductive oxide layer, and the grid line electrodes are arranged on the transparent conductive oxide layers. The invention is mainly used for power generation.

The invention belongs to the technical field of photovoltaic cells, and particularly relates to a back contact photovoltaic cell, a back contact photovoltaic cell assembly and a preparation method, and the method comprises the steps: providing an N-type silicon wafer which is provided with a double-sided texturing structure, and the textured surface is of a pyramid structure after texturing; boron diffusion is carried out on the backlight surface of the silicon wafer to form a P + doping layer, and meanwhile, a lightly doped P-type region is formed on the illuminated surface of the silicon wafer through diffusion and dissipation; performing laser film opening on the backlight surface P + doping layer to form P region and N region structures which are distributed in a staggered manner; depositing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer in the N region, and annealing the tunneling oxide layer and the phosphorus-doped amorphous silicon layer to form an N + polycrystalline silicon layer; printing etching slurry on the surface of the P region, performing etching slurry film opening, removing phosphorosilicate glass and forming an isolation gap between the P region and the N region; and the film is opened by printing etching slurry, so that the suede cannot generate thermal damage.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell with a specific front surface structure and a cell assembly thereof, and the specific front surface structure comprises a tunneling oxide layer and a specific doped amorphous silicon layer which are sequentially arranged on the front surface of a silicon substrate, a low-doped amorphous silicon layer, a high-doped amorphous silicon layer and an oxygen-doped amorphous silicon layer are sequentially arranged in the specific doped amorphous silicon layer along the direction far away from the tunneling oxide layer, and the specific doped amorphous silicon layer is doped with a P element and contains an H element; the P doping concentration C1 of the low-doping amorphous silicon layer and the P doping concentration C3 of the oxygen-doping amorphous silicon layer are respectively smaller than the P doping concentration C2 of the high-doping amorphous silicon layer, and the specific front structure enables the back contact cell to absorb incident light within 400 nm, and the highest absorptivity exceeds 85%. The back contact battery disclosed by the invention can still keep good performance after being exposed to ultraviolet rays for a long time, the UV reliability of the battery is improved, meanwhile, high light transmittance is realized, and relatively high battery efficiency is also realized.

The invention discloses a back contact solar cell and a preparation method thereof, the back contact solar cell comprises a semiconductor substrate, the semiconductor substrate is provided with a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of non-groove areas and a plurality of groove areas, the non-groove areas and the groove areas are alternately arranged on the first surface; a tunneling oxide layer and an N-type doped crystalline silicon layer; a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer; and the isolation structure comprises an isolation layer and an isolation groove. According to the invention, the preparation process window of the back contact solar cell is enlarged, the process difficulty is reduced, and the surface passivation effect of the P region is improved, so that the performance of the solar cell can reach the effect equivalent to that of the existing HBC cell structure.

The invention provides a solar cell and a preparation method thereof. The preparation method of the solar cell comprises the following steps: providing a silicon substrate with first doping atoms of a first conductive type; a first tunneling oxide layer and an intrinsic polycrystalline silicon layer are formed on the back face of a silicon substrate, second doping atoms with the conduction type opposite to that of the first doping atoms are diffused into the silicon substrate at a first temperature, and a first doping layer of a second conduction type is formed on the side, close to the back face, of the silicon substrate, converting the intrinsic polycrystalline silicon layer into a first doped polycrystalline silicon layer of a second conductive type; removing the first doped polycrystalline silicon layer; and growing an intrinsic amorphous silicon layer on one side, opposite to the silicon substrate, of the first tunneling oxide layer, and diffusing second doping atoms into the silicon substrate at a second temperature, the first temperature being higher than the second temperature. According to the preparation method of the solar cell, the passivation performance and the contact performance of the solar cell can be considered at the same time, and the cell conversion efficiency is improved.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell capable of reducing the thickness difference between an N-type region and a P-type region and preparation and application of the back contact cell capable of reducing the thickness difference between the N-type region and the P-type region. Wherein the surface of one side, far away from the crystalline silicon substrate, of the amorphous silicon layer is provided with an N-type region and a P-type region which are alternately formed, the N-type region comprises an N-type doped base layer and an N-type transition layer, and the P-type region comprises a P-type doped base layer and a P-type transition layer; wherein the content ratio of phosphorus to silicon in the N-type doped base layer is smaller than 1, the content ratio of phosphorus to silicon in the N-type transition layer is larger than 1, the content ratio of boron to silicon in the P-type doped base layer is smaller than 1, and the content ratio of boron to silicon in the P-type transition layer is larger than 1. The vertical contact resistance can be obviously reduced while the thickness difference between the N-type region and the P-type region is reduced, the high cell conversion efficiency is obtained, the stability of the cell is improved, and the service life of the cell is prolonged; meanwhile, the risk of film explosion in the subsequent process is reduced, and the edge compounding problem is relieved.

The invention relates to the technical field of solar cells, and discloses a hybrid passivation back contact solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a substrate layer comprising a light receiving surface and a backlight surface, wherein the backlight surface comprises first areas and second areas which are alternately arranged; first passivation contact structures are formed in the first region, each first passivation contact structure comprises a tunneling oxide layer and a doped polycrystalline silicon layer which are arranged in a stacked mode, and an isolation groove exposing the second region is formed between every two adjacent first passivation contact structures; a second passivation contact structure is formed in at least the second area, the second passivation contact structure comprises an intrinsic amorphous silicon layer and a doped amorphous silicon layer which are arranged in a stacked mode, the intrinsic amorphous silicon layer further covers part of the doped polycrystalline silicon layer of the first area, and the doped amorphous silicon layer covers the intrinsic amorphous silicon layer of the second area; the first electrode is connected with the doped amorphous silicon, and the second electrode is connected with the doped amorphous silicon layer. The first passivation contact structure is covered with a single layer of intrinsic amorphous silicon layer, the passivation performance of the surface of the doped polycrystalline silicon layer is effectively improved, and the risk of short circuit conduction is reduced.

The invention provides a preparation method of a surface structure of a back contact battery, which relates to the technical field of back contact batteries, and comprises the following steps: S1, carrying out double-sided polishing on the surface of a silicon wafer: firstly carrying out rough polishing, removing a damaged layer on the surface of the silicon wafer, then cleaning with acid and ozone, then carrying out fine polishing, then cleaning with a mixed solution of hydrogen peroxide and alkali, and then carrying out acid pickling with ozone, then cleaning with a mixed solution of acid and hydrogen peroxide, and finally washing and drying; sequentially depositing a tunneling oxide layer and amorphous silicon on a single surface at high temperature; and performing high-temperature diffusion on the surface to form a crystallized first semiconductor region and a mask layer BSG. According to the invention, the specific suede structure is formed on the front surface, and the polished surface is formed on the back isolation base region, so that high reflectivity of the back isolation base region is ensured, the specific suede structure on the front surface can be independently designed, and meanwhile, a double-surface ozone oxidation process is added; therefore, the open-circuit voltage and the short-circuit current of the cell are improved, and the photoelectric conversion efficiency of the cell is improved.

The invention discloses a secondary texturing method, a monocrystalline silicon wafer and a solar cell, the textured monocrystalline silicon wafer is immersed in a secondary texturing solution, and texturing is carried out for 100-200 s at 55-70 DEG C, so that the textured structure of the monocrystalline silicon wafer comprises a pyramid with the bottom edge length of 2-7 [mu] m, the top of the pyramid is round and full, the pyramid is overlooked, and the textured structure of the monocrystalline silicon wafer is obtained. And the side surface of the tower is provided with a step-shaped microstructure which is transited to the tower top layer by layer. The textured structure prepared by the method disclosed by the invention is beneficial to uniform growth of the amorphous silicon film, the passivation quality of amorphous silicon is improved, the service life of a carrier is prolonged, the light trapping effect is improved, and the reflectivity of a silicon wafer is reduced. Meanwhile, the prepared suede structure has a larger specific surface area, so that the contact area of the low-temperature conductive silver paste and the silicon wafer is larger, and the silver paste and the silicon wafer have better ohmic contact; the step-shaped microstructure of the tower surface enables the adhesive force of the silver paste to be increased on the surface of the pyramid, the width of the grid line can be reduced, the shading area and the silver paste consumption are reduced, and the purposes of reducing cost and improving efficiency of the HJT battery are achieved.

The invention relates to the technical field of photovoltaic cells, and discloses a PN junction of a photovoltaic cell, a preparation method of the PN junction and a preparation method of the photovoltaic cell. According to the preparation method of the PN junction, a thickened first intrinsic amorphous silicon layer is formed on the back surface of a silicon wafer, and then the first intrinsic amorphous silicon layer in a P region is thinned to a normal thickness through patterning, so that a thickness difference is formed between the first intrinsic amorphous silicon layers in an N region and the P region; the thickness difference is used for controlling the boron doping concentration of the boron-doped polycrystalline silicon layers of the N region and the P region (the larger the thickness of the intrinsic amorphous silicon layer is, the smaller the boron doping concentration is); thus, the doping concentration of the N-region boron-doped polycrystalline silicon layer can be reduced to reduce the etching difficulty, the high doping concentration of the P-region boron-doped polycrystalline silicon layer can be maintained, double masks are not needed, the productivity is improved, the problems of recombination, poor electrode preparation and the like caused by the height difference of the N-region and P-region doped polycrystalline silicon layers are solved, the manufacturing cost is low, and the yield is high. And compounding caused by mutual doping is avoided, and the electrical performance of the battery is improved.

The invention provides a solar cell and a preparation method thereof, and a photovoltaic module, and the solar cell comprises a semiconductor substrate; the intrinsic amorphous silicon layers are positioned on the front surface, the back surface and the side surfaces of the semiconductor substrate; the doping layer is positioned on the intrinsic amorphous silicon layer; the doping layer is located on the front side and the back side of the semiconductor substrate, the transparent conducting layer is located on the doping layer, the transparent conducting layer at least covers the front side and the back side of the semiconductor substrate, and the transparent conducting layer located on the front side of the semiconductor substrate and the transparent conducting layer located on the back side of the semiconductor substrate are disconnected.

The invention relates to the technical field of photovoltaic cells, and discloses a selective passivation contact structure, a preparation method thereof and application of the selective passivation contact structure to preparation of a selective TOPCon cell. The method comprises the steps that a first tunneling oxide layer, first thin intrinsic amorphous silicon with the high crystallization rate and second thick intrinsic amorphous silicon with the low crystallization rate are sequentially prepared on the back face of a silicon wafer; boron diffusion doping is carried out, so that the first boron-doped polycrystalline silicon and the second boron-doped polycrystalline silicon have difference in doping concentration and crystallization rate; in the alkali etching process after laser patterning, first boron-doped polycrystalline silicon and a first tunneling oxide layer in a back non-electrode contact area are reserved by utilizing the etching rate difference of an alkaline solution on BSG and two layers of boron-doped polycrystalline silicon with different doping concentrations and crystallization rates; and the first tunneling oxide layer, the first boron-doped polycrystalline silicon and the second boron-doped polycrystalline silicon in the back electrode contact region are reserved. According to the method, the process steps can be simplified, parasitic absorption and recombination are reduced, passivation and transverse transmission are improved, and the cell efficiency is improved.

The invention discloses an amorphous silicon passivation layer, a preparation method thereof and a heterojunction battery, and relates to the technical field of batteries, the preparation method comprises the following steps: depositing a first passivation layer on a crystalline silicon substrate by using a first reaction gas, the first reaction gas comprising hydrogen and silane, the flow ratio of hydrogen to silane being (1: 10)-(20: 1); a second reaction gas is adopted to deposit a second passivation layer on the first passivation layer, the second reaction gas comprises hydrogen and silane, and the flow ratio of the hydrogen to the silane is larger than 3: 1 and larger than the flow ratio of the hydrogen to the silane in the first reaction gas; in the step S1, reverse bias voltage is applied to the crystalline silicon substrate, so that the surface potential of the crystalline silicon substrate is below 0.5 eV; in the step S2, bias voltage is applied to the crystalline silicon substrate so as to increase the surface potential of the crystalline silicon substrate. According to the crystalline silicon substrate passivation film prepared by the preparation method, the stability, the electrical performance and the heterogeneous interface passivation performance of a material are improved, and the efficiency and the long-term stability of a heterojunction battery are improved.

To provide a technology capable of reducing the occurrence of seams when filling a recessed portion with a silicon nitride film.SOLUTION: A film formation method according to an embodiment of the present disclosure includes the steps of (a) preparing a substrate having a recess on its surface, (b) forming a silicon nitride film in the recess, (c) forming an amorphous silicon film in the recess, (d) removing the amorphous silicon film, and (e) filling the recess with a silicon nitride film after step (d), and the amorphous silicon film is formed to have a lower step coverage than the silicon nitride film, and step (c) is performed one or more times during step (b).SELECTED DRAWING: Figure 10

The present invention provides a multi-layer doping source structure, and a high-quality emitter and a controllable preparation method therefor. The multi-layer doping source structure comprises a dielectric layer, a nitrogen silicide layer and a doping source layer, which are stacked on the front surface of a crystalline silicon substrate, wherein the dielectric layer is a silicon oxide film or a silicon oxynitride film, the doping source layer is boron-doped amorphous silicon doped with functional elements or phosphorus-doped amorphous silicon doped with functional elements, and the functional elements doped in the doping source layer are carbon and / or nitrogen. In the present invention, the doping source structure is composed of the dielectric layer, a nitrogen silicide and boron- / phosphorus-doped amorphous silicon doped with functional elements; the multi-layer doping source structure has both a strong laser absorption capability and a high boron or phosphorus doping concentration, thereby facilitating a reduction in the laser power and the illumination time required by a laser selective emitter technique; moreover, such a multi-layer doping source structure is favorable for reducing the surface boron concentration, decreasing defects and improving the passivation effect of an emitter, and therefore an improvement in battery efficiency can be promoted.

An amorphous silicon layer or an amorphous boron layer may be deposited on a substrate using one or more silicon-containing or boron-containing precursors, respectively. A free radical species is provided from a plasma source or from a controlled reaction chamber atmosphere to convert the amorphous silicon layer into a doped silicon layer with compositionally adjustable properties. An initial layer is deposited on one or more semiconductor device structures having a dielectric layer over a conductive layer. The initial layer may be conformally deposited by a CVD-based process and may include amorphous silicon, doped silicon, amorphous boron, or doped boron.

The invention provides a solar cell and a preparation method thereof, a photovoltaic module and a laminated cell, and relates to the field of photovoltaic technology. The solar cell includes a silicon substrate; along the thickness direction of the silicon substrate, the silicon substrate comprises a light facing surface and a backlight surface which are opposite to each other; the light-facing face and the backlight face are each provided with a suede structure, and the average size of the suede structures of the light-facing face is smaller than that of the suede structures of the backlight face. The whole tunneling oxide layer and the doped polycrystalline silicon layer are sequentially stacked on the light-facing surface; the whole intrinsic amorphous silicon passivation layer and the whole doped amorphous silicon layer are sequentially arranged on the backlight face in a stacked mode. Good passivation effects and anti-reflection effects are obtained on the two sides of the silicon substrate.

The present application discloses a heterojunction solar cell and a preparation method therefor. The preparation method comprises the following steps: cleaning and texturing a silicon substrate; respectively preparing intrinsic amorphous silicon layers on two surfaces of the silicon substrate; preparing an N-type doped layer on a front intrinsic amorphous silicon layer; preparing a P-type doped layer on a back intrinsic amorphous silicon layer; using an RPD device to prepare a back indium-containing TCO seed layer on the P-type doped layer, and using a PVD device to prepare a back indium-free TCO thin film on the back indium-containing TCO seed layer; using the PVD device to prepare a front indium-containing TCO seed layer on the N-type doped layer, and preparing a front indium-free TCO thin film on the front indium-containing TCO seed layer; and respectively preparing back electrodes and front electrodes. According to the present application, the normal operation time and effective operation time of an RPD and PVD combination device can be effectively increased, the effective productivity of the device is increased, and battery manufacturing costs are reduced.

The invention discloses a double-heating-system electronic-grade polycrystalline silicon reduction furnace and a process method thereof, and relates to the technical field of polycrystalline silicon production equipment, and the reduction furnace comprises a cooling liquid inlet and a cooling liquid outlet which are respectively formed in the upper part and the lower part of a microwave window; a microwave emission branch pipe is fixedly arranged on the outer side of each microwave window, and each microwave emission branch pipe is connected with the microwave emitter through a microwave transmission header pipe; the method comprises the following steps: S1, starting the furnace; s2, early growth stage of the silicon rod; s3, middle growth stage of the silicon rod; s4, later growth stage of the silicon rod; and S5, blowing out the furnace and cooling. The double-heating-system electronic-grade polycrystalline silicon reduction furnace has the beneficial effects that silicon rods with larger diameters can be produced, and the yield of a single furnace is remarkably increased; the quality of the silicon rod is improved, and the high quality requirement of electronic-grade polycrystalline silicon is met; according to the process method disclosed by the invention, the utilization rate of raw materials is increased to 89% or above, the generation amount of amorphous silicon powder is reduced to 7.2 kg / furnace or below, and the energy consumption of a unit silicon rod is reduced.

The embodiment of the invention provides an electrocardio main cable based on a multi-layer heterogeneous shielding structure and a manufacturing method of the electrocardio main cable, and relates to the field of cables. Comprising a wire core group, a composite shielding layer structure and an outer sheath, the composite shielding layer structure and the outer sheath sequentially wrap the wire core group, the wire core group comprises a plurality of twisted pairs, and each twisted pair is formed by asymmetrically twisting a signal wire and a ground wire; the composite shielding layer structure is composed of a plurality of composite shielding sections which are arranged at intervals along the axial direction of the cable, and a resistive material is filled between the adjacent composite shielding sections; the composite shielding section sequentially comprises a spiral copper foil layer, a silver polyester braid layer and an amorphous silicon carbide coating from inside to outside, and the spiral copper foil layer wraps the outside of the multiple groups of twisted pairs; and the outer sheath is coated outside the amorphous silicon carbide coating. According to the invention, broadband shielding compatibility and pure physical structure noise reduction can be realized, the noise reduction effect is improved without additional electronic components, and the cable is light and low in cost.

The invention provides a method for testing the contact resistance of a solar cell film, which comprises the following steps of: preparing a plurality of multi-layer stacked test samples with different thicknesses, and alternately depositing an amorphous silicon film and a transparent conductive oxide film on a glass substrate of each sample to form a horizontal laminated structure; respectively arranging silver electrodes on the left side and the right side of each sample for performing voltage-current volt-ampere test, and recording the total resistance of each sample in a specified voltage range and the change condition of the total resistance along with the thickness of the film layer; electrode contact resistance is measured and deducted; reversely deducing the resistance value when the thickness of the film layer is 0 through an extrapolation method to obtain the contact resistance between the film layers; and calculating the contact resistance of a single interface according to the number of contact interfaces of the amorphous silicon film and the transparent conductive oxide film in the sample. The method is suitable for a test system under different manufacture procedures and thickness changes, and quantitative extraction of the contact resistance between the amorphous silicon and the TCO is achieved.

The invention relates to a solar cell and a preparation method thereof, the solar cell comprises a semiconductor substrate, a first polarity structure, a second polarity structure and a mixed passivation structure, and the semiconductor substrate comprises a first surface with a first region and a second region which are adjacently arranged; the first and second polar structures are respectively positioned in the first and second regions; the mixed passivation structure comprises a dielectric passivation layer which is located in the first region and comprises a first part covering the top surface of the first polar structure and a second part covering the side wall, close to the second polar structure, of the first polar structure; the intrinsic passivation layer comprises a third part located between the semiconductor substrate and the second polar structure and a fourth part located on the side wall, close to the first polar structure, of the second polar structure, and the fourth part and the second part are in contact overlapping in the direction perpendicular to the semiconductor substrate. According to the solar cell and the preparation method thereof, the problem of insufficient boundary passivation in a whole-surface amorphous silicon deposition process is avoided, and the device performance is improved.

Disclosed are a semiconductor device having improved selector characteristics of a memory cell and a method for manufacturing the same. The semiconductor device includes a plurality of memory cells, where each of the memory cells includes: a memory layer; a selector layer formed in an upper portion or a lower portion of the memory layer to select the memory layer; and a buffer layer directly coupled to an upper portion or a lower portion of the selector layer, where the buffer layer includes an amorphous silicon layer including at least one dopant selected from a group including Group 13 elements, Group 14 elements, and Group 15 elements of the periodic table.