14146 results about "Transistor" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

A mixed-signal in-memory computing sub-cell requires only 9 transistors for 1-bit multiplication. In one aspect, a computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain.

A power supply control device includes: an output stage circuit having a high-side transistor provided between an application terminal of an input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal; a high-side driver; a low-side driver; a switching control circuit for controlling on / off state of the high-side and low-side transistors using the low-side and high-side drivers; a boot terminal for applying a boot voltage; a rectifying element for supplying a charging current to a boot capacitor during an on period of the low-side transistor; a reverse current detection circuit for detecting a specific reverse current state in which a reverse current flows from an output terminal to which the output voltage is applied, toward the low-side transistor via the coil and the switch terminal; and a monitor circuit for monitoring a height of the boot voltage.

The invention belongs to the technical field of semiconductor design automation, and provides a standard cell physical layout generation method and related equipment. The method comprises the steps of obtaining design data of a standard unit to be designed and multi-patterning process constraint parameters under a target process; according to the design data and the multi-patterning process constraint parameters, a transistor in a to-be-designed standard cell is arranged, in the arrangement process, folding and / or source-drain sharing are / is dynamically carried out on the transistor in the to-be-designed standard cell, and the feasibility of a gate cutting process and a contact through hole cutting process is synchronously detected; and after the layout of the transistors in the standard unit to be designed is completed, wiring is carried out on the standard unit to be designed by adopting a multi-network synchronous optimization strategy so as to generate a standard unit physical layout, and in the wiring process, sign-off data is fused so as to optimize wiring. Through the technical scheme provided by the invention, the generation efficiency of the standard cell physical layout can be improved.

A semiconductor device includes a semiconductor layer having first and second principal surfaces, an insulated gate bipolar transistor (IGBT) region formed in the semiconductor layer, and a diode region formed adjacent to the IGBT region in a first direction. A plurality of gate trenches are arranged in the IGBT region and extend in a second direction intersecting the first direction. Each trench includes a gate conductive layer embedded through a gate insulating layer, and unit cells are defined between adjacent trenches. An emitter region is formed on the first principal surface of each unit cell. The emitter region of a unit cell located closer to the diode region has a smaller area than the emitter region of a unit cell located farther from the diode region.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A control method and system for a resonant converter. The control method for a resonant converter comprises: in each switching cycle, determining a target power value on the basis of an input power control amount and a compensation amount corresponding to a bridge leg (S101); on the basis of the target power value, an input voltage, circuit parameters of the resonant converter, and the current operating mode of a full-bridge inverter module, determining a target slope control amount corresponding to a counter which corresponds to a switching transistor (S102); determining a comparison threshold on the basis of the target slope control amount, the current count value of the counter which corresponds to the switching transistor, and a DC bias voltage of a resonant capacitor corresponding to the current operating mode, wherein the counter starts counting using the DC bias voltage as an initial value in each switching cycle until the actual voltage of the resonant capacitor is equal to the comparison threshold (S103); and determining a control signal on the basis of the actual voltage of the resonant capacitor and the comparison threshold, and controlling the switching transistor on the basis of the control signal (S104).

A gate driving circuit includes a plurality of stages, wherein each of the plurality of stages includes transistors that control the voltages of control nodes by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces leakage current of a first control node.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

A semiconductor device includes a foundation layer and a transistor layer. The foundation layer is based on single-crystalline silicon carbide and includes a current propagation region of a first conductivity type and a non-depletable shielding structure of a second conductivity type. The transistor layer is based on epitaxially grown single-crystalline silicon carbide and includes a transistor cell (TC) configured to control a current through the current propagation region. The transistor layer is formed on the foundation layer after formation of the shielding structure in the foundation layer such that an epitaxial interface forms between the transistor foundation layer and the layer. The current propagation region extends from the epitaxial interface between neighboring partial regions of the shielding structure. Along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration changes by at least 1e17 1 / cm3 per 0.1 μm at the position of the pn junction.

The embodiment of the invention discloses a bidirectional switching device. The bidirectional switching device comprises a control node, a first load node, a second load node, a main substrate, a main transistor and a substrate potential modulation circuit, the main transistor is a bidirectional conduction transistor and comprises a first gate terminal, a first main electrode terminal, a second main electrode terminal and a first main substrate terminal, the first gate terminal is connected to the control node, and the second gate terminal is connected to the second load node. The first main electrode terminal is connected to a first load node, the second main electrode terminal is connected to a second load node, and the first main substrate terminal is connected to the main substrate. The substrate potential modulation circuit adjusts the substrate potential of the bidirectional switching device to be always basically consistent with the lower voltage in the voltages at the first main electrode terminal and the second main electrode terminal according to the signals in the first main electrode terminal and the second main electrode terminal. Therefore, the potential floating of the main substrate can be effectively inhibited, and the stability and the performance consistency of the device are improved.

The invention relates to the technical field of transistor component assembling, and discloses a transistor pin sleeve assembling machine which comprises an assembling table and pipe feeding equipment and further comprises an assembling module, a pipe feeding frame is fixedly installed at the top of the assembling table, the pipe feeding equipment is arranged at the top of the pipe feeding frame, and an assembling frame is fixedly installed at the top of the assembling table; the assembling module comprises an assembling plate, a spacing plate, a spacing hole, a connecting plate, a clamping plate, a clamping spring, an elastic telescopic plate, a detection plate, a detection spring and a limiting groove, the clamping plate is pulled to move rightwards to break away from contact with the transistor, the transistor is in a suspended state at the moment, and after the transistor breaks away from contact with the clamping plate, the elastic telescopic plate is connected with the detection plate. According to the technical scheme, the transistors fall together under the action of the gravity of the transistors, collective falling is achieved by means of the gravity without depending on additional driving parts, the problem of asynchronous discharging or discharging blockage is solved, and then the assembling efficiency of the transistor pin sleeves is improved.

The invention is suitable for the technical field of resonant converters, and provides a starting control circuit and a resonant converter. The starting control circuit comprises a feedback module, a comparison selection module and a logical operation module, the comparison selection module is electrically connected with the feedback module and the logical operation module, the feedback module is used for being electrically connected with the output end of a resonant conversion circuit in the resonant converter, and the logical operation module is used for being electrically connected with a driving circuit in the resonant converter. According to the starting control circuit provided by the embodiment of the invention, the resonant capacitor voltage constraint threshold value which is gradually enlarged along with the starting process can be constructed, smooth establishment of resonant capacitor direct current bias is realized, the fluctuation amplitude of the resonant capacitor voltage is limited, the problem that the total bus voltage is applied to the resonant inductor in a traditional scheme is avoided, and the starting control circuit is suitable for a high-voltage power supply. Finally, the resonance current peak value in the starting stage is effectively suppressed, and the impact of current stress on core devices such as a switching tube and a resonance inductor is reduced.

A display apparatus is disclosed that includes a first pixel arranged in a row and an odd column, and a second pixel arranged in the row and an even column. Each of the first pixel and the second pixel includes a light-emitting diode, a first transistor configured to output a current corresponding to a data signal, a second transistor transmitting the data signal to the first transistor, and a distribution transistor connected in series between the second transistor and a data line configured to supply the data signal. While the second transistor of the first pixel and the second transistor of the second pixel are simultaneously activated, the distribution transistor of the first pixel and the distribution transistor of the second pixel are sequentially activated.

The invention belongs to the pulse power semiconductor technology, and provides a drift step recovery diode with an anode short circuit structure, a cell of the drift step recovery diode comprises an anode structure, a voltage-withstanding layer structure and a cathode structure from top to bottom, and the anode structure is a mixed anode structure comprising a diode anode part, an NPN transistor part and an isolation and insulation part; the diode anode part, the NPN transistor part and the isolation and insulation part are jointly positioned on the voltage-withstanding layer structure; the anode part of the diode comprises a P-type low-doped layer, a P-type anode region and anode metal from bottom to top; the NPN transistor part comprises a P-type base region and an N-type anode region from bottom to top, and then the P-type base region and the N-type anode region form an NPN transistor together with an N-type drift region; the anode metal is located on the upper surfaces of the P-type anode region of the anode part of the diode, the NPN transistor part and the isolation and insulation part and makes contact with the P-type anode region and the N-type anode region at the same time to form a short circuit point, namely, anode short circuit, and better pulse output characteristics and lower process difficulty are achieved.

The invention discloses a semiconductor structure, a manufacturing method thereof and electronic equipment. The manufacturing method comprises the following steps: forming a first stack structure on a semiconductor substrate; forming a horizontal opening in the first region of the first stack structure, and forming a first vertical opening exposing the semiconductor substrate and a second vertical opening not exposing the semiconductor substrate at two sides of the first region; epitaxially growing using the first vertical opening to form a single crystal active pattern in the horizontal opening; a transistor is formed based on the active pattern. The process difficulty of forming the single crystal active pattern can be reduced, the defect that holes exist in the active pattern can be avoided or reduced, and the electrical performance of the transistor can be improved.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and belongs to the technical field of semiconductors, and the semiconductor device comprises a plurality of layers of storage units which are stacked in the direction perpendicular to a substrate; the memory cell includes: a transistor; the transistor comprises a grid electrode extending in the direction perpendicular to a substrate, a semiconductor layer surrounding the side wall of the grid electrode, and a transition layer surrounding the side wall of the semiconductor layer and making contact with the semiconductor layer. Wherein the transition layer comprises two conductive contact areas which are isolated from each other, and two insulating areas which are positioned between the two conductive contact areas.

The invention discloses an electric energy discharge control device. The energy storage circuit is used for storing potential storage electric energy; the bleeder circuit is used for releasing the potential storage electric energy through a bleeder resistor and a bleeder transistor which are connected in series; the reference voltage setting circuit is used for outputting a reference voltage signal; the bleeder sampling feedback circuit is used for outputting a bleeder sampling feedback electric signal according to the bleeder sampling current of the bleeder resistor; the post-stage voltage feedback circuit is used for outputting a post-stage voltage feedback electric signal according to the potential storage voltage; and the conduction degree of the discharge transistor is controlled according to the post-stage voltage feedback electric signal, the reference voltage signal and the discharge current collection feedback electric signal. The conduction degree of the bleeder transistor is dynamically controlled according to the bleeder current collection feedback electric signal and the post-stage voltage feedback electric signal, so that the change of potential storage electric energy of the energy storage device is dynamically adapted, the bleeder power and the current of the bleeder circuit are stable and controllable, and a higher bleeder rate can be realized under the condition that the bleeder power and the current are kept unchanged.

In a current drive type display device of a variable refresh rate system such as an organic EL display device, an on-bias voltage line for supplying an on-bias voltage Vobs to be applied to a driving transistor in a pixel circuit is provided in a display portion in order to reduce an influence of a hysteresis characteristic of the driving transistor on display luminance. Therefore, when an operation mode is switched from the low refresh mode to the high refresh mode, among pixel circuits in the same column connected to the same data signal line, a pixel circuit to which data is written and a pixel circuit to which the on-bias voltage is applied can be mixed. This enables quick switching from the low refresh rate to the high refresh rate.

The invention relates to the technical field of radio frequency integrated circuits, in particular to a harmonic suppression power amplifier combining a matching network and a feed network, which comprises a transistor, an input matching module, an output matching module, a stabilizing module and a bias module, the input matching module comprises a first parallel resonance unit, the first parallel resonance unit is used for second harmonic suppression, the output matching module comprises a series resonance unit and a second parallel resonance unit, the series resonance unit is used for resonating at a second harmonic frequency and performing low-impedance grounding on the second harmonic, and the second parallel resonance unit is used for resonating at a second harmonic frequency and performing low-impedance grounding on the second harmonic. The second parallel resonance unit is used for resonating at a third harmonic frequency and forms a high-impedance open circuit for the third harmonic, the output matching module is coupled to a drain electrode of the transistor, and the bias module comprises a grid bias sub-module and a drain bias sub-module. The grid bias sub-module is coupled to a connection node of the input matching module and the grid of the transistor, the drain bias sub-module is coupled to the output matching module, and the bias voltage of the transistor is jointly determined by the grid bias sub-module and the drain bias sub-module. The power amplifier has the effect of improving the efficiency level of the power amplifier while realizing harmonic suppression optimization.

The invention relates to the technical field of molds, in particular to a transistor semiconductor multi-point injection packaging mold which comprises upper molds, lower molds, a driving assembly, a slow flow plate and an injection control rod, the upper molds and the lower molds form cavities when closed, a plurality of injection ports are formed in the upper molds, every two adjacent upper mold cavities are communicated through the corresponding injection ports, and the upper mold cavities and the lower mold cavities are communicated through the corresponding injection ports. The flow slowing plate is slidably mounted in the upper mold, the material injection control rod is slidably mounted in the material injection opening, the interior of the material injection control rod communicates with the mold material injection pipe, and the driving assembly controls the flow slowing plate and the material injection control rod to move. When the liquid packaging material is pressurized and injected, the flow slowing plate is used for blocking and slowing down the impact speed of the liquid packaging material, the impact force borne by the connecting gold wire is reduced, wire collapse or stripping of the connecting gold wire is avoided, and the use safety and stability of a product are guaranteed.

The invention discloses a semiconductor device and a manufacturing method thereof, electronic equipment and an access method, the semiconductor device comprises a plurality of vertically stacked memory cells and a vertically penetrating word line, and each memory cell comprises a first transistor and a second transistor. A first semiconductor layer of the first transistor comprises a first semiconductor sub-layer and a second semiconductor sub-layer which are distributed along a second direction, and a word line is arranged between the first semiconductor sub-layer and the second semiconductor sub-layer; the second semiconductor layer surrounds the word line; the first gate electrode partially surrounds the word line and the second semiconductor layer and is in contact with the second semiconductor layer, and the first gate electrode is further distributed on the side wall of the side, facing the word line, of the first semiconductor sub-layer and the side wall of the side, facing the word line, of the second semiconductor sub-layer; the plurality of first gate electrodes of the plurality of vertically stacked first transistors are distributed at intervals in different areas of the side wall of the word line in the direction perpendicular to the substrate. According to the scheme provided by the embodiment, the word line can control on and off of the second transistor and the first transistor, control lines can be reduced, and the device area can be reduced.

The invention provides a carbazole-containing heterocyclic compound and an organic electroluminescent device thereof, and relates to the technical field of organic electroluminescent materials. The carbazole-containing heterocyclic compound provided by the invention has relatively high polarizability, is beneficial to improving the refractive index, and can reduce the total reflection phenomenon during light emission of the device and effectively improve the light extraction efficiency of the device when being applied to a covering layer of the organic electroluminescent device; and meanwhile, the compound has relatively high glass transition temperature and good film-forming property, and can isolate moisture and oxygen, so that the luminous efficiency and the service life of the organic electroluminescent device are further improved and prolonged. The preparation method of the compound is simple, raw materials are easy to obtain, and the compound can be widely applied to the fields of organic thin film transistors, panel display and the like and has good application effects and industrialization prospects.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

The invention provides a robust two-way stacked electrostatic protection circuit, which comprises a two-way stacked electrostatic protection module and a floating charge discharge module, and is characterized in that the two-way stacked electrostatic protection module comprises at least one floating node, and the floating node can accumulate residual charges in the process of normal working of the circuit or electrical characteristic test characterization; the floating charge discharge module is composed of a state control module and a charge discharge module, and the state control module monitors the potential state of a floating node in real time and generates a control signal; the charge discharge module responds to the control signal to conduct and discharge charges accumulated by the floating node, the floating charge discharge module comprises an MOS transistor, the MOS transistor is connected with the first port through the state control module, a source electrode of the MOS transistor is connected with the floating node, and a drain electrode of the MOS transistor is connected with the second port. According to the series high-voltage ESD protection circuit, accumulated charges on the floating node in the series high-voltage ESD protection circuit can be discharged in time.

A display device may include sub-pixels, each sub-pixel including: a first mode sub-pixel having a first viewing angle and including a first emitting element; a second mode sub-pixel having a second viewing angle and including a second emitting element; a driving transistor; a first emitting control line supplying a first emitting control signal; a second emitting control line supplying a second emitting control signal; a first switching transistor supplying a reference voltage to a storage capacitor by being controlled by the first emitting control signal; a second switching transistor supplying a reference voltage to a storage capacitor by being controlled by the second emitting control signal; a first control transistor connecting the first emitting element and the driving transistor by being controlled by the first emitting control signal; and a second control transistor connecting the second emitting element and the driving transistor controlled by the second emitting control signal.

A power amplifier device includes a transistor die with an elongated bondpad coupled to a terminal of an integrated transistor. The device also includes a substrate formed from a stack of alternating dielectric and patterned conductive layers. An elongated die contact is exposed at a first substrate surface and is attached to the elongated bondpad to provide a uniform connection between the die contact and the elongated bondpad. A vertical interconnect structure is connected to the die contact and extends towards the second substrate surface. A circuit includes passive component(s) coupled to the second substrate surface and to the vertical interconnect structure. An encapsulation material layer covers the passive component(s) and the second substrate surface. A plurality of device interconnects are coupled to the substrate, electrically coupled to the power transistor die, and exposed at a contact surface of the power amplifier device.

A gate driving circuit, and a display panel and display device including the gate driving circuit are discussed. The display device in an example includes a first switching transistor connected between an output node of a first signal transmitter from which a first gate signal is output and a first gate line, a second switching transistor connected to the output node of the first signal transmitter, a first diode connected between the second switching transistor and the first gate line, a third switching transistor connected between an output node of a second signal transmitter from which a second gate signal is output and a second gate line, a fourth switching transistor connected to the output node of the second signal transmitter, and a second diode connected between the fourth switching transistor and the second gate line.