16903 results about "Transistor" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

A display device according to one or more embodiments of the present disclosure includes: a display panel including a plurality of pixels; and a panel driver configured to drive the display panel, wherein each of the pixels includes: a first light emitting element having a first viewing angle; a second light emitting element having a second viewing angle; a pixel circuit configured to generate a driving current; a first transistor configured to provide the driving current to the first light emitting element in response to a first select signal; and a second transistor configured to provide the driving current to the second light emitting element in response to a second select signal, and wherein, in a mode switching frame period between a first mode and a second mode, the panel driver is configured to sequentially provide the first and second select signals to the pixels on a row-by-row basis.

A mixed-signal in-memory computing sub-cell requires only 9 transistors for 1-bit multiplication. In one aspect, a computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain.

The present application provides a converter and a chopper transistor blocking control method therefor. According to the chopper transistor blocking control method, when switching transistors in a converter need to be blocked, switching transistors in a primary side circuit connected to a transformer of the converter are blocked, and switching transistors in a secondary side circuit are blocked when the current on a branch where a secondary side winding in the transformer is located is zero, or batch blocking of the switching transistors in the secondary side circuit is completed after the current on the branch where the secondary side winding is located recirculates to zero, thereby avoiding overvoltage damage to the switching transistors caused by the current on the branch where the secondary side winding is located recirculating by means of the junction capacitance of the switching transistors in the secondary side circuit.

A power supply control device includes: an output stage circuit having a high-side transistor provided between an application terminal of an input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal; a high-side driver; a low-side driver; a switching control circuit for controlling on / off state of the high-side and low-side transistors using the low-side and high-side drivers; a boot terminal for applying a boot voltage; a rectifying element for supplying a charging current to a boot capacitor during an on period of the low-side transistor; a reverse current detection circuit for detecting a specific reverse current state in which a reverse current flows from an output terminal to which the output voltage is applied, toward the low-side transistor via the coil and the switch terminal; and a monitor circuit for monitoring a height of the boot voltage.

The invention belongs to the technical field of semiconductor design automation, and provides a standard cell physical layout generation method and related equipment. The method comprises the steps of obtaining design data of a standard unit to be designed and multi-patterning process constraint parameters under a target process; according to the design data and the multi-patterning process constraint parameters, a transistor in a to-be-designed standard cell is arranged, in the arrangement process, folding and / or source-drain sharing are / is dynamically carried out on the transistor in the to-be-designed standard cell, and the feasibility of a gate cutting process and a contact through hole cutting process is synchronously detected; and after the layout of the transistors in the standard unit to be designed is completed, wiring is carried out on the standard unit to be designed by adopting a multi-network synchronous optimization strategy so as to generate a standard unit physical layout, and in the wiring process, sign-off data is fused so as to optimize wiring. Through the technical scheme provided by the invention, the generation efficiency of the standard cell physical layout can be improved.

Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a sacrificial gate structure over a portion of a fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked. The method also includes removing a portion of the fin structure not covered by the sacrificial gate structure, subjecting exposed surfaces of each first and second semiconductor layers to at least one radical species, removing an edge portion of the second semiconductor layers to form a cavity between two adjacent first semiconductor layers, and forming a dielectric spacer in the cavity.

A semiconductor device includes a semiconductor layer having first and second principal surfaces, an insulated gate bipolar transistor (IGBT) region formed in the semiconductor layer, and a diode region formed adjacent to the IGBT region in a first direction. A plurality of gate trenches are arranged in the IGBT region and extend in a second direction intersecting the first direction. Each trench includes a gate conductive layer embedded through a gate insulating layer, and unit cells are defined between adjacent trenches. An emitter region is formed on the first principal surface of each unit cell. The emitter region of a unit cell located closer to the diode region has a smaller area than the emitter region of a unit cell located farther from the diode region.

A stage circuit includes an output unit which supplies a scan signal to an output terminal in response to a voltage of a first node and a second node, an input unit which outputs a carry signal or a start signal input to a first input terminal in response to a clock signal, a first transistor connected between the input unit and the second node and set to a turn-on state during a driving period, and a controller connected between the input unit and the first transistor or between the first transistor and the second node, where the controller controls an electrical connection between the input unit and the second node.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A display substrate and a display device relate to the technical field of display. The display substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a thin film transistor. The display substrate comprises a substrate, a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer, the first conductive layer, the semiconductor layer, the first insulating layer and the second conductive layer are sequentially stacked on one side of the substrate, the first conductive layer is close to the substrate and comprises a data line, and the semiconductor layer comprises a plurality of semiconductor patterns located at different sub-pixels. The semiconductor pattern comprises a source electrode connection region, a first conductor region and a channel region which are arranged along a first direction and are connected in sequence, and the second conductive layer comprises a first switching pattern and a grid electrode; wherein the first insulating layer is provided with a first via hole, the first via hole exposes a part of the data line, the source electrode connecting area and the first conductor area, the data line and the source electrode connecting area are in lap joint with the first switching pattern through the first via hole, and the orthographic projection of the first switching pattern and the orthographic projection of the first conductor area on the substrate are not overlapped.

The invention provides a display device which is characterized in that two cascaded gate drive circuits are spaced by X gate drive circuits, and the phase difference of first clock signals corresponding to the two cascaded gate drive circuits is (X + 1) H, the effective level of a first gate control signal corresponding to the compensation transistor and the effective level of a second gate control signal corresponding to the data transistor are at least partially overlapped; the effective level of a second gate control signal corresponding to the data transistor is located between two first effective levels of a first clock signal applied by a gate drive circuit corresponding to the compensation transistor, and the phase difference between the effective level of the second gate control signal corresponding to the data transistor and one of the two first effective levels is larger than 0 and smaller than (X + 1) H, therefore, in the same sub-pixel, the effective level of the second gate control signal corresponding to the data transistor does not coincide with the moment when the voltage drop of the first gate control signal corresponding to the compensation transistor occurs, and the problem of uneven display is solved.

A control method and system for a resonant converter. The control method for a resonant converter comprises: in each switching cycle, determining a target power value on the basis of an input power control amount and a compensation amount corresponding to a bridge leg (S101); on the basis of the target power value, an input voltage, circuit parameters of the resonant converter, and the current operating mode of a full-bridge inverter module, determining a target slope control amount corresponding to a counter which corresponds to a switching transistor (S102); determining a comparison threshold on the basis of the target slope control amount, the current count value of the counter which corresponds to the switching transistor, and a DC bias voltage of a resonant capacitor corresponding to the current operating mode, wherein the counter starts counting using the DC bias voltage as an initial value in each switching cycle until the actual voltage of the resonant capacitor is equal to the comparison threshold (S103); and determining a control signal on the basis of the actual voltage of the resonant capacitor and the comparison threshold, and controlling the switching transistor on the basis of the control signal (S104).

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

A display device includes a first pixel circuit disposed on a substrate and a first light-emitting diode electrically connected to the first pixel circuit, the first pixel circuit includes a driving transistor including a driving semiconductor layer and a driving gate electrode, a first initialization transistor including a first initialization semiconductor layer and a first initialization gate electrode and electrically connected to the driving transistor, and a first connection electrode electrically connecting the first initialization semiconductor layer to the driving gate electrode, a semiconductor layer including the first initialization semiconductor layer includes a first extension area extending from a channel area of the first initialization semiconductor layer to the first connection electrode, and the first extension area overlaps a first shield layer disposed under the first initialization semiconductor layer and a second shield layer disposed above the first initialization semiconductor layer.

A gate driving circuit includes a plurality of stages, wherein each of the plurality of stages includes transistors that control the voltages of control nodes by a carry signal output from a previous stage and a carry signal output from a next stage, and a transistor that reduces leakage current of a first control node.

The invention discloses a display driving circuit and a display device. The display driving circuit comprises a scanning control module and an output module, the scanning control module comprises a forward control unit, a reverse control unit and a first control node which are symmetrically arranged; wherein the forward control unit comprises a first transistor and a first leakage protection module, and the reverse control unit comprises a second transistor and a second leakage protection module; the forward control unit and the reverse control unit are used for enabling the scanning control module to realize a forward and reverse scanning function according to signals input into the control ends of the transistors, and outputting a first control signal to the output module through a first control node; and the output module is used for performing pull-up control and / or pull-down control according to the first control signal so as to output a driving signal. Therefore, according to the technical scheme, the display driving circuit is optimized, electric leakage can be avoided or electric leakage current can be reduced, and therefore the output stability of the driving signal is ensured.

Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.

The invention relates to the technical field of data processing, and discloses an integrated circuit design optimization method and system based on data mining. The method comprises the following steps: extracting a multi-process node transistor parameter vector set through an EDA tool, performing data enhancement by using a double-layer process perception generative adversarial network to obtain a cross-node circuit sample library, and inputting the sample library into an R-PTT prediction model to obtain a performance prediction matrix; based on the matrix, optimizing through a multi-target genetic algorithm to obtain an optimal device size combination, and finally performing SPICE simulation verification to obtain verified integrated circuit design parameters. According to the method, the problems of data scarcity and poor model generalization ability during cross-process node application of an existing integrated circuit design optimization method based on data mining are solved, and the accuracy and efficiency of design optimization under new process nodes are improved.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

An electronic device of the disclosure includes a plurality of electronic units. Each of the plurality of electronic units includes a pixel circuit and a plurality of tunable circuits. The plurality of tunable circuits is coupled to the pixel circuit. The pixel circuit includes at least one scan transistor, a plurality of de-multiplexer transistors, and a plurality of storage capacitors. The plurality of de-multiplexer transistors is coupled to the at least one scan transistor. The plurality of storage capacitors is coupled to a data line through the at least one scan transistor and the plurality of de-multiplexer transistors.

A semiconductor device includes a foundation layer and a transistor layer. The foundation layer is based on single-crystalline silicon carbide and includes a current propagation region of a first conductivity type and a non-depletable shielding structure of a second conductivity type. The transistor layer is based on epitaxially grown single-crystalline silicon carbide and includes a transistor cell (TC) configured to control a current through the current propagation region. The transistor layer is formed on the foundation layer after formation of the shielding structure in the foundation layer such that an epitaxial interface forms between the transistor foundation layer and the layer. The current propagation region extends from the epitaxial interface between neighboring partial regions of the shielding structure. Along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration changes by at least 1e17 1 / cm3 per 0.1 μm at the position of the pn junction.

The embodiment of the invention discloses a bidirectional switching device. The bidirectional switching device comprises a control node, a first load node, a second load node, a main substrate, a main transistor and a substrate potential modulation circuit, the main transistor is a bidirectional conduction transistor and comprises a first gate terminal, a first main electrode terminal, a second main electrode terminal and a first main substrate terminal, the first gate terminal is connected to the control node, and the second gate terminal is connected to the second load node. The first main electrode terminal is connected to a first load node, the second main electrode terminal is connected to a second load node, and the first main substrate terminal is connected to the main substrate. The substrate potential modulation circuit adjusts the substrate potential of the bidirectional switching device to be always basically consistent with the lower voltage in the voltages at the first main electrode terminal and the second main electrode terminal according to the signals in the first main electrode terminal and the second main electrode terminal. Therefore, the potential floating of the main substrate can be effectively inhibited, and the stability and the performance consistency of the device are improved.

The invention relates to the technical field of transistor component assembling, and discloses a transistor pin sleeve assembling machine which comprises an assembling table and pipe feeding equipment and further comprises an assembling module, a pipe feeding frame is fixedly installed at the top of the assembling table, the pipe feeding equipment is arranged at the top of the pipe feeding frame, and an assembling frame is fixedly installed at the top of the assembling table; the assembling module comprises an assembling plate, a spacing plate, a spacing hole, a connecting plate, a clamping plate, a clamping spring, an elastic telescopic plate, a detection plate, a detection spring and a limiting groove, the clamping plate is pulled to move rightwards to break away from contact with the transistor, the transistor is in a suspended state at the moment, and after the transistor breaks away from contact with the clamping plate, the elastic telescopic plate is connected with the detection plate. According to the technical scheme, the transistors fall together under the action of the gravity of the transistors, collective falling is achieved by means of the gravity without depending on additional driving parts, the problem of asynchronous discharging or discharging blockage is solved, and then the assembling efficiency of the transistor pin sleeves is improved.

The invention is suitable for the technical field of resonant converters, and provides a starting control circuit and a resonant converter. The starting control circuit comprises a feedback module, a comparison selection module and a logical operation module, the comparison selection module is electrically connected with the feedback module and the logical operation module, the feedback module is used for being electrically connected with the output end of a resonant conversion circuit in the resonant converter, and the logical operation module is used for being electrically connected with a driving circuit in the resonant converter. According to the starting control circuit provided by the embodiment of the invention, the resonant capacitor voltage constraint threshold value which is gradually enlarged along with the starting process can be constructed, smooth establishment of resonant capacitor direct current bias is realized, the fluctuation amplitude of the resonant capacitor voltage is limited, the problem that the total bus voltage is applied to the resonant inductor in a traditional scheme is avoided, and the starting control circuit is suitable for a high-voltage power supply. Finally, the resonance current peak value in the starting stage is effectively suppressed, and the impact of current stress on core devices such as a switching tube and a resonance inductor is reduced.