27383 results about "Transistor" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

The invention relates to a reverse polarity protected electronic circuit with a negative and a positive supply voltage line and with an electrical application circuit. The electrical application circuit has a positive and a negative power supply terminal. The reverse polarity protected electronic circuit comprises a reverse polarity protection circuit (1). The reverse polarity protection circuit (1) has a first and a second N-channel enhancement transistor as part of a reverse polarity protection transistor group (17). The first and second N-channel enhancement transistors are electrically connected in anti-series via a center terminal (86) of the reverse polarity protection circuit (1). The reverse polarity protection circuit (1) includes a control device (4) which is connected to the positive and negative supply voltage lines.Only when connected with the correct polarity does the control device (4) switch the first and second N-channel enhancement transistors of the reverse polarity protection transistor group (17) on. The control device (4) includes its own additional control reverse polarity protection circuit (81) which prevents damage to the control device (4) if connected with incorrect polarity, so that the control device (4) does not switch on the first and second N-channel enhancement transistors if connected with incorrect polarity.

The invention relates to a reverse polarity protected electronic circuit with a negative and a positive supply voltage line and with an electrical application circuit. The electrical application circuit has a positive and a negative power supply terminal. The reverse polarity protected electronic circuit comprises a reverse polarity protection circuit (1). The reverse polarity protection circuit (1) has a first and a second N-channel enhancement transistor as part of a reverse polarity protection transistor group (17). The first and second N-channel enhancement transistors are electrically connected in anti-series via a center terminal (86) of the reverse polarity protection circuit (1). The reverse polarity protection circuit (1) includes a control device (4) which is connected to the positive and negative supply voltage lines.Only when connected with the correct polarity does the control device (4) switch the first and second N-channel enhancement transistors of the reverse polarity protection transistor group (17) on. The control device (4) includes its own additional control reverse polarity protection circuit (81) which prevents damage to the control device (4) if connected with incorrect polarity, so that the control device (4) does not switch on the first and second N-channel enhancement transistors if connected with incorrect polarity.

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on / in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

To provide a semiconductor device with excellent electric characteristics.SOLUTION: A transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 thereon, an oxide 230a thereon, an oxide 230b thereon, an oxide 243a and an oxide 243b thereon, conductors 242a and 242b on the oxides 243a and 243b, insulators 272a and 272b on the conductors 242a and 242b, an oxide 230c on the oxide 230b, an insulator 250 thereon, and a conductor 260 existing thereon and overlapping with the oxide 230c. The oxide 230c is in contact with each of side surfaces of the oxides 243a and 243b and side surfaces of the conductors 242a and 242b. In an insulator 274 and an insulator 280 on the transistor 200, regions 241a and 241b with higher nitrogen concentration than the other regions are formed near an interface with the conductors 240a and 240b.SELECTED DRAWING: Figure 1

A display device and its driving method are provided. The display device includes a display panel. The display panel includes pixel circuits arranged in multiple rows. Each pixel circuit includes a light-emitting control transistor and a driving transistor. The light-emitting control transistor is used to control a corresponding light-emitting element to enter a light-emitting stage; and the driving transistor is used to provide a driving current for the corresponding light-emitting element. A driving process of the display panel includes a first stage and a display stage. The first stage is located at least before or after the display stage. In the first stage, at least one of light-emitting control transistors and driving transistors in each row of pixel circuits is turned off. A duration of the first stage is t, and a data refresh frequency of the pixel circuits in the display stage is f, t≤1 / f.

The invention discloses a power supply circuit, a power supply method, a server, a product and a medium, and relates to the technical field of server power supply, the total power demand of the server is dispersed through the parallel design of multiple power panels, the bus current of a single board connected to a first voltage is reduced to the safe bearing range of an MOS tube, the impact risk is reduced, and the service life of the server is prolonged. The electronic fuse is matched with the single-board power to set an overcurrent protection threshold value, and the short-circuit protection response time is shortened; each board is independently provided with a power supply brick to realize second voltage localization conversion and single board output current reduction, a multi-board output end combined power supply design is combined, a heat source is dispersed to eliminate heat accumulation, the through-current capability is multiplied through a parallel path, and the heat dissipation and electrical design feasibility of the circuit board is improved. The technical problems of MOS tube over-limit, overcurrent protection delay, circuit board heat accumulation and difficult through-flow caused by large current brought by a power supply in a high-power server are solved, and the technical effects of enhancing power supply reliability and optimizing energy efficiency are achieved.

The invention discloses a transistor high-power electromagnetic heat model optimization system based on deep learning, and relates to the technical field of electromagnetic heat. Comprising an input module, a deep learning module, a global optimization module, an online adaptive module and a real-time simulation module. The input module obtains various key parameters and constructs a high-dimensional input space; the deep learning module constructs a deep learning model by embedding a physical constraint and uncertainty quantization mechanism; the global optimization module is used for carrying out global search on design parameters, rapidly evaluating a target function by utilizing an agent model, and searching a Pareto optimal solution in a design parameter space; the online adaptive module is used for drift detection and updating; the real-time simulation module simulates an electromagnetic field and a thermal field in real time, and data exchange ensures timely synchronization of boundary data through dynamic scheduling and load balancing; all the modules cooperate with one another through data and feedback, and a complete, closed-loop and continuously self-adaptive updating optimization system is achieved.

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

A display device can include a first mode sub-pixel having a first viewing angle and including a first emitting element, a second mode sub-pixel having a second viewing angle and including a second emitting element, a driving transistor connected to the first emitting element or the second emitting element, a first control transistor configured to connect the first emitting element to the driving transistor by being controlled by a mode selecting signal, a second control transistor configured to connect the second emitting element to the driving transistor by being controlled by the mode selecting signal, and a mode control line configured to apply the mode selection signal to the first switching transistor and the second switching transistor. The first control transistor and the second control transistor are applied with the mode selection signal from the same mode control line.

A voltage mode driver circuit has a first driver slice has a pullup structure that includes a first transistor and a second transistor and a pulldown structure that includes a third transistor and a fourth transistor. The first transistor has a gate that receives a first version of a first data signal. The second transistor has a gate that receives a first version of a second data signal. The third transistor has a gate that receives a second, complementary version of the first data signal. The fourth transistor has a gate that receives a second, complementary version of the second data signal. The first data signal encodes data in a first mode and enables the pullup and pulldown structures in a second mode of operation. The second data signal encodes data in the second mode of operation and enables the pullup and pulldown structures in the first mode of operation.

Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source / drain element of the first transistor to the first interconnect structure. The second contact connects a first source / drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

A light emitting display panel can include a display area including subpixels and a non-display area outside of the display area, in which each of the subpixels includes a first light emitting unit configured to be driven by a first viewing angle control transistor, and a second light emitting unit configured to be driven by a second viewing angle control transistor. Also, a shape of a first lens included in the first light emitting unit is different than a shape of a second lens included in the second light emitting unit, and a polarity type of the first viewing angle control transistor is different than a polarity type of the second viewing angle control transistor.

The invention discloses a dynamic on-resistance test circuit based on a gallium nitride transistor and a test method thereof. Belongs to the technical field of power electronics. The circuit comprises a DPT test circuit, a switch state switching circuit and a clamping circuit, the test method comprises the following steps: monitoring the voltage between test points on the clamping circuit and the current on the coaxial resistor to obtain the on resistance of the to-be-tested tube; the switching between the hard switching test and the soft switching test is realized by changing the switch interface. According to the invention, a gallium nitride transistor and a clamping circuit are introduced into a traditional double-pulse test circuit, and a dynamic on-resistance test function in a soft switching mode and a hard switching mode is integrated. Compared with a traditional testing circuit, the clamping circuit can capture the dynamic on-resistance within nanosecond time delay, meanwhile, the peak of the clamping voltage is greatly reduced, the testing precision is improved, and rapid and accurate measurement of the dynamic on-resistance is achieved.

A display module includes a substrate including a mounting surface and a side surface; a Thin Film Transistor (TFT) layer provided on the mounting surface of the substrate; a plurality of inorganic light emitting diodes mounted on the mounting surface of the substrate; an anisotropic conductive layer provided on an upper surface of the TFT layer and electrically connecting the TFT layer to the plurality of inorganic light emitting diodes; a front cover covering the mounting surface; and a side cover surrounding the side surface. A side end of the front cover extends to a region outside the mounting surface, and the side cover is bonded to a lower surface of the front cover and to the side surface of the substrate which correspond to the region outside of the mounting surface.

A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space extending from a sidewall of the first semiconductor IC chip.

A method for equalizing a data signal includes providing a data signal to a pair of input transistors that provides an output signal, contributing to the output signal, a first current or voltage that has a magnitude determined by a first weighted feedback signal using a first decision-feedback circuit that includes a first pullup circuit coupled to a drain of a first input transistor, and a first pulldown circuit coupled to the drain of the first input transistor, and contributing to the output signal, a second current or voltage that has a magnitude determined by a second weighted feedback signal using a second decision-feedback circuit that includes a second pullup circuit coupled between a drain of a second input transistor and the first voltage rail, and a second pulldown circuit coupled between the drain of the second input transistor and a second voltage rail.

A motor controller for pulse heating of a power battery. The motor controller includes an inverter circuit, the inverter circuit includes three switching transistor bridge arms, two ends of each switching transistor bridge arm are respectively configured to connect to positive and negative electrodes of the power battery through a direct current bus, and bridge arm midpoints of the three switching transistor bridge arms are separately configured to connect to a three-phase winding of a motor. The bridge arm midpoints of the three switching transistor bridge arms are configured to output a three-phase current, the three-phase current is used to generate a pulse alternating current on the direct current bus, and the pulse alternating current is used to heat the power battery. A current of each phase of the three-phase current is a unipolar triangular wave, and a sum of the three-phase current is zero.

The invention discloses a nanosecond-order delay transistor reliability test system and method, and belongs to the technical field of transistor test. The test system is divided into three parts, namely a voltage stress value and stress duration control module, a current control module and a hard switch transient and on-resistance test module. The drain voltage stresses are respectively used for controlling the drain voltage stress value and the drain voltage stress duration of the transistor to be tested; the current during hard switch testing is determined; and the conduction time is long. The test system processes signals through a hardware circuit, can convert an input single-path pulse signal into two paths of inverted pulse signals with dead time, and improves the safety of the test system. The voltage stress duration, the current and the conduction duration of the drain electrode of the transistor to be tested can be flexibly regulated and controlled only by inputting a pulse signal to each of the three modules. Simulation and experiments prove that the measurement delay of switching to the test state after the drain electrode voltage stress is ended is nanosecond magnitude, and the method has important significance for monitoring performance degradation after the transistor drain electrode voltage stress is monitored in real time.

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

A packaged RF transistor amplifier includes an RF transistor amplifier die having a first terminal, a first lead, an integrated passive device that includes a first series microstrip transmission line, a first bond wire coupled between the first terminal and the first series microstrip transmission line, and a second bond wire coupled between the first series microstrip transmission line and the first lead.

The invention provides a preparation method of an island and beam film structure micro differential pressure sensor with an IC (Integrated Circuit), which comprises the following steps: arranging an N-type buried layer, a P-type buried layer and an island film structure on an SOI (Silicon On Insulator) silicon wafer, then connecting the SOI silicon wafer with a double-parabolic silicon wafer, and arranging a medium isolation groove, an N-type buried layer connecting region, a P well, a P-type buried layer connecting region, a sensitive resistor, a P-type base region, an N-type base region, an N-type emitter region and a P-type emitter region on the SOI silicon wafer. According to the invention, the preparation of the complementary bipolar transistor double-buried layer is completed by combining a semiconductor manufacturing technology and an MEMS manufacturing technology under the condition of not using an epitaxial process; the process flow is integrally simplified, and the preparation efficiency is improved.

A power tool device (102) is controlled to emit sounds that can identify the power tool device and / or be used to encode data for acoustic data transmission. Modulating the switching frequency of electronic components (370) (e.g., transistors, semiconductor switched devices) of the power tool device (102) can create an acoustic signature detectable by a microphone-equipped device (104), such as a cell phone, tablet, security camera, or the like. In this way, power tool identification and / or acoustic data transmission can be realized with existing power tool device circuitry and hardware components.

An RF transmitter (1) having a gate-segmented power output stage (2) and a digital driver (5). The gate-segmented power output stage (2) includes a field-effect transistor with a plurality of gate fingers (32) and drain fingers (31) that define a gate periphery. The field-effect transistor comprises a plurality of power output stage segments (3) that each correspond to a respective part of the gate periphery, and that each have a respective power output stage segment input (4). The digital driver (5) has control outputs (6) which are connected to corresponding ones of the respective power output stage segment inputs (4), and is configured for individually switching each of the power output stage segments (3) between an on mode and a cut-off mode in dependence of one or more input signals to obtain a modulated RF carrier signal at an output (7) of the gate-segmented power output stage (2).

Provided is a semiconductor device which includes: a transistor structure; a plurality of 1st metal lines above the transistor structure; and a plurality of 1st vias formed on selected 1st metal lines, respectively, among the plurality of 1st metal lines; a 2nd via formed on a 1st via among the plurality of 1st vias; and a 2nd metal line on the 2nd via, wherein the 1st metal lines are arranged in a 1st direction and extended in a 2nd direction which intersects the 1st direction, and the 2nd metal line is extended in the 1st direction, and wherein the plurality of 1st vias comprise at least one dummy via which is not connected to any metal line thereabove other than an underlying 1st metal line among the selected 1st metal lines.

A power management circuit is disclosed that includes a boost converter, a pass transistor, and an overcurrent detect circuit. The boost converter is configured to convert an input voltage into a first power supply voltage. The pass transistor is configured to transfer the first power supply voltage as a second power supply voltage after a predetermined time from a time point at which the first power supply voltage is activated. The overcurrent detect circuit is configured to perform an overcurrent detect operation by sensing a current flowing through the pass transistor. A display device is also disclosed that includes the power management circuit.

A resonant converter switching between different operational state modes is provided. The resonant converter includes a first transistor, a second transistor, a control circuit, a resonant circuit, a transformer and an output stage circuit. A first terminal of the first transistor and a second terminal of the second transistor are connected to positive and negative terminals of an input voltage source, respectively. A first terminal of the second transistor is connected to a second terminal of the first transistor. The resonant circuit is connected to the second terminal of the first transistor and the transformer. The transformer is connected to a load through the output stage circuit. The control circuit modulates frequencies or duty cycles of conduction time control signals that are outputted to the first and second transistors to different values for switching the resonant converter between the operational state modes.

The invention relates to the technical field of design and application of two-dimensional materials, and discloses a design and simulation method of a two-dimensional semiconductor nanometer transistor, which comprises the following steps: collecting multi-source data of design and simulation of the two-dimensional semiconductor nanometer transistor, and screening through a data quality evaluation model to obtain a layered data structure; constructing and training a Bayesian neural network model; key influence parameters are identified through a multi-scale feature extraction algorithm and a parameter correlation analysis algorithm, and an attention algorithm is applied to pay attention to an important parameter combination; meanwhile, the uncertainty is predicted, a sampling point with the most information content is generated, and a prediction confidence interval is provided; through active learning feedback optimization circulation, high-value data points are selected based on prediction uncertainty for verification, and the model is updated until preset precision or resource constraint is achieved; according to the method, through multi-scale feature representation and parameter correlation analysis, invalid parameter exploration is reduced, and meanwhile, the model interpretability is improved through integrated physical constraint and uncertainty quantification.