325results about "From chemically reactive gases" patented technology

The utility model relates to the technical field of semiconductor material preparation, specifically discloses the inductive heating epitaxial furnace of silicon carbide substrate piece growth epitaxial layer, including support plate, the bottom surface fixed connection of support plate has four support rods, the outer surface fixed connection of support plate has rotary mechanism, the outer surface fixed connection of rotary mechanism has base, the upper surface of base is seted up and places the groove through the pressure sensor in the heating assembly and senses the silicon carbide placed in the placing groove, subsequently passes through the controller control heater operation, transports the heat to the heating pipeline, carries out heating treatment to the heating chamber through the heating pipeline, and then realizes the heating treatment to the silicon carbide substrate piece growth epitaxial layer, through the rotary mechanism drive the silicon carbide rotation placed in the placing groove on the base, sprays the raw material on the silicon carbide again through the growth epitaxial layer mechanism, realizes the silicon carbide substrate piece growth epitaxial layer.

The application discloses a single-crystal diamond substrate surface defect repairing method and a single-crystal diamond substrate. The method comprises the following steps: taking a single-crystal diamond after laser cutting as a substrate, and performing solution cleaning treatment on the substrate; placing the cleaned substrate in an MPCVD device, inputting hydrogen to form a hydrogen plasma, and performing etching activation on the surface of the substrate; inputting a carbon source gas into the MPCVD device, and performing carbon atom pulse deposition on the surface of the etching-activated substrate to repair the surface defects of the substrate. The application realizes effective repair of the surface defects of the single-crystal diamond substrate after laser cutting.

To provide a technique for further reducing a dislocation density in a crystal substrate composed of a group III nitride.SOLUTION: A crystal substrate is a substrate composed of a group III nitride single crystal, a low-index crystal plane most proximate to a principal surface of the substrate is a c-plane, a threading dislocation included in the single crystal and penetrating the c-plane extends in a thickness direction without bending in a direction orthogonal to the thickness direction of the substrate, and a ratio of edge dislocations in the threading dislocations is less than 60%.SELECTED DRAWING: Figure 12

The application provides a thin film with an epsilon phase gallium oxide hetero-epitaxial structure and a preparation method thereof, which comprises, from bottom to top, a substrate layer, a first gallium oxide layer and a second gallium oxide layer; the first gallium oxide layer is an epsilon phase gallium oxide layer doped with magnesium Mg, and the magnesium Mg doping acts as an acceptor type trap in the epsilon phase gallium oxide, effectively compensates for the donor type defects of the epsilon phase gallium oxide, and improves the overall resistivity of the epsilon phase gallium oxide thin film. The preparation method adopts a metal organic chemical vapor deposition method, and the growth temperature of the second gallium oxide layer is higher than that of the first gallium oxide layer; and the molar flow ratio of the magnesium source to the gallium source is controlled to be 0.0001-0.1 during preparation. The application introduces appropriate Mg doping through a nucleation layer stage, so that the Mg acts as an acceptor type trap to compensate for donor type defects, while improving the crystal nucleation quality, reducing dislocations and leakage channels, and realizing the dual optimization of the crystal quality and electrical performance of the epsilon phase gallium oxide thin film, thereby effectively reducing the thin film leakage current and improving the resistivity.

This invention belongs to the field of optical functional thin film materials, specifically relating to a silicon-oxygen-aluminum ternary composite optical coating material and its preparation method. Addressing the problem in existing technologies of achieving high transmittance, high hardness, and corrosion resistance synergistically within a single ternary material system, this invention utilizes a single-crystal thin film with a completely ordered single-phase structure epitaxially grown on a MgAl2O4 spinel single-crystal substrate, co-doped with transition metal ions and protons. Employing a combined laser molecular beam epitaxy and low-temperature proton implantation technique, alternatingly ablates the silicon target, aluminum target, and doped target, and simultaneously irradiating with a low-energy hydrogen ion beam under ultra-high vacuum, atomic-level epitaxial growth and in-situ proton embedding are achieved, resulting in a unified high transmittance, high hardness, and corrosion resistance.

The objective of the invention is to provide an improved solution for realizing semiconductor substrates. [Solution] The present invention relates to a method for manufacturing a semiconductor substrate 100. The method comprises supplying a base substrate 10. The method further comprises growing a first group III nitride semiconductor layer 20 on the base substrate 10 along a growth direction A under a hyperstoichiometric nitrogen supply, wherein the surface 22 of the first group III nitride semiconductor layer 20 includes depressions 24 defined by facets 26 of the first group III nitride semiconductor layer 20 oriented obliquely to the growth direction A. The method further comprises growing a second group III nitride semiconductor layer 30 on the first group III nitride semiconductor layer 20 along the growth direction A, covering the depressions 24. The present invention further relates to a semiconductor substrate 100 preferably manufactured by this method.

The application discloses a growth method for improving pit defects of a silicon carbide epitaxial wafer, and comprises the following steps: cleaning a silicon carbide substrate and placing the substrate in an epitaxial reaction chamber, introducing hydrogen, and performing high-temperature annealing treatment; increasing the hydrogen flow and the reaction chamber temperature, and performing hydrogen etching; reducing or maintaining the reaction chamber temperature, introducing a carbon source and a silicon source, and growing a buffer layer on the substrate surface; maintaining the gas introduction, increasing the reaction chamber temperature, and growing a gradient layer on the buffer layer; reducing the reaction chamber temperature, simultaneously opening a center gas source and an edge gas source, and growing a base epitaxial layer on the gradient layer; maintaining the reaction chamber temperature, adjusting the edge gas source flow to form a gradient flow, and growing a flat epitaxial layer on the base epitaxial layer. Through the substrate pretreatment-low rate epitaxy-high rate flat epitaxy, combined with the gradient process filling process, the application realizes the step-by-step filling and surface flattening of the pit defects, and effectively reduces the number of Pit defects and the epitaxial thickness uniformity.

This application discloses a wafer carrier tray and an epitaxial growth apparatus, relating to the field of semiconductor epitaxial growth technology. By setting the first surface of the wafer carrier tray to support the wafer as a convex structure, the center of the wafer is in direct contact with the center of the first surface of the wafer carrier tray, while there is a gap between the periphery of the wafer and the periphery of the first surface of the wafer carrier tray. This results in the temperature at the periphery of the wafer being lower than the temperature at the center of the wafer, and consequently, the epitaxial growth rate at the periphery is lower than that at the center of the wafer. Ultimately, this yields an epitaxial wafer with a more stable thickness model during the epitaxial growth process, characterized by a higher center and lower edges. This reduces the impact of uneven density distribution of the wafer carrier tray and the wafer's own curvature on the thickness model of the epitaxial wafer, thereby reducing the probability of product scrap due to changes in the thickness model and improving the stability of the epitaxial growth process and product quality.

We provide high-quality silicon carbide epitaxial substrates with a silicon carbide epitaxial layer that has few defects. [Solution] The silicon carbide epitaxial substrate 10 comprises a silicon carbide substrate 20 having a first surface and a silicon carbide epitaxial layer 30 located on the first surface, wherein the first surface 20a is the (000-1)C surface, and the stacking fault density confirmed by photoluminescence imaging on the upper surface 30a of the silicon carbide epitaxial layer is 1.2 cm². -2 The ratio of the stacking fault density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.05%, and the basal plane dislocation density on the first surface of the silicon carbide substrate is 3000 cm². -2 It is less than.

To provide an epitaxial wafer that has a low-defect heteroepitaxial film without depending on the dopant concentration and the kind of a silicon wafer.SOLUTION: An epitaxial wafer has a silicon substrate, and an epitaxial film of semiconductor material different from silicon formed on the substrate. When the film thickness in a wafer center part of the epitaxial film is defined as 1, the film thickness in a wafer outer peripheral part is less than 1.SELECTED DRAWING: Figure 1

The application discloses a light-emitting diode epitaxial wafer and a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer comprises a substrate and a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer arranged on the substrate in sequence, wherein the stress release layer comprises a first sub-layer and a second sub-layer; the first sub-layer is a first Si-doped GaN layer; the second sub-layer comprises alternately stacked AlInGaN layers and second Si-doped GaN layers; the Si doping concentration of the second Si-doped GaN layer is less than the Si doping concentration of the first Si-doped GaN layer; and the Si doping concentration of the first Si-doped GaN layer is less than the Si doping concentration of the N-type GaN layer. By implementing the application, the light-emitting efficiency of the light-emitting diode can be improved.

The application discloses an interface stress regulation type silicon-based PHEMT epitaxial growth method and device, relates to the technical field of electronic components and equipment manufacturing, and comprises the following steps: firstly, performing cleaning, in-situ degassing, surface reconstruction and composite buffer layer deposition on a silicon substrate in sequence to construct a low-defect transition structure; then, based on the same trigger source, curvature, reflection and diffraction signals are synchronously collected, stress deviation modeling and trajectory generation are performed, and process window adaptive control instructions are arranged and generated accordingly; then, the instructions are used to control the deposition sequence and delta doping linkage of each functional layer of the active layer, so that the active layer structure growth is completed; finally, post-processing and multi-index quantitative quality inspection are performed to construct quality inspection grading and abnormal backtracking structure. The application realizes real-time monitoring and dynamic closed-loop regulation of interface stress, significantly reduces the defect density of the epitaxial layer, and improves the consistency and yield of device performance.

To provide an apparatus and method for improving heating uniformity for semiconductor processing in a thermal process chamber.SOLUTION: A process chamber 100b comprises a first window 108, a second window 110, multiple lamp bulbs 141, a substrate support (susceptor 106) disposed between the first and second windows to support the substrate 102, and a spot heating source assembly 170 having a motorized rotatable radiant spot heating source, which is disposed over the first window and on an upper surface of a chamber lid 103B and provides radiant energy through the first window.SELECTED DRAWING: Figure 1B

This method for producing a diamond thin film involves synthesizing a diamond thin film on a base material through a plasma CVD method, wherein a raw material gas containing C, H, and O is supplied to a vacuum vessel in which the base material is disposed, high-frequency current is applied to an antenna that is disposed inside or outside the vacuum vessel and that has a conductor element and a capacitive element which are electrically connected to each other in series to generate inductively coupled plasma inside the vacuum vessel, and the generated inductively coupled plasma is used for the plasma CVD method. When the diamond thin film is being synthesized, the plasma has the following characteristics: the electron temperature is 1.0 eV or more and 2.0 eV or less; the electron density is 1.0 × 1011cm-3 or more and 1.0 × 1012cm-3 or less; and the ion saturation current is 1.0 × 10-4 A or more and 1.0 × 10-2 A or less.

A method for fabricating a semiconductor device includes providing an engineered substrate (ES) [40] having a core [12], an engineered layer (ELY) [44] on the core [12], and a lattice-matched layer (LML) [46] on the engineered layer (ELY) [44]. The method also includes providing a plurality of epitaxial (EPI) layers [42] on the engineered substrate (ES) [40]. The method also includes forming a plurality of device epitaxial (EPI) structures [54] separated by vias [58] in the epitaxial (EPI) layers [42], forming a plurality of connecting metal layers (C-MLs) [62] connecting the device epitaxial (EPI) structures [54], and removing the core [12] of the engineered substrate [40], leaving new device structures [70] connected by the connecting metal layers (C-MLs) [62]. The method can also include attaching a temporary substrate [68], such as a UV release substrate, to the device epitaxial (EPI) structures [54], and performing additional fabrication steps.

The application provides a semiconductor device and a manufacturing method thereof, which comprises a substrate, a first temperature-variable barrier layer located on the substrate, a first temperature-variable recrystallization layer located on the first temperature-variable barrier layer, and a gallium oxide epitaxial layer located on the first temperature-variable recrystallization layer. By forming the temperature-variable barrier layer and the temperature-variable recrystallization layer between the substrate and the gallium oxide epitaxial layer, enough nucleation centers are provided for epitaxial growth of the gallium oxide epitaxial layer, the crystal quality of the gallium oxide epitaxial layer is improved, the defect density of the gallium oxide epitaxial layer is reduced, and a foundation is laid for subsequent manufacturing of power electronic devices.

A processing system applicable for use in semiconductor manufacturing, including a chamber. The chamber including a chamber body at least partially defining an internal volume, one or more windows disposed in the internal volume, a substrate support at least partially disposed in the internal volume, one or more heat sources operable to heat the internal volume, and one or more cooling channels. The one or more cooling channels extend at least partially between the one or more heat sources and the one or more windows. The one or more cooling channels are operable to flow a cooling fluid.

The application provides a passivation device, which comprises a reaction chamber with a process area; a conveying mechanism arranged at the bottom of the reaction chamber and used for conveying materials along a first direction; and a gas supply mechanism arranged at the side of the reaction chamber and located in the process area, wherein the gas supply mechanism comprises a plurality of process nozzles arranged at intervals along the first direction, and the plurality of process nozzles can respectively output different process gases to the materials when the materials move to the process area. During the movement of the materials along the first direction through the process area, the materials will pass through the plurality of process nozzles in sequence, so that the plurality of process nozzles can spray different process gases to the cross section of the materials in sequence, and the plurality of process gases can be alternately sprayed in a single movement of the materials, thereby reducing the process time and improving the production efficiency.

The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.

The present disclosure provides a graphite carrier disc, and relates to the technical field of semiconductors. The graphite carrier disc comprises a graphite cover disc, a bearing surface of the graphite cover disc has a plurality of first grooves, side walls of the first grooves have a plurality of convex structures, and the plurality of convex structures are distributed along a circumferential direction of the first grooves. During growth of an epitaxial wafer, part of the carrier gas flows into a gap region between the side walls of the first grooves and a planetary disc. The plurality of convex structures on the side walls of the first grooves make the carrier gas flowing into the gap region more likely to form a turbulent carrier gas field, the turbulent carrier gas field makes it difficult for by-products of a side reaction to accumulate in the gap region, avoids hindering rotation of the planetary disc, thereby affecting uniformity of the epitaxial wafer, and also prevents part of the accumulated by-products from being thrown onto the epitaxial wafer being grown when the planetary disc rotates, which is conducive to improving crystal quality of the epitaxial wafer.

A method for characterizing a heat treatment chamber may involve training a model using temperature rate of change data from an existing heat treatment chamber. A supervised learning process can label the rate of change data based on the deposition profile on the substrate. The trained model can be used to characterize other chambers, and it can be determined whether the predicted performance will match that of the chamber used to train the model. Temperature data can be obtained and rate of change data derived using an inert process with a carrier gas, without actually depositing layers on the substrate. The rate of change data is provided to the model, and the model can generate component-specific outputs that characterize how well the chamber is predicted to match the characteristic state of the chamber (matching at different times) or match between different chambers.

The application discloses a preparation strategy of a single-layer magnetic cage lattice film material, and belongs to the technical field of nanometer materials.The application comprises the following steps: in an ultrahigh vacuum environment, Nb and Te are evaporated and deposited onto a substrate according to a certain deposition beam flow ratio by using a molecular beam epitaxy process, chemical bonding between the Nb and Te is realized through annealing treatment, and a single-layer magnetic cage lattice NbTe2 film material is obtained.The application realizes the preparation of the single-layer cage lattice NbTe2, and the single-layer cage lattice NbTe2 is subjected to atomic structure and magnetic characterization by means of a characterization system, so that the application has excellent scientific research value and wide application potential, and provides a new platform for in-depth scientific research and exploration of novel quantum physical properties.

This invention relates to the field of synthetic diamond technology, and particularly to a method for epitaxial growth of single-crystal diamond on a micron-sized diamond powder substrate. It employs laser-induced graphitization anchoring technology to generate nano-graphite bonding points in situ at the micron-powder contact points, increasing the seed layer adhesion to over 18N and ensuring the stability of the seed layer during long-term MPCVD growth. A pulsed oxygen-nitrogen alternating doping strategy is used, utilizing nitrogen to promote rapid lateral expansion of the {100} crystal plane while selectively etching non-{100} crystal orientations with oxygen pulses and releasing growth stress in real time, resulting in a {100} texture of over 92% in the obtained thick film. A variable-temperature stress balance growth technology is used to rapidly cycle temperatures to cancel out thermal and growth stresses, producing single-crystal diamond with comprehensive performance close to that of HPHT, at a cost only one-fifth to one-tenth of existing technologies. This provides a new industrial solution for high-power electronic devices, optical windows, and heat sink materials.

The utility model relates to the technical field of electronic new material, provide a kind of MOCVD multi-machine MO source supply system, by setting up gas pipeline by nitrogen to MO source bottle form the TMG carrier gas carrying trimethyl gallium, trimethyl gallium passes through TMG carrier gas and enters the condenser in water tank by gas pipeline, part TMG carrier gas after condensation by condenser enters MOCVD machine platform by supply pipeline, so as to realize the supply of MO source to MOCVD machine platform, and the trimethyl gallium condensed into liquid is refluxed into MO source bottle by reflux pipeline and continues to use.Water tank is pumped by water pump by being communicated with machine platform sink, water tank is arranged in machine platform sink by overflow port, and water is arranged in machine platform sink, so as to realize the water circulation in water tank, to ensure that the water temperature in water tank reaches the requirement, the circulation of water tank water can be realized by the sink of MOCVD machine platform, energy consumption is reduced, and water flow indicator is arranged to observe and monitor water flow condition.

Systems and apparatus for a reduced mass substrate support are disclosed, according to certain embodiments. A front side pocket is provided for support of a substrate, while a backside pocket is provided that reduces the mass of the substrate support. By providing the backside pocket, the mass of the overall substrate support is reduced, providing faster thermal cycling times for the substrate support and reducing the weight of the substrate support for transport. Lift pin systems, according to disclosed embodiments, are compatible with existing pedestal systems by providing a hollow extension from each lift pin hole that extends from a bottom of the backside pocket to provide support for lift pin insertion and operation.

This invention discloses a method for preparing quasi-one-dimensional indium tin sulfide (ITS) nanowire semiconductor materials and their applications, belonging to the field of semiconductor materials and devices. The method includes: weighing high-purity nanoscale In, Sn, and S powders and an iodine transport agent in a specific molar ratio under an inert atmosphere; encapsulating the powders under high vacuum; and then performing chemical vapor deposition (CVD) growth in a dual-temperature zone tube furnace. After cleaning and annealing, high-quality quasi-one-dimensional ITS nanowires are obtained. Furthermore, a single nanowire photodetector can be constructed using dry transfer and standard micro / nano processes. This device utilizes the in-plane optical anisotropy of the ITS nanowires to achieve direct polarization-sensitive detection and imaging in the 265nm solar-blind ultraviolet band without the need for an external polarizer, exhibiting microsecond-level fast light response. This invention solves the problem of the difficult and controllable preparation of high-quality ITS single crystals, providing a new solution for a simplified and low-cost polarization imaging device, with significant application prospects in environmental monitoring, security defense, and other fields.

The application discloses a coating cleaning method, system and equipment for an epitaxial reaction chamber, the method comprising: determining the coating thickness of the epitaxial reaction chamber according to the single-batch wafer processing quantity of the epitaxial reaction chamber and the epitaxial layer thickness of the wafer, then determining the cleaning cycle number according to the coating thickness and the baking cleaning parameters and etching cleaning parameters in single cleaning, and performing coating cleaning on the epitaxial reaction chamber according to the cleaning parameters in single cleaning and the cleaning cycle number, so that the dynamic correlation between the coating thickness and the cleaning cycle number is established, the adaptive adjustment of the cleaning number of the epitaxial reaction chamber is realized, and the cyclic cleaning process of the epitaxial reaction chamber is performed based on the quantitative cleaning number and cleaning parameters, which not only ensures the parameter normalization in each coating cleaning process, but also achieves the balance between complete cleaning of residual coating and resource saving through accurate control of the cycle number, improves the coating cleaning effect and avoids waste of cleaning resources.

The application discloses a bearing structure and an epitaxial equipment, and belongs to the technical field of semiconductor processing equipment. The bearing structure comprises a base, a first connecting part and a transmission shaft assembly. The base comprises a bearing surface for bearing a substrate and a first connecting surface opposite to the bearing surface in a first direction. The first connecting part is arranged on the side of the base away from the bearing surface in the first direction and is connected to the first connecting surface. The transmission shaft assembly is connected to the side of the first connecting part away from the base in the first direction. The first connecting part comprises a first body arranged in a ring shape and a receiving cavity arranged on the inner side of the ring-shaped first body. The first body is arranged between the base and the transmission shaft assembly in the first direction. The material of the first body comprises graphite. The application can reduce the contact area of the first connecting part and the base under the premise of ensuring the maximum shear stress, thereby reducing the heat loss at the connection between the base and the first connecting part and improving the epitaxial yield.