7 results about "Epitaxial silicon" patented technology

In order to suppress the peeling of the annular protrusion formed by epitaxial processing, in an epitaxial silicon wafer (100) having a silicon epitaxial layer (2) on the main surface of a silicon wafer (1) having a chamfer (13), the aforementioned silicon wafer (1) contains boron and has a resistivity of 5 to 30 mΩ•cm. The resistivity of the aforementioned silicon epitaxial layer (2) is higher than that of the aforementioned silicon wafer 1. The thickness of the aforementioned silicon epitaxial layer 2 is 0.5 to 15 μm. The surfaces of the chamfer (131) and the end face (133) of the chamfer on the main surface side of the aforementioned silicon wafer (1) are covered by the aforementioned silicon epitaxial layer (2). The chamfer (132) on the back side has an annular protrusion (4). The annular protrusion (4) is formed by the boundary (14) of the region (R1) covered by the aforementioned silicon epitaxial layer (2) and the region (R2) not covered by the aforementioned silicon epitaxial layer (2).

This disclosure provides a susceptor, apparatus and method for epitaxial growth of silicon wafers and an epitaxial silicon wafer, and belongs to the semiconductor manufacturing technology field. The susceptor for epitaxial growth of silicon wafers includes a disc-shaped mounting portion for mounting the silicon wafer and an annular peripheral portion extending radially outward from the disc-shaped mounting portion, wherein the annular peripheral portion has a plurality of spaced groove regions, the groove regions are uniformly distributed along the circumferential direction of the annular peripheral portion, the groove regions exhibit a fan-ring shape, and each of the groove regions has a plurality of pits arranged in an array.

An apparatus comprising a memory array comprising word lines, bit lines, and memory cells, one or more of the memory cells coupled to an associated word line and an associated bit line and comprising active areas and shallow trench isolation (STI) structures adjacent to a base material. The word lines are in the active areas and STI structures and bit line structures are adjacent to the active areas and the STI structures and oriented perpendicular to the word lines. The bit line structures comprise bit lines and bit contacts. Cell contact structures are laterally adjacent to the bit line structures and comprise cell contacts comprising an epitaxial semiconductive material. One or more of the bit contacts and the epitaxial semiconductive material comprise a doped epitaxial silicon material, the doped epitaxial silicon material exhibiting a relatively greater dopant concentration in a [110] crystal orientation than in a [100] or [111] crystal orientation. Methods of forming the apparatus are also disclosed.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single-crystal silicon donor substrate; forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single-crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer; bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single-crystal silicon donor substrate, the handle structure including a single-crystal semiconductor handle substrate; and removing the single-crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

This disclosure discloses a semiconductor structure and its fabrication method. The fabrication method includes: depositing a thin film stacked structure on a substrate; forming a first hole in the thin film stacked structure, the first hole penetrating the thin film stacked structure along the stacking direction of the thin film stacked structure, and exposing the substrate at the bottom of the first hole; growing an epitaxial silicon pillar in the first hole; etching the thin film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through the center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half-pillar and a second half-pillar; forming a first isolation layer, the first isolation layer filling the first trench; forming a first channel region of a first type of doping on the sidewall of the first half-pillar away from the first trench, and forming a second channel region of a second type of doping on the sidewall of the second half-pillar away from the first trench, wherein one of the first type of doping and the second type of doping is N-type and the other is P-type; and forming a gate dielectric layer and a gate conductive layer on the surface of both the first channel region and the second channel region.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

Method for producing a silicon epitaxial wafer (100, 200) comprising the following: a first step in the formation of a first epitaxial silicon layer (12) which contains a surface layer part with an oxygen concentration of 2 × 10 16 atoms / cm² 3 or less, on a silicon wafer (10) which has an oxygen concentration of 2 × 10 17 atoms / cm² 3 or more; a second step of irradiating the surface layer portion of the first epitaxial silicon layer (12) with first ions (18) containing carbon to form a first modification layer (14) in which the carbon is implanted in the surface layer portion of the first epitaxial silicon layer (12); and a third step of forming a second epitaxial silicon layer (16) on the first modification layer (14), wherein after the third step a silicon epitaxial wafer (100, 200) is obtained, wherein a peak concentration of an oxygen concentration profile in the first modification layer (14) 2 × 10 17 atoms / cm² 3 or less and an oxygen concentration of the second epitaxial silicon layer (16) 2 × 10 16 atoms / cm² 3 or less.