46 results about "Epitaxial silicon" patented technology

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

In order to suppress the peeling of the annular protrusion formed by epitaxial processing, in an epitaxial silicon wafer (100) having a silicon epitaxial layer (2) on the main surface of a silicon wafer (1) having a chamfer (13), the aforementioned silicon wafer (1) contains boron and has a resistivity of 5 to 30 mΩ•cm. The resistivity of the aforementioned silicon epitaxial layer (2) is higher than that of the aforementioned silicon wafer 1. The thickness of the aforementioned silicon epitaxial layer 2 is 0.5 to 15 μm. The surfaces of the chamfer (131) and the end face (133) of the chamfer on the main surface side of the aforementioned silicon wafer (1) are covered by the aforementioned silicon epitaxial layer (2). The chamfer (132) on the back side has an annular protrusion (4). The annular protrusion (4) is formed by the boundary (14) of the region (R1) covered by the aforementioned silicon epitaxial layer (2) and the region (R2) not covered by the aforementioned silicon epitaxial layer (2).

A silicon wafer is provided, wherein the dopant is phosphorus, the resistivity is 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or even higher. The carbon concentration near the surface of a silicon wafer is reduced by 10% or more compared to the depth at the center of the wafer.

This disclosure provides a susceptor, apparatus and method for epitaxial growth of silicon wafers and an epitaxial silicon wafer, and belongs to the semiconductor manufacturing technology field. The susceptor for epitaxial growth of silicon wafers includes a disc-shaped mounting portion for mounting the silicon wafer and an annular peripheral portion extending radially outward from the disc-shaped mounting portion, wherein the annular peripheral portion has a plurality of spaced groove regions, the groove regions are uniformly distributed along the circumferential direction of the annular peripheral portion, the groove regions exhibit a fan-ring shape, and each of the groove regions has a plurality of pits arranged in an array.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source / drain regions.

The application discloses an epitaxial silicon wafer pretreatment system and process with high uniformity of passivation layer, a support is fixedly arranged at the bottom of the treatment box, and the application relates to the technical field of silicon wafer pretreatment. The epitaxial silicon wafer pretreatment system and process with high uniformity of passivation layer, through cooperation between the partition plate mechanism, the disturbance plate mechanism, the suction mechanism and the servo motor, the servo motor is started, the suction mechanism is driven to work, the hydrofluoric acid solution in the treatment box is sucked out from the lower part, then is sprayed out through each disturbance plate mechanism, impacts the surface of the adjacent epitaxial silicon wafer, at the same time, the external gas is sucked in, then is blown into the hydrofluoric acid solution through each disturbance plate mechanism, so that the hydrofluoric acid is more uniformly contacted to the surface of the epitaxial silicon wafer, the circulating flowing hydrofluoric acid solution and the inhaled gas are cooperated with each other, the purpose of efficiently removing the oxide and impurities on the surface of the epitaxial silicon wafer is achieved, and the flatness and uniformity of the surface of the epitaxial silicon wafer are ensured.

A workpiece includes a doped p-type substrate, a co-doped P+ epitaxial silicon layer disposed on the doped p-type substrate, and a boron-doped P− epitaxial layer disposed on the co-doped P+ epitaxial silicon layer. The co-doped P+ epitaxial silicon layer is co-doped with germanium and boron. A ratio of the germanium to the boron in the co-doped P+ epitaxial silicon layer may be from 10 to 16.

An apparatus comprising a memory array comprising word lines, bit lines, and memory cells, one or more of the memory cells coupled to an associated word line and an associated bit line and comprising active areas and shallow trench isolation (STI) structures adjacent to a base material. The word lines are in the active areas and STI structures and bit line structures are adjacent to the active areas and the STI structures and oriented perpendicular to the word lines. The bit line structures comprise bit lines and bit contacts. Cell contact structures are laterally adjacent to the bit line structures and comprise cell contacts comprising an epitaxial semiconductive material. One or more of the bit contacts and the epitaxial semiconductive material comprise a doped epitaxial silicon material, the doped epitaxial silicon material exhibiting a relatively greater dopant concentration in a [110] crystal orientation than in a [100] or [111] crystal orientation. Methods of forming the apparatus are also disclosed.

The present application provides an epitaxial silicon wafer and a manufacturing method therefor. During the growth process of an epitaxial layer, the step of growing a homoepitaxial layer on one side of a substrate material in stages comprises: providing a silicon wafer serving as a substrate; depositing a middle epitaxial layer on the silicon wafer substrate, and then performing edge topography flatness compensation on the middle epitaxial layer; and depositing a top epitaxial layer on the middle epitaxial layer. The method comprises at least one stage I and a stage II.

An epitaxial deposition device of a large-size silicon wafer comprises a graphite base and a nozzle arranged in the middle of the graphite base, multiple layers of heat insulation rings are arranged on the graphite base and located on the periphery of the nozzle at intervals, and the heat conductivity of the heat insulation rings is different. According to the utility model, the influence of thermal radiation of the graphite base on the nozzle can be effectively isolated, thereby reducing the generation of sediments and improving the surface quality of an epitaxial silicon wafer.

In these embodiments, a semiconductor device includes a substrate having a well structure with n-type doping, and an epitaxial silicon germanium fin formed on the substrate. The epitaxial silicon germanium fin has a lower portion and an upper portion. The germanium content of the lower portion is less than the germanium content of the upper portion. A channel is formed by the epitaxial silicon germanium fin. A gate is formed on the epitaxial silicon germanium fin. Doped source / drain are formed proximate to the channel.

A preheating ring for large-size epitaxial silicon wafer production belongs to the technical field of silicon product manufacturing and comprises an annular main body which comprises an upper surface in contact with reaction gas in a reaction chamber and a lower surface attached to a bearing surface of epitaxial production equipment. The outer edge of the lower surface extends in the direction away from the lower surface to form an annular boss, the upper surface is formed by splicing an inclined face and a horizontal face, the horizontal face is located on the inner side of the upper surface, the inclined face is located on the outer side of the upper surface, the inclined face inclines downwards from inside to outside in the radial direction, and the highest end of the inclined face is flush with the horizontal face. The area, corresponding to an air inlet of the epitaxial production equipment, of the upper surface is a flow guide area, the flow guide area is provided with a plurality of grooves formed in the horizontal plane, and the grooves extend in the radial direction to penetrate through the horizontal plane. Due to the design, reaction gas smoothly circulates at the edge of the annular main body, and the process stability is improved.

The invention provides a process chamber judgment method and device, and belongs to the technical field of semiconductor manufacturing. The process chamber judgment method comprises the following steps: providing a substrate silicon wafer, and measuring metal pollution values of M areas of the substrate silicon wafer to obtain a first measurement result; fixing the position of the V-shaped groove of the substrate silicon wafer, and preparing an epitaxial layer on the substrate silicon wafer through a plurality of process chambers to obtain an epitaxial silicon wafer; measuring the metal pollution values of the M areas of the epitaxial silicon wafer to obtain a second measurement result; measuring the metal pollution values of the M areas of the sample epitaxial silicon wafer to obtain a third measurement result; and determining the process chamber with metal pollution according to the first measurement result, the second measurement result and the third measurement result. According to the method, the source of metal pollution of the epitaxial silicon wafer can be determined, processing can be carried out in time, the abnormal occurrence rate of the epitaxial silicon wafer is reduced, and the quality of the epitaxial silicon wafer and the equipment productivity are improved.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

Method for producing a semiconductor silicon wafer, which is composed of a silicon wafer substrate and a monocrystalline epitaxial silicon layer on it, comprising: a step (S2) of forming a silicon oxide layer with a thickness of at least 300 nm or thicker only on the back side of the silicon wafer substrate by the CVD process at a temperature of not more than 500 °C, wherein the silicon wafer substrate is produced from a monocrystalline silicon ingot grown by the Czochralski process, is doped with phosphorus, has a resistivity set to not more than 1.05 mΩ·cm, and a solid solution oxygen concentration of not more than 0.9×10 18 atoms / cm² 3 exhibits and on whose front surface a monocrystalline epitaxial silicon layer is to be formed; a heat treatment step (S4) after the step of forming the silicon oxide layer, in which the substrate is held in an oxidizing atmosphere at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes; a step (S5) of removing the surface oxide layer, which is formed as a thermal oxide layer on the front surface of the substrate during the heat treatment step, after the heat treatment step; and a step of depositing a monocrystalline epitaxial silicon layer on the substrate after the step of removing the surface oxide layer.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single-crystal silicon donor substrate; forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single-crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer; bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single-crystal silicon donor substrate, the handle structure including a single-crystal semiconductor handle substrate; and removing the single-crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The application relates to an epitaxial layer removal method, a rework method and a semiconductor process method. The epitaxial layer removal method comprises the following steps: providing a substrate, the substrate is provided with a metal structure and an epitaxial layer, the metal structure is located in the epitaxial layer; and removing the epitaxial layer by using a wet etching solution; under the same condition, the removal rate of the wet etching solution to the epitaxial layer is greater than the removal rate of the wet etching solution to the metal structure, and is greater than the removal rate of the wet etching solution to an oxide. The substrate is provided with a metal structure and an epitaxial layer, the metal structure is located in the epitaxial layer, the removal rate of the wet etching solution to the epitaxial layer is greater than the removal rate of the wet etching solution to the metal structure under the same condition, and the metal structure is not seriously damaged when the epitaxial layer is removed by using the wet etching solution, so that the problem that there is no good way to remove the epitaxial silicon when the epitaxial layer on the front surface of the substrate is abnormal can be solved.

In one general embodiment, a process includes a repeated sequence of growing a first layer having a first type of electrically active dopant and growing a second layer having a second type of electrically active dopant, where the first type of electrically active dopant of the first layer is one of either a P-type or an N-type and the second type of electrically active dopant of the second layer is the other one of either the P-type or N-type.

A workpiece includes a doped p-type substrate, a co-doped P+ epitaxial silicon layer disposed on the doped p-type substrate, and a boron-doped P- epitaxial layer disposed on the co-doped P+ epitaxial silicon layer. The co-doped P+ epitaxial silicon layer is co-doped with germanium and boron. A ratio of the germanium to the boron in the co-doped P+ epitaxial silicon layer may be from 10 to 16.

A silicon wafer is provided in which a dopant is phosphorus, resistivity is from 0.5 mΩ·cm to 1.2 mΩ·cm, and carbon concentration is 3.0×1016 atoms / cm3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

[Problem] To provide an epitaxial silicon wafer with low in-plane resistance variation and low distortion, and a manufacturing process for it. [Solution] An epitaxial silicon wafer 1 with a diameter of 300 mm and a thickness of 761 to 795 µm comprises: a bulk silicon substrate 2 doped with boron and exhibiting a resistivity of 8 to 20 mΩ cm; an epitaxial silicon film 3 formed on a front surface 2a of the bulk silicon substrate 2; and a back oxide film 4 formed on a back surface 2b of the bulk silicon substrate 2. The epitaxial silicon film 3 is configured to have a thickness of 1.7 to 2.7 µm, is boron doped, has a resistivity of 8 to 12 Ω cm, and exhibits an in-plane resistivity distribution of 3% or less. The reverse oxide film 4 has a thickness of 50 to 150 nm.

The present disclosure provides an epitaxial growth apparatus and an epitaxial growth method, the epitaxial growth apparatus comprising: a main chamber configured to grow a silicon epitaxial layer on a monocrystalline silicon wafer by chemical vapor deposition to obtain an epitaxial silicon wafer; the auxiliary chamber is configured to generate an oxidation film on the surface of the silicon epitaxial layer of the epitaxial silicon wafer through a dry-oxygen thermal oxidation process; the transmission chamber is connected with the main chamber and the auxiliary chamber; the transmission device is configured to transmit the epitaxial silicon wafer from the main chamber to the auxiliary chamber through the transmission chamber; and the vacuum generator is configured to vacuumize the transmission chamber so as to enable the epitaxial silicon wafer to be transmitted in a vacuum environment.

Epitaxial silicon carbide substrate (100) comprising: a silicon carbide single crystal substrate (10) with a first principal surface (11); and a silicon carbide layer (20) on the first principal surface (11), wherein the silicon carbide layer (20) has a surface in contact with the silicon carbide single-crystal substrate (10) and a second principal surface (12) opposite the surface, the silicon carbide layer (20) comprises a buffer layer (21) in contact with the first principal surface (11), the nitrogen concentration contained in the buffer layer (21) is 5 × 10¹⁷ cm⁻³ or more and 1 × 10¹⁹ cm⁻³ or less, the second principal surface (12) is a plane inclined at a dislocation angle in a dislocation direction relative to a {0001} plane, the second principal surface (12) has defects, and assuming that a defect satisfying the relations of Formula 1 and Formula 2 is a first defect (1), wherein the dislocation angle is θ°,a thickness of the silicon carbide layer in a direction perpendicular to the second principal surface (12) is W µm, a width of the defect in a direction parallel to a direction obtained by projecting the dislocation direction onto the second principal surface (12) is L µm, and a width of the defect in a direction perpendicular to the dislocation direction and parallel to the second principal surface (12) is Y µm, and assuming that a defect with an elongated shape considered in the direction perpendicular to the second principal surface (12) and satisfying the relations of formula 3 and formula 4 is a second defect (2) where a width of the defect in a longitudinal direction of the defect is A µm and a width of the defect in a short direction of the defect is B µm when considered in the direction perpendicular to the second principal surface (12), then a value iswhich is obtained by dividing a number of the second defect (2) by a sum of a number of the first defect (1) and the number of the second defect (2), greater than 0.5: LY≦10.8xWtanθ <L<1.2xWtanθ3<ABL<Wtan θ,

A pretreatment device before large-size epitaxial silicon wafer detection comprises an ozone generator, a constant-temperature water container and a spraying device which are connected in sequence, the constant-temperature water container is a vertical tank, the top of the constant-temperature water container is connected with the spraying device through an exhaust pipeline, and an air inlet header pipe is inserted into the bottom of the constant-temperature water container; the lower end of the gas inlet main pipe is connected with the ozone generator through a gas inlet pipeline, the upper end of the gas inlet main pipe is positioned in the constant-temperature water container and is provided with a plurality of gas inlet branch pipes which are radially distributed, the gas inlet branch pipes are distributed along the horizontal direction, and any gas inlet branch pipe is provided with a plurality of gas nozzles along the longitudinal direction of the gas inlet branch pipe. The device is used for improving the heating effect of ozone, so that the passivation process of epitaxial silicon wafers is stably carried out, and the requirements of large-scale industrial application are met.

[Problem] To provide an epitaxial silicon wafer having small in-plane variation in resistivity and a small amount of warpage, and a method for manufacturing the same. [Solution] An epitaxial silicon wafer (1) having a diameter of 300 mm and a thickness of 761-795 [mu] m comprises: a boron-doped bulk silicon substrate (2) having a resistivity of 8-20 m [Omega] cm; an epitaxial silicon film (3) formed on the front surface (2a) of the bulk silicon substrate (2); and a back surface oxide film (4) formed on the back surface (2b) of the bulk silicon substrate (2). The thickness of the epitaxial silicon film (3) is 1.7-2.7 [mu] m, the resistivity under boron doping is 8-12 [Omega] cm, and the in-plane distribution of the resistivity is 3% or less. The thickness of the back oxide film (4) is 50-150 nm.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

Provided is a method for producing an epitaxial silicon wafer that has a high passivation effect due to hydrogen. This method for producing an epitaxial silicon wafer 100 is characterized by including: a first step of forming a modification layer 14 on a surface layer portion of a silicon wafer 10 by irradiating the surface of the silicon wafer 10 with a beam of cluster ions including ions 12A of SiHx (where x is an integer from 1 to 3) and ions 12B of C2Hy (where y is an integer from 2 to 5); and a second step of forming a silicon epitaxial layer 16 on the modification layer 14. A total dose amount is from 6.00×1013ions / cm2 to 1.00×1015ions / cm2; a dose amount of the C2Hy ions 12B is greater than 1.00×1014ions / cm2 and less than or equal to 3.00×1014ions / cm2; and a ratio [Si / C] of a number of Si atoms to a number of C atoms injected is from 0.3 to 1.6.

The visual inspection detection device comprises a detection table, and a visual inspection table, a first silicon wafer rack, a second silicon wafer rack and a mechanical arm which are arranged on the detection table, the first silicon wafer frame is used for containing silicon wafers to be detected, the second silicon wafer frame is used for containing detected silicon wafers, and the mechanical arm is used for placing the silicon wafers to be detected on the first silicon wafer frame on the visual inspection table and placing the detected silicon wafers on the visual inspection table on the second silicon wafer frame; the visual inspection table comprises a pitching disc and a rotary disc, the pitching disc is hinged to the visual inspection table and can swing back and forth in a pitching mode under the driving of external force, the rotary disc is rotationally arranged on the pitching disc and can rotate under the driving of the external force, and a wafer groove used for containing a silicon wafer is formed in the rotary disc. According to the utility model, visual inspection of detection personnel is facilitated, and the risk of silicon wafer scratch is reduced.

An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

A semiconductor substrate comprising a first epitaxial silicon carbide layer and a second silicon carbide epitaxial layer. At least one semiconductor device is formed in or on the second silicon carbide epitaxial layer. The semiconductor substrate is formed overlying a silicon carbide substrate having a surface comprising silicon carbide and carbon. An exfoliation process is used to remove the semiconductor substrate from the silicon carbide substrate. The carbon on the surface of the silicon carbide substrate supports separation. A portion of the silicon carbide substrate on the semiconductor substrate is removed after the exfoliation process. The surface of the silicon carbide substrate is prepared for reuse in subsequent formation of semiconductor substrates.