82 results about "Epitaxial silicon" patented technology

The invention provides a preparation method of a gate-all-around transistor device and the gate-all-around transistor device. The method comprises the following steps: providing a preset substrate; the preset base comprises a substrate, a plurality of periodically distributed fins located on the substrate and a dummy gate structure located on the fins, and each fin comprises a laminated structure formed by a plurality of sacrificial layers and channel layers which grow alternately; etching the side walls of the two sides of the sacrificial layer to enable the two sides of each sacrificial layer of the laminated structure to be embedded grooves relative to the channel layer; performing epitaxy of a semiconductor material on the two sides of the laminated structure after the groove is formed, so that the groove is filled with the semiconductor material, and epitaxial layers are formed on the two sides of the laminated structure; and epitaxially growing a source electrode and a drain electrode, etching to remove the false gate structure to form a groove, etching to remove the sacrificial layer in the laminated structure to form a channel, and forming a gate structure in the groove and the channel. According to the invention, the two sides of the sacrificial layer can be wrapped with a thick epitaxial semiconductor material, thereby avoiding device failure caused by wrong etching through of the epitaxial silicon layer, and improving the overall yield of products.

A base, device and method for epitaxial growth of a silicon wafer, and an epitaxial silicon wafer. The base for epitaxial growth of a silicon wafer comprises a disc-shaped bearing part used for bearing the silicon wafer; and an annular periphery extending outwards in the radial direction from the disc-shaped bearing part, wherein the annular periphery is provided with a plurality of trench areas which are spaced apart, the trench areas are uniformly distributed in the circumferential direction of the annular periphery and are fan-shaped, and each trench area is provided with a plurality of pits arranged in an array.

The invention relates to the technical field of silicon wafer processing, and discloses a method for growing a single crystal diamond on a silicon wafer, which comprises the following steps of: by taking an atomic lattice of the silicon wafer as a template and the silicon wafer as a substrate, epitaxially growing silicon atoms and carbon atoms layer by layer by using an atomic layer deposition method, epitaxially growing silicon first and then adding carbon layer by layer during deposition, the silicon wafer with the single crystal diamond surface is formed through one hundred to one thousand layers, and the ratio of carbon to silicon is from initial zero to final 100%, so that the silicon wafer with the single crystal diamond surface is obtained. According to the method for growing the single crystal diamond from the silicon wafer, the existing huge silicon wafer industry is used, the silicon wafer serves as a substrate, epitaxial layer by layer is carried out through an atomic layer deposition (ALD) method, gas components of the ALD method are silane diluted by hydrogen and methane, during deposition, epitaxial silicon is carried out firstly, then carbon is added layer by layer, and the single crystal diamond surface silicon wafer is formed after one hundred to one thousands of layers; therefore, the stress of heteroepitaxy can be reduced to the minimum, and the monocrystal diamond can inherit extremely few defects of liquid-phase crystal pulling growth of silicon crystals.

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

In order to suppress the peeling of the annular protrusion formed by epitaxial processing, in an epitaxial silicon wafer (100) having a silicon epitaxial layer (2) on the main surface of a silicon wafer (1) having a chamfer (13), the aforementioned silicon wafer (1) contains boron and has a resistivity of 5 to 30 mΩ•cm. The resistivity of the aforementioned silicon epitaxial layer (2) is higher than that of the aforementioned silicon wafer 1. The thickness of the aforementioned silicon epitaxial layer 2 is 0.5 to 15 μm. The surfaces of the chamfer (131) and the end face (133) of the chamfer on the main surface side of the aforementioned silicon wafer (1) are covered by the aforementioned silicon epitaxial layer (2). The chamfer (132) on the back side has an annular protrusion (4). The annular protrusion (4) is formed by the boundary (14) of the region (R1) covered by the aforementioned silicon epitaxial layer (2) and the region (R2) not covered by the aforementioned silicon epitaxial layer (2).

A silicon wafer is provided, wherein the dopant is phosphorus, the resistivity is 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or even higher. The carbon concentration near the surface of a silicon wafer is reduced by 10% or more compared to the depth at the center of the wafer.

The application discloses a method for forming a hybrid substrate of a SOI wafer. Buried oxide and silicon-on-insulator in some areas are removed, a layer of SiOCN is deposited on a SOI sidewall to protect the silicon-on-insulator sidewall, and then the growth of epitaxial silicon is performed to cause the silicon substrate area to grow to be flush with the silicon-on-insulator area. The SiOCN on the SOI sidewall acts as a protective layer to prevent the growth of epitaxial silicon on the SOI sidewall, thereby preventing the generation of a bulge at a boundary between the SOI area and the silicon substrate area and improving the product yield. Moreover, a SiOCN film may be deposited with high conformality, and the SiOCN deposited on the SOI sidewall has good uniformity, so that the growth of epitaxial Si from the SOI does not occur during subsequent growth of the epitaxial silicon.

This disclosure provides a susceptor, apparatus and method for epitaxial growth of silicon wafers and an epitaxial silicon wafer, and belongs to the semiconductor manufacturing technology field. The susceptor for epitaxial growth of silicon wafers includes a disc-shaped mounting portion for mounting the silicon wafer and an annular peripheral portion extending radially outward from the disc-shaped mounting portion, wherein the annular peripheral portion has a plurality of spaced groove regions, the groove regions are uniformly distributed along the circumferential direction of the annular peripheral portion, the groove regions exhibit a fan-ring shape, and each of the groove regions has a plurality of pits arranged in an array.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source / drain regions.

The application discloses an epitaxial silicon wafer pretreatment system and process with high uniformity of passivation layer, a support is fixedly arranged at the bottom of the treatment box, and the application relates to the technical field of silicon wafer pretreatment. The epitaxial silicon wafer pretreatment system and process with high uniformity of passivation layer, through cooperation between the partition plate mechanism, the disturbance plate mechanism, the suction mechanism and the servo motor, the servo motor is started, the suction mechanism is driven to work, the hydrofluoric acid solution in the treatment box is sucked out from the lower part, then is sprayed out through each disturbance plate mechanism, impacts the surface of the adjacent epitaxial silicon wafer, at the same time, the external gas is sucked in, then is blown into the hydrofluoric acid solution through each disturbance plate mechanism, so that the hydrofluoric acid is more uniformly contacted to the surface of the epitaxial silicon wafer, the circulating flowing hydrofluoric acid solution and the inhaled gas are cooperated with each other, the purpose of efficiently removing the oxide and impurities on the surface of the epitaxial silicon wafer is achieved, and the flatness and uniformity of the surface of the epitaxial silicon wafer are ensured.

A workpiece includes a doped p-type substrate, a co-doped P+ epitaxial silicon layer disposed on the doped p-type substrate, and a boron-doped P− epitaxial layer disposed on the co-doped P+ epitaxial silicon layer. The co-doped P+ epitaxial silicon layer is co-doped with germanium and boron. A ratio of the germanium to the boron in the co-doped P+ epitaxial silicon layer may be from 10 to 16.

An apparatus comprising a memory array comprising word lines, bit lines, and memory cells, one or more of the memory cells coupled to an associated word line and an associated bit line and comprising active areas and shallow trench isolation (STI) structures adjacent to a base material. The word lines are in the active areas and STI structures and bit line structures are adjacent to the active areas and the STI structures and oriented perpendicular to the word lines. The bit line structures comprise bit lines and bit contacts. Cell contact structures are laterally adjacent to the bit line structures and comprise cell contacts comprising an epitaxial semiconductive material. One or more of the bit contacts and the epitaxial semiconductive material comprise a doped epitaxial silicon material, the doped epitaxial silicon material exhibiting a relatively greater dopant concentration in a [110] crystal orientation than in a [100] or [111] crystal orientation. Methods of forming the apparatus are also disclosed.

Provided is a method for producing an epitaxial silicon wafer having a high hydrogen-based passivation effect. This method for producing an epitaxial silicon wafer (100) is characterized by comprising: a first step for irradiating the surface of a silicon wafer (10) with a beam containing cluster ions of SiHx (x is an integer of 1-3) ions (12A) and C2Hy (y is an integer of 2-5) ions (12B), and forming a modified layer (14) on the surface layer portion of the silicon wafer (10); and a second step in which a silicon epitaxial layer (16) is formed on the modified layer (14), the total dose of the silicon epitaxial layer (16) being 6.00 * 1013-1.00 * 1015 ions / cm2 inclusive, the dose of C2Hy ions (12B) exceeding 1.00 * 1014 ions / cm2 inclusive and 3.00 * 1014 ions / cm2 inclusive, and the ratio of the number of implanted Si atoms to the number of implanted C atoms [Si / C] being 0.3-1.6 inclusive.

The present application provides an epitaxial silicon wafer and a manufacturing method therefor. During the growth process of an epitaxial layer, the step of growing a homoepitaxial layer on one side of a substrate material in stages comprises: providing a silicon wafer serving as a substrate; depositing a middle epitaxial layer on the silicon wafer substrate, and then performing edge topography flatness compensation on the middle epitaxial layer; and depositing a top epitaxial layer on the middle epitaxial layer. The method comprises at least one stage I and a stage II.

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

Methods for low temperature selective deposition of epitaxial silicon-containing films and semiconductor devices incorporating the epitaxial silicon-containing films are provided. The method includes etchant-free selective epitaxy of N-type doped silicon including either a soak in a phosphorous source gas or an antimony seed layer. In one or more implementations, an underlying silicon surface is exposed to a pre-soak process performed by exposing the silicon surface to a phosphorous-containing gas, for example, phosphine gas, for a period of time followed by growing the N-doped epitaxial silicon film by co-flowing silicon sources and antimony sources only. The pre-soak / deposition process can be applied repeatedly to achieve desirable stack thickness. In one or more implementations, a seed layer of antimony-doped silicon is formed by co-flowing silicon and antimony source gases followed by co-flowing silicon source gases, antimony source gases, and phosphorous source gases to grow the N-doped epitaxial silicon film.

An epitaxial deposition device of a large-size silicon wafer comprises a graphite base and a nozzle arranged in the middle of the graphite base, multiple layers of heat insulation rings are arranged on the graphite base and located on the periphery of the nozzle at intervals, and the heat conductivity of the heat insulation rings is different. According to the utility model, the influence of thermal radiation of the graphite base on the nozzle can be effectively isolated, thereby reducing the generation of sediments and improving the surface quality of an epitaxial silicon wafer.

In these embodiments, a semiconductor device includes a substrate having a well structure with n-type doping, and an epitaxial silicon germanium fin formed on the substrate. The epitaxial silicon germanium fin has a lower portion and an upper portion. The germanium content of the lower portion is less than the germanium content of the upper portion. A channel is formed by the epitaxial silicon germanium fin. A gate is formed on the epitaxial silicon germanium fin. Doped source / drain are formed proximate to the channel.

A preheating ring for large-size epitaxial silicon wafer production belongs to the technical field of silicon product manufacturing and comprises an annular main body which comprises an upper surface in contact with reaction gas in a reaction chamber and a lower surface attached to a bearing surface of epitaxial production equipment. The outer edge of the lower surface extends in the direction away from the lower surface to form an annular boss, the upper surface is formed by splicing an inclined face and a horizontal face, the horizontal face is located on the inner side of the upper surface, the inclined face is located on the outer side of the upper surface, the inclined face inclines downwards from inside to outside in the radial direction, and the highest end of the inclined face is flush with the horizontal face. The area, corresponding to an air inlet of the epitaxial production equipment, of the upper surface is a flow guide area, the flow guide area is provided with a plurality of grooves formed in the horizontal plane, and the grooves extend in the radial direction to penetrate through the horizontal plane. Due to the design, reaction gas smoothly circulates at the edge of the annular main body, and the process stability is improved.

The invention provides a process chamber judgment method and device, and belongs to the technical field of semiconductor manufacturing. The process chamber judgment method comprises the following steps: providing a substrate silicon wafer, and measuring metal pollution values of M areas of the substrate silicon wafer to obtain a first measurement result; fixing the position of the V-shaped groove of the substrate silicon wafer, and preparing an epitaxial layer on the substrate silicon wafer through a plurality of process chambers to obtain an epitaxial silicon wafer; measuring the metal pollution values of the M areas of the epitaxial silicon wafer to obtain a second measurement result; measuring the metal pollution values of the M areas of the sample epitaxial silicon wafer to obtain a third measurement result; and determining the process chamber with metal pollution according to the first measurement result, the second measurement result and the third measurement result. According to the method, the source of metal pollution of the epitaxial silicon wafer can be determined, processing can be carried out in time, the abnormal occurrence rate of the epitaxial silicon wafer is reduced, and the quality of the epitaxial silicon wafer and the equipment productivity are improved.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source / drain regions.

Method for producing a semiconductor silicon wafer, which is composed of a silicon wafer substrate and a monocrystalline epitaxial silicon layer on it, comprising: a step (S2) of forming a silicon oxide layer with a thickness of at least 300 nm or thicker only on the back side of the silicon wafer substrate by the CVD process at a temperature of not more than 500 °C, wherein the silicon wafer substrate is produced from a monocrystalline silicon ingot grown by the Czochralski process, is doped with phosphorus, has a resistivity set to not more than 1.05 mΩ·cm, and a solid solution oxygen concentration of not more than 0.9×10 18 atoms / cm² 3 exhibits and on whose front surface a monocrystalline epitaxial silicon layer is to be formed; a heat treatment step (S4) after the step of forming the silicon oxide layer, in which the substrate is held in an oxidizing atmosphere at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes; a step (S5) of removing the surface oxide layer, which is formed as a thermal oxide layer on the front surface of the substrate during the heat treatment step, after the heat treatment step; and a step of depositing a monocrystalline epitaxial silicon layer on the substrate after the step of removing the surface oxide layer.

Described herein are semiconductor devices that include an epitaxial silicon carbide drift region with vertical current transport having a rectifying current injector or field effect transistor current injector on the upper portion of the drift layer and a lower portion having a contact on a substrate or contact on a drift layer to collect current.

Methods for low temperature selective deposition of epitaxial silicon- containing films and semiconductor devices incorporating the epitaxial silicon- containing films are provided. The method includes etchant-free selective epitaxy of N-type doped silicon including either a soak in a phosphorous source gas or an antimony seed layer. In one or more implementations, an underlying silicon surface is exposed to a pre-soak process performed by exposing the silicon surface to a phosphorous-containing gas, for example, phosphine gas, for a period of time followed by growing the N-doped epitaxial silicon film by co-flowing silicon sources and antimony sources only. The pre-soak / deposition process can be applied repeatedly to achieve desirable stack thickness. In one or more implementations, a seed layer of antimony-doped silicon is formed by co-flowing silicon and antimony source gases followed by co-flowing silicon source gases, antimony source gases, and phosphorous source gases to grow the N-doped epitaxial silicon film.

Semiconductor devices and methods for manufacturing semiconductor devices that include low temperature selective deposition of epitaxial silicon-containing films are provided. The method includes performing a first deposition process, a second deposition process subsequent to the first deposition process, and an etch process. The first deposition process includes forming an n-type doped semiconductor layer including a first n-type dopant on an exposed surface of a substrate. The second deposition process includes forming an n-type doped capping layer on the doped semiconductor layer, the n-type doped capping layer including a second n-type dopant different from the first n-type dopant. The etch process selectively removing an amorphous portion of the n-type doped semiconductor layer and an amorphous portion of the n-type doped capping layer, and leaving an epitaxial portion of the n-type doped semiconductor layer and an epitaxial portion of the n-type doped capping layer.

Semiconductor devices and methods for manufacturing semiconductor devices that include low temperature selective deposition of epitaxial silicon-containing films are provided. The method includes performing a first deposition process, a second deposition process subsequent to the first deposition process, and an etch process. The first deposition process includes forming an n-type doped semiconductor layer including a first n-type dopant on an exposed surface of a substrate. The second deposition process includes forming an n-type doped capping layer on the doped semiconductor layer, the n-type doped capping layer including a second n-type dopant different from the first n-type dopant. The etch process selectively removing an amorphous portion of the n-type doped semiconductor layer and an amorphous portion of the n-type doped capping layer, and leaving an epitaxial portion of the n-type doped semiconductor layer and an epitaxial portion of the n-type doped capping layer.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single-crystal silicon donor substrate; forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single-crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer; bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single-crystal silicon donor substrate, the handle structure including a single-crystal semiconductor handle substrate; and removing the single-crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The present application relates to the technical field of semiconductor devices, and provides a high-speed germanium-silicon HBT structure having low base region connection resistance and a manufacturing method therefor. The structure comprises: a substrate; isolation regions formed by etching and backfilling the substrate; a first dielectric layer arranged on the side of the substrate close to the isolation regions; a second dielectric layer arranged on the side of the first dielectric layer facing away from the substrate; an outer base region arranged on the side of the second dielectric layer facing away from the first dielectric layer; first side walls formed by etching the outer base region and depositing a dielectric material; and an inner base region formed by etching the first dielectric layer and the second dielectric layer and epitaxially growing silicon and germanium, the inner base region being in contact with the outer base region. In the present invention, the first dielectric layer and the second dielectric layer are etched and silicon and germanium are epitaxially grown to form the inner base region, so that the problems that the connection region of the inner base region and the outer base region is narrow, and the resistance and capacitance optimization have a large bottleneck are overcome; the outer base region and the inner base region are connected to form a self-aligned structure, base region connection resistance is reduced, and the highest oscillation frequency of a device is improved.

An epitaxial silicon wafer comprises a silicon wafer in which the entire surface, excluding an edge region from the outermost edge to 2 mm inward, is a COP region, and an epitaxial silicon layer formed on the surface of the silicon wafer. The average COP size in the peripheral region, located within 5 mm inward from the outermost edge of the silicon wafer, is 75 nm or less.

The application relates to an epitaxial layer removal method, a rework method and a semiconductor process method. The epitaxial layer removal method comprises the following steps: providing a substrate, the substrate is provided with a metal structure and an epitaxial layer, the metal structure is located in the epitaxial layer; and removing the epitaxial layer by using a wet etching solution; under the same condition, the removal rate of the wet etching solution to the epitaxial layer is greater than the removal rate of the wet etching solution to the metal structure, and is greater than the removal rate of the wet etching solution to an oxide. The substrate is provided with a metal structure and an epitaxial layer, the metal structure is located in the epitaxial layer, the removal rate of the wet etching solution to the epitaxial layer is greater than the removal rate of the wet etching solution to the metal structure under the same condition, and the metal structure is not seriously damaged when the epitaxial layer is removed by using the wet etching solution, so that the problem that there is no good way to remove the epitaxial silicon when the epitaxial layer on the front surface of the substrate is abnormal can be solved.