166 results about "Epitaxial silicon" patented technology

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single crystal silicon donor substrate, forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer, bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure, the handle structure including a single crystal semiconductor handle substrate, to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single crystal silicon donor substrate, and removing the single crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The invention provides a preparation method of a gate-all-around transistor device and the gate-all-around transistor device. The method comprises the following steps: providing a preset substrate; the preset base comprises a substrate, a plurality of periodically distributed fins located on the substrate and a dummy gate structure located on the fins, and each fin comprises a laminated structure formed by a plurality of sacrificial layers and channel layers which grow alternately; etching the side walls of the two sides of the sacrificial layer to enable the two sides of each sacrificial layer of the laminated structure to be embedded grooves relative to the channel layer; performing epitaxy of a semiconductor material on the two sides of the laminated structure after the groove is formed, so that the groove is filled with the semiconductor material, and epitaxial layers are formed on the two sides of the laminated structure; and epitaxially growing a source electrode and a drain electrode, etching to remove the false gate structure to form a groove, etching to remove the sacrificial layer in the laminated structure to form a channel, and forming a gate structure in the groove and the channel. According to the invention, the two sides of the sacrificial layer can be wrapped with a thick epitaxial semiconductor material, thereby avoiding device failure caused by wrong etching through of the epitaxial silicon layer, and improving the overall yield of products.

A semiconductor substrate comprising a first epitaxial silicon carbide layer and a second silicon carbide epitaxial layer. At least one semiconductor device is formed in or on the second silicon carbide epitaxial layer. The semiconductor substrate is formed overlying a silicon carbide substrate having a surface comprising silicon carbide and carbon. An exfoliation process is used to remove the semiconductor substrate from the silicon carbide substrate. The carbon on the surface of the silicon carbide substrate supports separation. A portion of the silicon carbide substrate on the semiconductor substrate is removed after the exfoliation process. The surface of the silicon carbide substrate is prepared for reuse in subsequent formation of semiconductor substrates.

A base, device and method for epitaxial growth of a silicon wafer, and an epitaxial silicon wafer. The base for epitaxial growth of a silicon wafer comprises a disc-shaped bearing part used for bearing the silicon wafer; and an annular periphery extending outwards in the radial direction from the disc-shaped bearing part, wherein the annular periphery is provided with a plurality of trench areas which are spaced apart, the trench areas are uniformly distributed in the circumferential direction of the annular periphery and are fan-shaped, and each trench area is provided with a plurality of pits arranged in an array.

The invention relates to a preparation method of a groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises the following steps of: forming a silicon oxide layer on the top surface of a silicon carbide substrate by adopting a thermal oxidation process, and then forming a groove in the silicon oxide layer; forming an initial gate electrode in the groove and on the top surface of a part of the silicon oxide layer on the outer side of the groove; etching the silicon oxide layer until the top surface of the silicon carbide substrate is exposed by taking the initial gate electrode as a mask, and forming a gate dielectric layer covering the bottom surface and the side wall of the groove; forming an epitaxial silicon carbide layer on the top surface of the silicon carbide substrate outside the gate dielectric layer; and removing a part of the epitaxial silicon carbide layer and a part of the initial gate electrode until the top surface of the gate dielectric layer is exposed, and taking the residual initial gate electrode in the groove as a gate electrode. According to the method, the gate dielectric layer of which the shape thickness can meet the design requirement is arranged at the bottom of the groove, so that the pressure resistance of the device is improved, the defects of the gate dielectric layer and a silicon carbide substrate interface are reduced, and the reliability of the device is improved.

The invention provides a silicon wafer polishing method and device, and belongs to the technical field of semiconductor manufacturing. The silicon wafer polishing method comprises the following steps: polishing a first silicon wafer by using a rough polishing solution; acquiring a flatness parameter of the polished first silicon wafer; and adjusting the pressure for polishing the second silicon wafer and / or the conductivity of a rough polishing solution according to the flatness parameter of the first silicon wafer. According to the invention, the flatness of the epitaxial silicon wafer can be improved.

The invention discloses an SIC MOSFET device and a preparation method thereof. The device comprises an N-type epitaxial silicon carbide layer, a high-K material suspension layer, a gate trench, a P body region, an N-type active region, a connecting hole, a high-K material dielectric layer, a top silicon dioxide layer and a metal layer. The high-K material suspension layer is arranged in the N-type epitaxial silicon carbide layer; the P body region and the N-type active region are arranged in the top region of the N-type epitaxial silicon carbide layer; a gate trench and a connecting hole are formed in the N-type epitaxial silicon carbide layer and extend to the lower part of the P body region; the gate trench is arranged right above the high-K material suspension layer; the gate trench is internally provided with a gate oxide layer and is filled with a polycrystalline silicon gate; the connecting hole is filled with a high-K material dielectric layer; the top silicon dioxide layer is arranged on the surfaces of the N-type active region and the gate trench; and the metal layer is filled in the connecting hole and covers the top silicon dioxide layer. The gate oxide in the trench can be protected from being influenced by a high electric field, the withstand voltage of the device is improved, the Miller capacitance and the output capacitance are reduced, and the switching loss of the device is reduced.

The invention relates to a silicon wafer suitable for a high-voltage device and a manufacturing method of the silicon wafer. The manufacturing method of the silicon wafer suitable for the high-voltage device comprises the following steps: providing a supporting wafer, wherein the supporting wafer comprises a first surface and a second surface which are oppositely distributed along a first direction; an epitaxial stack layer is formed on the first surface of the supporting wafer, the epitaxial stack layer comprises a plurality of epitaxial silicon layers which are sequentially stacked in the first direction, the supporting wafer is removed, the epitaxial silicon layers are sequentially formed through multiple epitaxial growth processes in a growing mode, and the epitaxial stack layer serves as a silicon wafer. According to the invention, the overall resistivity uniformity of the silicon wafer can be improved, and the internal defects of the silicon wafer are reduced, so that the performance of a high-voltage device manufactured by the silicon wafer is improved.

The invention relates to a semiconductor chip (1) with a semiconductor device (100) in a semiconductor body (10), wherein the semiconductor body (10) is a silicon carbide substrate (11); an epitaxial silicon carbide layer system (12) on a first side (11.1) of the silicon carbide substrate (11); a discontinuity layer (13); wherein the discontinuity layer (13) is embedded either in the silicon carbide substrate (11) or in the epitaxial silicon carbide layer system (12), each at a vertical distance (20) from the first side (11.1) of the silicon carbide substrate (11).

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

A large-size epitaxial silicon wafer taking mechanism comprises a supporting arm and a suction cup connected to the end of the supporting arm through a connecting piece, a first channel connected with negative pressure equipment is arranged in the supporting arm, a second channel is arranged in the suction cup, the bottom side of the second channel penetrates through the bottom of the suction cup to adsorb an epitaxial silicon wafer, and the top side of the second channel is connected with the first channel through a connecting piece. The connecting piece comprises a ball socket fixed to the supporting arm and a ball head fixed to the suction cup and matched with the ball socket, an inner cavity of the ball socket is connected with the first channel, the ball head is provided with a first channel in a penetrating mode, the lower end of the first channel is connected with the second channel, and elastic pieces distributed downwards are fixedly arranged in the ball socket and located on the periphery of the third channel. The elastic piece can deform and clamp and fix the ball head after the first channel sucks the negative pressure. The method is used for further reducing point-point contact damage between the suction cup and the silicon wafer to be detected.

The invention relates to the technical field of silicon wafer processing, and discloses a method for growing a single crystal diamond on a silicon wafer, which comprises the following steps of: by taking an atomic lattice of the silicon wafer as a template and the silicon wafer as a substrate, epitaxially growing silicon atoms and carbon atoms layer by layer by using an atomic layer deposition method, epitaxially growing silicon first and then adding carbon layer by layer during deposition, the silicon wafer with the single crystal diamond surface is formed through one hundred to one thousand layers, and the ratio of carbon to silicon is from initial zero to final 100%, so that the silicon wafer with the single crystal diamond surface is obtained. According to the method for growing the single crystal diamond from the silicon wafer, the existing huge silicon wafer industry is used, the silicon wafer serves as a substrate, epitaxial layer by layer is carried out through an atomic layer deposition (ALD) method, gas components of the ALD method are silane diluted by hydrogen and methane, during deposition, epitaxial silicon is carried out firstly, then carbon is added layer by layer, and the single crystal diamond surface silicon wafer is formed after one hundred to one thousands of layers; therefore, the stress of heteroepitaxy can be reduced to the minimum, and the monocrystal diamond can inherit extremely few defects of liquid-phase crystal pulling growth of silicon crystals.

Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.

In order to suppress the peeling of the annular protrusion formed by epitaxial processing, in an epitaxial silicon wafer (100) having a silicon epitaxial layer (2) on the main surface of a silicon wafer (1) having a chamfer (13), the aforementioned silicon wafer (1) contains boron and has a resistivity of 5 to 30 mΩ•cm. The resistivity of the aforementioned silicon epitaxial layer (2) is higher than that of the aforementioned silicon wafer 1. The thickness of the aforementioned silicon epitaxial layer 2 is 0.5 to 15 μm. The surfaces of the chamfer (131) and the end face (133) of the chamfer on the main surface side of the aforementioned silicon wafer (1) are covered by the aforementioned silicon epitaxial layer (2). The chamfer (132) on the back side has an annular protrusion (4). The annular protrusion (4) is formed by the boundary (14) of the region (R1) covered by the aforementioned silicon epitaxial layer (2) and the region (R2) not covered by the aforementioned silicon epitaxial layer (2).

A silicon wafer is provided, wherein the dopant is phosphorus, the resistivity is 0.5 mΩ·cm to 1.2 mΩ·cm, and the carbon concentration is 3.0 × 10⁻⁶. 16 atoms / cm 3 Or even higher. The carbon concentration near the surface of a silicon wafer is reduced by 10% or more compared to the depth at the center of the wafer.

The application discloses a method for forming a hybrid substrate of a SOI wafer. Buried oxide and silicon-on-insulator in some areas are removed, a layer of SiOCN is deposited on a SOI sidewall to protect the silicon-on-insulator sidewall, and then the growth of epitaxial silicon is performed to cause the silicon substrate area to grow to be flush with the silicon-on-insulator area. The SiOCN on the SOI sidewall acts as a protective layer to prevent the growth of epitaxial silicon on the SOI sidewall, thereby preventing the generation of a bulge at a boundary between the SOI area and the silicon substrate area and improving the product yield. Moreover, a SiOCN film may be deposited with high conformality, and the SiOCN deposited on the SOI sidewall has good uniformity, so that the growth of epitaxial Si from the SOI does not occur during subsequent growth of the epitaxial silicon.

This disclosure provides a susceptor, apparatus and method for epitaxial growth of silicon wafers and an epitaxial silicon wafer, and belongs to the semiconductor manufacturing technology field. The susceptor for epitaxial growth of silicon wafers includes a disc-shaped mounting portion for mounting the silicon wafer and an annular peripheral portion extending radially outward from the disc-shaped mounting portion, wherein the annular peripheral portion has a plurality of spaced groove regions, the groove regions are uniformly distributed along the circumferential direction of the annular peripheral portion, the groove regions exhibit a fan-ring shape, and each of the groove regions has a plurality of pits arranged in an array.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. And, more particularly, to multiple, alternating epitaxial silicon, e.g., in horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source / drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures. Vertical digit lines coupled to the first source / drain regions.

The application discloses an epitaxial silicon wafer pretreatment system and process with high uniformity of passivation layer, a support is fixedly arranged at the bottom of the treatment box, and the application relates to the technical field of silicon wafer pretreatment. The epitaxial silicon wafer pretreatment system and process with high uniformity of passivation layer, through cooperation between the partition plate mechanism, the disturbance plate mechanism, the suction mechanism and the servo motor, the servo motor is started, the suction mechanism is driven to work, the hydrofluoric acid solution in the treatment box is sucked out from the lower part, then is sprayed out through each disturbance plate mechanism, impacts the surface of the adjacent epitaxial silicon wafer, at the same time, the external gas is sucked in, then is blown into the hydrofluoric acid solution through each disturbance plate mechanism, so that the hydrofluoric acid is more uniformly contacted to the surface of the epitaxial silicon wafer, the circulating flowing hydrofluoric acid solution and the inhaled gas are cooperated with each other, the purpose of efficiently removing the oxide and impurities on the surface of the epitaxial silicon wafer is achieved, and the flatness and uniformity of the surface of the epitaxial silicon wafer are ensured.

The invention discloses a method for forming an SOI (Silicon On Insulator) silicon wafer mixed substrate, which comprises the following steps of: removing a buried oxide layer and silicon-on-insulator in a partial region, protecting the side wall of the silicon-on-insulator by depositing a layer of SiOCN on the side wall of an SOI, and performing epitaxial silicon growth to enable a silicon substrate region to grow to be flush with a silicon-on-insulator region. The SiOCN on the side wall of the SOI is used as a protective layer, so that the growth of epitaxial silicon on the side wall of the SOI can be prevented, the generation of bumps at the boundary of the SOI region and the silicon substrate region can be prevented, and the product yield is improved. Moreover, the SiOCN film can be deposited with high conformality, the uniformity of SiOCN deposited on the side wall of the SOI is good, the situation that Si is subjected to epitaxial growth on the SOI cannot occur during subsequent epitaxial silicon growth, and the product yield can be further improved.

The present application belongs to the technical field of semiconductors. Disclosed are a transistor preparation method and an electronic device. The method comprises: etching a first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303), so as to form a plurality of first silicon pillars (304) in a first direction; etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to a plurality of columns of second masks (305); forming laterally epitaxial silicon on the first silicon layer (301), a lateral groove and the second silicon layer (303); depositing a gate material above the first silicon layer (301); performing anisotropic etching of the gate material according to a plurality of side walls (305-1), so as to form a plurality of second silicon pillars (306); and forming a vertical gate-all-around transistor on the basis of the plurality of second silicon pillars (306). The method prevents a source / drain from being contaminated with metal.

The present invention is an epitaxial wafer comprising a single-crystal silicon substrate having a resistivity of 10-5,000 Ω·cm and having, formed thereon in the following order, an epitaxial silicon film having a carbon concentration of 2×1019 atoms / cm3 or higher but less than 3×1020 atoms / cm3 and containing carbon defects and a dielectric layer. The epitaxial silicon film has a thickness satisfying the formula: 6.6×1020×exp\{-1.6×[thickness (μm) of epitaxial silicon film]\}>[carbon concentration (atoms / cm3) of epitaxial silicon film]. As a result, the present invention provides: an epitaxial silicon wafer for high-frequency integrated circuit boards which is obtained by forming the epitaxial silicon film on a silicon substrate having an ordinary resistivity and which has the excellent ability to reduce higher harmonics and is easy to process; and a method for producing the epitaxial silicon wafer.

A workpiece includes a doped p-type substrate, a co-doped P+ epitaxial silicon layer disposed on the doped p-type substrate, and a boron-doped P− epitaxial layer disposed on the co-doped P+ epitaxial silicon layer. The co-doped P+ epitaxial silicon layer is co-doped with germanium and boron. A ratio of the germanium to the boron in the co-doped P+ epitaxial silicon layer may be from 10 to 16.

An apparatus comprising a memory array comprising word lines, bit lines, and memory cells, one or more of the memory cells coupled to an associated word line and an associated bit line and comprising active areas and shallow trench isolation (STI) structures adjacent to a base material. The word lines are in the active areas and STI structures and bit line structures are adjacent to the active areas and the STI structures and oriented perpendicular to the word lines. The bit line structures comprise bit lines and bit contacts. Cell contact structures are laterally adjacent to the bit line structures and comprise cell contacts comprising an epitaxial semiconductive material. One or more of the bit contacts and the epitaxial semiconductive material comprise a doped epitaxial silicon material, the doped epitaxial silicon material exhibiting a relatively greater dopant concentration in a [110] crystal orientation than in a [100] or [111] crystal orientation. Methods of forming the apparatus are also disclosed.

Provided is a method for producing an epitaxial silicon wafer having a high hydrogen-based passivation effect. This method for producing an epitaxial silicon wafer (100) is characterized by comprising: a first step for irradiating the surface of a silicon wafer (10) with a beam containing cluster ions of SiHx (x is an integer of 1-3) ions (12A) and C2Hy (y is an integer of 2-5) ions (12B), and forming a modified layer (14) on the surface layer portion of the silicon wafer (10); and a second step in which a silicon epitaxial layer (16) is formed on the modified layer (14), the total dose of the silicon epitaxial layer (16) being 6.00 * 1013-1.00 * 1015 ions / cm2 inclusive, the dose of C2Hy ions (12B) exceeding 1.00 * 1014 ions / cm2 inclusive and 3.00 * 1014 ions / cm2 inclusive, and the ratio of the number of implanted Si atoms to the number of implanted C atoms [Si / C] being 0.3-1.6 inclusive.

The present application provides an epitaxial silicon wafer and a manufacturing method therefor. During the growth process of an epitaxial layer, the step of growing a homoepitaxial layer on one side of a substrate material in stages comprises: providing a silicon wafer serving as a substrate; depositing a middle epitaxial layer on the silicon wafer substrate, and then performing edge topography flatness compensation on the middle epitaxial layer; and depositing a top epitaxial layer on the middle epitaxial layer. The method comprises at least one stage I and a stage II.

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

The invention provides a method and a device for measuring the width of a transition region of an epitaxial silicon wafer, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: acquiring resistivity data of an epitaxial silicon wafer at different depths, and generating a resistivity curve according to the resistivity data; determining the slope of each position point on the resistivity curve, and determining a tangent line at the target position point with the maximum slope; selecting a resistivity curve corresponding to the first preset depth range, generating a first straight line according to the resistivity curve of the first preset depth range, selecting a resistivity curve corresponding to the second preset depth range, and generating a second straight line according to the resistivity curve of the second preset depth range; determining a first intersection point of the tangent and the first straight line and a second intersection point of the tangent and the second straight line; and the abscissa of the first intersection point and the abscissa of the second intersection point are subtracted to obtain the thickness of the epitaxial layer of the epitaxial silicon wafer. The method can accurately measure the width of the transition region of the epitaxial silicon wafer.

A semiconductor substrate includes a handle wafer, an oxide layer formed on the handle wafer, and a device layer formed or disposed on the oxide layer. The device layer includes a first epitaxial silicon layer bonded to the oxide layer formed on the handle wafer, a layer of compensated silicon crystalline material formed or disposed on the first epitaxial silicon layer, and a second epitaxial silicon layer formed on the layer of compensated silicon crystalline material. The compensated silicon crystalline material includes a Czochralski silicon substrate.

Methods for low temperature selective deposition of epitaxial silicon-containing films and semiconductor devices incorporating the epitaxial silicon-containing films are provided. The method includes etchant-free selective epitaxy of N-type doped silicon including either a soak in a phosphorous source gas or an antimony seed layer. In one or more implementations, an underlying silicon surface is exposed to a pre-soak process performed by exposing the silicon surface to a phosphorous-containing gas, for example, phosphine gas, for a period of time followed by growing the N-doped epitaxial silicon film by co-flowing silicon sources and antimony sources only. The pre-soak / deposition process can be applied repeatedly to achieve desirable stack thickness. In one or more implementations, a seed layer of antimony-doped silicon is formed by co-flowing silicon and antimony source gases followed by co-flowing silicon source gases, antimony source gases, and phosphorous source gases to grow the N-doped epitaxial silicon film.