11 results about "Strained silicon" patented technology

Devices and / or methods of fabrication facilitating suppression of embedded SiGe optical waveguides with low defectivity are provided. In an embodiment, a device can comprise a substrate comprising a trench within the substrate, wherein the trench comprises a base surface and sidewalls comprising the substrate; and a fully strained silicon-germanium (SiGe) structure located within the trench, wherein a bottom surface of the SiGe structure is in contact with the base surface, wherein side surfaces of the SiGe structure are in contact with the sidewalls, and wherein the SiGe structure is at least twice the critical thickness.

The invention relates to a method for producing a microelectronic device on an FD-SOI substrate, wherein the method comprises: forming a first well in a substrate (11) of a first wafer made of insulating material suitable for forming a shallow trench isolation (STI) (14); forming a strained silicon film (23) (sSi) covered with an oxide layer (24) on a second wafer; bonding the second wafer, after a vertical flip, onto the first wafer so that the oxide layer becomes a buried oxide layer (BOX) covered with the sSi film, which thus becomes a strained silicon on insulator film; removing the donor substrate while retaining the BOX layer and the sSi film; and forming a second isolation trench SSTI (34) by local oxidation of the silicon of the sSi film, which is connected to the STI via the BOX, to form a composite isolation structure (STI-BOX-SSTI).

The invention discloses a low-strain silicon-carbon negative electrode material and a preparation method thereof. The preparation method comprises the following steps: S100, synthesizing an MgV2O6 product from a magnesium source and a vanadium source; s200, porous carbon and the MgV2O6 product are mixed, and a base material is prepared; and S300, performing vapor deposition on the outer surface and the pore channels of the base material by using a silane gas source and a carbon gas source in inert gas to obtain the silicon-carbon negative electrode material. The MgV2O6 with a stable crystal structure is prepared from the magnesium source and the vanadium source, rigid support is provided in the subsequent preparation process, and the use stability and the thermal stability are improved. A silane gas source and a carbon gas source are subjected to vapor deposition on a base material to generate a silicon-carbon active substance in situ, so that silicon atoms, carbon atoms and carbon atoms on the surface of the base material form firm chemical bonding, stress generated during silicon expansion is absorbed by an internal structure of the silicon-carbon negative electrode material, and the silicon-carbon negative electrode material with high use stability is prepared.

The application discloses a local strain silicon LDMOS device and a manufacturing method thereof. The LDMOS device comprises a body region of a first conductive type and a drift region of a second conductive type, a source region of the second conductive type is formed in the body region, a drain region of the second conductive type is formed in the drift region, and a strain region distributed along a source-drain direction is further formed in the interior of the drift region, which can at least generate stress on the drift region and improve the carrier mobility of the drift region. The local strain silicon LDMOS device has higher radio frequency output power, gain, efficiency and working frequency.

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) disposed directly on the support (1a). At least one pFET structure is located directly on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is located directly on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and an nFET gate structure encapsulating each channel nanosheet of the second stack.

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof, and the semiconductor device comprises a first channel, a dielectric isolation layer and a second channel which are sequentially stacked; the dielectric isolation layer comprises a first stress layer, an isolation layer and a second stress layer which are stacked in sequence; the first stress layer is adjacent to the first channel. According to the semiconductor device, stress can be applied to the upper channel region and the lower channel region, and independent stress regulation and control can be carried out, so that collaborative optimization of carrier mobility can be realized, and the strain engineering problem in an advanced node strain silicon complementary field effect transistor device can be effectively solved.

The invention relates to a pressure sensor and a pressure detection method thereof. The pressure sensor includes a substrate; a first coupled resonator and a second coupled resonator are arranged on the same layer of the substrate; a pressure strain silicon mode is embedded in an anchor area, corresponding to the first coupled resonator, in the substrate; the first coupled resonator and the second coupled resonator are coupled through static electricity; the first coupled resonator and the second coupled resonator are the same in mass and rigidity; the first coupled resonator and the second coupled resonator are connected to the anchor area through symmetrical pressure amplification structures; the pressure strain silicon mold is rigidly connected with a central anchor point in the anchor area; the pressure strain silicon mode is used for driving the center anchor point to displace under the condition that the pressure strain silicon mode is deformed due to the change of ambient pressure so as to change the rigidity change of the first coupled resonator; the rigidity change is used for determining environment air pressure of the environment where the pressure sensor is located. By adopting the method, the detection sensitivity can be remarkably improved.

The application discloses a low-strain silicon-carbon negative electrode material and a preparation method thereof. The preparation method comprises the following steps: S100, synthesizing MgV2O6 products from a magnesium source and a vanadium source; S200, mixing porous carbon and the MgV2O6 products to obtain a base material; and S300, performing vapor deposition on the outer surface and the pores of the base material by using a silane gas source and a carbon gas source in an inert gas to obtain a silicon-carbon negative electrode material. The MgV2O6 with a stable crystal structure is prepared from the magnesium source and the vanadium source, and rigid support is provided in the subsequent preparation process, so that the use stability and the thermal stability are improved. The silane gas source and the carbon gas source are vapor-deposited on the base material to generate silicon-carbon active substances in situ, so that the silicon atoms, the carbon atoms and the carbon atoms on the surface of the base material form firm chemical bonds, the stress generated when the silicon expands is absorbed by the internal structure of the silicon-carbon negative electrode material, and thus the silicon-carbon negative electrode material with high use stability is prepared.

This invention discloses a temperature-dependent analytical method for the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET, relating to the field of semiconductor technology. The method includes: substituting the approximate expression of the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition to obtain a two-dimensional channel potential energy expression; substituting the two-dimensional channel potential energy expression into the Poisson equation and setting the coordinates perpendicular to the channel direction to 0 to obtain a temperature-dependent surface potential equation; solving the surface potential energy equation using the second, third, fourth, and fifth boundary conditions to obtain an analytical expression for the surface potential; obtaining the minimum surface potential by taking the first derivative of the analytical expression; and obtaining a temperature model for the threshold voltage based on the minimum surface potential and the definition of the threshold voltage; and solving the temperature model to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET. This method improves the analytical accuracy of the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

The application provides a semiconductor structure preparation method and a semiconductor structure, and the semiconductor structure preparation method comprises the following steps: sequentially growing a SiGe relaxation buffer layer and a fully relaxed SiGe strain relaxation layer on a second silicon substrate, bonding the SiGe strain relaxation layer on the second silicon substrate on a dielectric layer on a first silicon substrate, then removing the second silicon substrate and the SiGe relaxation buffer layer, thinning the SiGe strain relaxation layer, and finally epitaxially growing a tensile-strained silicon layer on the thinned SiGe strain relaxation layer, so as to realize a high-mobility tensile-strained silicon layer SOI structure, and a new nanosheet substrate platform with high-mobility, less impurity contamination, low impurity contamination and high-quality stacked structure and channel structure is manufactured. The application is convenient for subsequent preparation of structures such as but not limited to a tensile-strained silicon channel in the tensile-strained silicon layer according to application scenarios, and provides an excellent substrate for an FD / GAAOI device.

Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.