31 results about "Strained silicon" patented technology

The invention discloses an enhanced MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) performance structure with a strained silicon channel and a manufacturing process of the enhanced MOSFET performance structure, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; through the rectangular side symmetric P-layers with V-shaped notches on the two sides of the N drift layer, the contact area with the N substrate layer is enlarged, transverse electric field constraint is constructed, the short-channel effect is remarkably inhibited, scattering of carriers on the edge of a channel is reduced, and electric field concentration between a drain electrode and the channel can be relieved through a longitudinal doping gradient formed by the lightly doped N layer and the trapezoidal heavily doped N layer; and the electric field breakdown risk under the short channel is avoided.

Devices and / or methods of fabrication facilitating suppression of embedded SiGe optical waveguides with low defectivity are provided. In an embodiment, a device can comprise a substrate comprising a trench within the substrate, wherein the trench comprises a base surface and sidewalls comprising the substrate; and a fully strained silicon-germanium (SiGe) structure located within the trench, wherein a bottom surface of the SiGe structure is in contact with the base surface, wherein side surfaces of the SiGe structure are in contact with the sidewalls, and wherein the SiGe structure is at least twice the critical thickness.

The invention relates to an RF semiconductor device and a manufacturing method thereof. The present disclosure relates to a radio frequency (RF) device including a molded device die and a multi-layer redistribution structure underlying the molded device die. The molded device die includes a device region having a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a first molding compound. The FEOL portion includes an active layer formed of a strained silicon epitaxial layer, the lattice constant in the strained silicon epitaxial layer being greater than 5.461 at a temperature of 300K. The first molding compound is over the active layer. Herein, there is no silicon crystal between the first molding compound and the active layer. The multi-layer redistribution structure includes a plurality of bump structures at a bottom of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the molded device die.

The invention provides a fully-depleted silicon-on-insulator wafer and a manufacturing method thereof, and the method comprises the steps: providing a first substrate, enabling a first silicon-germanium layer, a second silicon-germanium layer and a first buried oxide layer to be sequentially stacked on the first substrate, and enabling the germanium content of the second silicon-germanium layer to be greater than 50%, and the second silicon-germanium layer to be a compressive strain silicon-germanium layer; providing a second substrate, wherein a second buried oxide layer is arranged on the second substrate; bonding the first substrate and the second substrate, and removing the first substrate and the first silicon germanium layer; etching to remove the second silicon germanium layer located in the N-type conductive type region to form an opening, and forming a first silicon layer which is a tensile strain silicon layer at the opening by using an ultralow-temperature lateral selective epitaxial process based on disilane silicon source gas or trisilane silicon source gas; the second silicon germanium layer located in the P-type conductive type region and the first silicon layer located in the N-type conductive type region form a fully depleted silicon-on-insulator (FDSOI) wafer, and the FDSOI wafer is provided with a compressive strain silicon germanium layer with high hole mobility and a tensile strain silicon layer with high electron mobility.

Heterostructures having germanium-seeded, shear-strained silicon quantum wells are provided. Also provided are gate-controlled qubits based on the heterostructures, and quantum computing systems based on the qubits. The heterostructures include a quantum well of germanium-seeded silicon positioned between two quantum barriers of germanium or a silicon-germanium alloy. The silicon of the quantum well is under a shear strain and is seeded with germanium such that the germanium concentration in the quantum well has an oscillating profile.

The invention relates to a method for producing a microelectronic device on an FD-SOI substrate, wherein the method comprises: forming a first well in a substrate (11) of a first wafer made of insulating material suitable for forming a shallow trench isolation (STI) (14); forming a strained silicon film (23) (sSi) covered with an oxide layer (24) on a second wafer; bonding the second wafer, after a vertical flip, onto the first wafer so that the oxide layer becomes a buried oxide layer (BOX) covered with the sSi film, which thus becomes a strained silicon on insulator film; removing the donor substrate while retaining the BOX layer and the sSi film; and forming a second isolation trench SSTI (34) by local oxidation of the silicon of the sSi film, which is connected to the STI via the BOX, to form a composite isolation structure (STI-BOX-SSTI).

The fabrication of a microelectronic device on an FD-SOI substrate involves: the formation in the substrate (11) of a first wafer, of first boxes in insulating material adapted to form shallow insulation trenches (14) (STI); the formation, on a second wafer, of a film (23) of strained silicon (sSi) covered with a layer of oxide (24); the bonding of the second wafer on the first wafer, after vertical inversion, whereby the oxide layer becomes a buried oxide layer (BOX), covered by the sSi film which thus becomes a strained silicon film on insulator; the removal of the donor substrate while leaving the BOX layer and the sSi film; and the formation of second SSTI insulation trenches (34) by local oxidation of the silicon of the sSi film, which join the STIs via the BOX, to form complex insulation structures (STI-BOX-SSTI). Figure for the abridged version: [Fig.11]

This invention discloses a ferroelectric field-effect transistor (FeFET) based on strained silicon technology and its fabrication method. The ferroelectric field-effect transistor includes: a Si substrate of a first doping type; a drain and a source region of a second doping type, located at both ends of the Si substrate, with their upper surfaces flush with the upper surface of the Si substrate; a SiO2 insulating layer located on the Si substrate and in contact with the drain and source regions; an HZO ferroelectric dielectric layer located on the SiO2 insulating layer; a gate electrode located on the HZO ferroelectric dielectric layer; a source electrode and a drain electrode located on a portion of the drain region and a portion of the source region, respectively; a SiN layer located on the remaining portion of the drain region, the remaining portion of the source region, the gate electrode, the source electrode, and the drain electrode, as well as on the sidewalls of the SiO2 insulating layer, the HZO ferroelectric dielectric layer, the gate electrode, the source electrode, and the drain electrode. This invention can further improve the ferroelectric characteristics and storage capacity of the FeFET.

Provided are a light-receiving element which has more capability of detecting wavelengths than that of existing silicon light-receiving elements and a unit pixel of an image sensor by using it. The light-receiving element includes: a light-receiving unit which is floated or connected to external voltage and absorbs light; an oxide film which is formed to come in contact with a side of the light-receiving unit; a source and a drain which stand off the light-receiving unit with the oxide film in between and face each other; a channel which is formed between the source and the drain and forms an electric current between the source and the drain; and a wavelength expanding layer which is formed in at least one among the light-receiving unit, the oxide film and the channel and forms a plurality of local energy levels by using strained silicon.

The invention discloses a low-strain silicon-carbon negative electrode material and a preparation method thereof. The preparation method comprises the following steps: S100, synthesizing an MgV2O6 product from a magnesium source and a vanadium source; s200, porous carbon and the MgV2O6 product are mixed, and a base material is prepared; and S300, performing vapor deposition on the outer surface and the pore channels of the base material by using a silane gas source and a carbon gas source in inert gas to obtain the silicon-carbon negative electrode material. The MgV2O6 with a stable crystal structure is prepared from the magnesium source and the vanadium source, rigid support is provided in the subsequent preparation process, and the use stability and the thermal stability are improved. A silane gas source and a carbon gas source are subjected to vapor deposition on a base material to generate a silicon-carbon active substance in situ, so that silicon atoms, carbon atoms and carbon atoms on the surface of the base material form firm chemical bonding, stress generated during silicon expansion is absorbed by an internal structure of the silicon-carbon negative electrode material, and the silicon-carbon negative electrode material with high use stability is prepared.

The present disclosure relates to a radio frequency (RF) device comprising a molded device die and a multi-layer redistribution structure located below the molded device die. The molded device die comprises a device region and a first molding compound, wherein the device region has a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion located above the BEOL portion. The FEOL portion comprises an active layer formed of a strained silicon epitaxial layer having a lattice constant greater than 5.461 at a temperature of 300K. The first molding compound is located above the active layer. In this context, no silicon crystals are present between the first molding compound and the active layer. The multi-layer redistribution structure comprises a plurality of bump structures located at a bottom of the multi-layer redistribution structure and electrically coupled to the FEOL portion of the molded device die.

The invention relates to a method of manufacturing a stacked structure comprising a layer of semiconductor material adhered to a substrate, comprising: manufacturing a heterostructure by:forming an interlayer made of a two-dimensional material on a growth substrate (1);patterning the interlayer with a plurality of openings to form a patterned interlayer (3);growing a semiconductor material on the patterned interlayer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned interlayer;forming a first assembly by bonding the heterostructure with a handle substrate (6), the continuous epitaxial layer being located at the bonding interface;separating the first assembly at the level of the patterned interlayer (3) so as to obtain a second assembly resulting from the transfer of the continuous epitaxial (4) layer from the heterostructure towards the handle substrate (6). Figure pour l’abrégé : Figure 7

Techniques for creating an SiGe / Si electro-optomechanical quantum transducer, comprising an SiGe / Si optical ring resonator and capacitor, that can be associated with a qubit are presented. The optical resonator, comprising an SiGe optical waveguide and a strained silicon membrane, can be formed and disposed over a substrate. The strained silicon membrane can have a photoelastic coupling with the SiGe optical waveguide. A capacitor, comprising a superconducting material, can be formed in proximity to the optical resonator. The top plate of the capacitor can be associated with the strained silicon membrane. A recessed region can be formed in the back side of the substrate along a desired silicon plane, extending to form a hole in the top side of the substrate. A superconducting material can be applied along substrate surfaces defining the recessed region and hole. The superconducting material covering the hole can be the bottom plate of the capacitor.

The application discloses a local strain silicon LDMOS device and a manufacturing method thereof. The LDMOS device comprises a body region of a first conductive type and a drift region of a second conductive type, a source region of the second conductive type is formed in the body region, a drain region of the second conductive type is formed in the drift region, and a strain region distributed along a source-drain direction is further formed in the interior of the drift region, which can at least generate stress on the drift region and improve the carrier mobility of the drift region. The local strain silicon LDMOS device has higher radio frequency output power, gain, efficiency and working frequency.

Method for manufacturing an SSOI structure The present description relates to a method for manufacturing an SSOI structure comprising the following steps: - Providing a receiver substrate (10) comprising a first support substrate (11), - Providing a donor substrate (20) comprising a second support substrate (21) successively covered by a buffer layer, preferably made of SiGe (22), a strained silicon layer (23), an oxide layer (24) and an amorphous silicon layer (25), - Bringing the receiver substrate (10) and the donor substrate (20) into contact to form a bonding interface, - Carrying out a heat treatment at a temperature between 500 and 800°C to consolidate the bonding interface, - Removing the second support substrate (21) and the buffer layer (22), whereby an SSOI structure is obtained. Figure for abstract: Fig. 1A

A strain-relaxed silicon / silicon germanium (Si / SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) disposed directly on the support (1a). At least one pFET structure is located directly on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is located directly on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and an nFET gate structure encapsulating each channel nanosheet of the second stack.

The invention relates to a method for producing a stacked structure comprising a layer of semiconductor material bonded to a substrate, which comprises: producing a heterostructure by: • forming an intermediate layer made of a two-dimensional material on a growth substrate (1); patterning the intermediate layer with a plurality of openings to form a patterned intermediate layer (3); growing a semiconductor material on the patterned intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a handling substrate (6), the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer (3) so as to obtain a second assembly resulting from transferring the continuous epitaxial layer (4) from the heterostructure to the handling substrate (6).

The invention relates to a method for producing a microelectronic device on a FD-SOI substrate, wherein the method comprises: forming, in the substrate (11) of a first wafer, first wells made of insulating material suitable for forming shallow trench isolations (STIs) (14); forming, on a second wafer, a strained silicon film (23) (sSi) covered with an oxide layer (24); bonding the second wafer to the first wafer, after vertical flipping, whereby the oxide layer becomes a buried oxide layer (BOX), covered by the sSi film, which thus becomes a strained silicon film on insulator; removing the donor substrate while leaving the BOX layer and the sSi film; and forming second trench isolations SSTIs (34) by locally oxidising the silicon of the sSi film, which join to the STIs via the BOX, to form complex isolation structures (STI-BOX-SSTI).

The invention discloses a silicon / graphene composite material as well as a preparation method and application thereof, and belongs to the technical field of lithium ion batteries. The method comprises the following steps: adding silicon powder into water, then adding a cationic polymer, carrying out ultrasonic dispersion, and centrifuging to obtain a silicon precipitate; and adding the aqueous solution of the silicon precipitate into the graphene oxide solution, stirring, filtering, and calcining the obtained Si-coated GO to obtain the silicon / graphene composite material. The strongly coupled silicon / graphene composite material is prepared through in-situ electrostatic self-assembly and post-annealing reduction processes, the composite structure greatly inhibits stress / strain caused by volume change, silicon nanoparticles are completely wrapped by graphene nanosheets, many gaps are formed by aggregation of silicon and folding and stacking of the graphene nanosheets, and the graphene / silicon composite material is prepared. And permeation of electrolyte and transmission of Li < + > ions are facilitated.

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof, and the semiconductor device comprises a first channel, a dielectric isolation layer and a second channel which are sequentially stacked; the dielectric isolation layer comprises a first stress layer, an isolation layer and a second stress layer which are stacked in sequence; the first stress layer is adjacent to the first channel. According to the semiconductor device, stress can be applied to the upper channel region and the lower channel region, and independent stress regulation and control can be carried out, so that collaborative optimization of carrier mobility can be realized, and the strain engineering problem in an advanced node strain silicon complementary field effect transistor device can be effectively solved.

This invention discloses an enhancement-mode MOSFET structure with strained silicon channel and its manufacturing process, belonging to the field of semiconductor technology. It comprises several parallel MOSFET cells, each including a drain, a semiconductor epitaxial layer, a source, and a gate. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, a P+ layer, an N-well layer, and a P-well layer. A lightly doped N-layer is disposed in the middle of the N-drift layer of each MOSFET cell. This invention expands the contact area with the N-substrate layer by using rectangular, side-symmetric P-layers with V-shaped notches on both sides of the N-drift layer, thus constructing a lateral electric field constraint, significantly suppressing the short-channel effect, reducing carrier scattering at the channel edge, and mitigating the electric field concentration between the drain and the channel by the vertical doping gradient formed by the lightly doped N-layer and the trapezoidal heavily doped N-layer, avoiding the risk of electric field breakdown under short-channel conditions.

Heterostructures having germanium-seeded, shear-strained silicon quantum wells are provided. Also provided are gate-controlled qubits based on the heterostructures, and quantum computing systems based on the qubits. The heterostructures include a quantum well of germanium-seeded silicon positioned between two quantum barriers of germanium or a silicon-germanium alloy. The silicon of the quantum well is under a shear strain and is seeded with germanium such that the germanium concentration in the quantum well has an oscillating profile.

The invention relates to a pressure sensor and a pressure detection method thereof. The pressure sensor includes a substrate; a first coupled resonator and a second coupled resonator are arranged on the same layer of the substrate; a pressure strain silicon mode is embedded in an anchor area, corresponding to the first coupled resonator, in the substrate; the first coupled resonator and the second coupled resonator are coupled through static electricity; the first coupled resonator and the second coupled resonator are the same in mass and rigidity; the first coupled resonator and the second coupled resonator are connected to the anchor area through symmetrical pressure amplification structures; the pressure strain silicon mold is rigidly connected with a central anchor point in the anchor area; the pressure strain silicon mode is used for driving the center anchor point to displace under the condition that the pressure strain silicon mode is deformed due to the change of ambient pressure so as to change the rigidity change of the first coupled resonator; the rigidity change is used for determining environment air pressure of the environment where the pressure sensor is located. By adopting the method, the detection sensitivity can be remarkably improved.

The application discloses a low-strain silicon-carbon negative electrode material and a preparation method thereof. The preparation method comprises the following steps: S100, synthesizing MgV2O6 products from a magnesium source and a vanadium source; S200, mixing porous carbon and the MgV2O6 products to obtain a base material; and S300, performing vapor deposition on the outer surface and the pores of the base material by using a silane gas source and a carbon gas source in an inert gas to obtain a silicon-carbon negative electrode material. The MgV2O6 with a stable crystal structure is prepared from the magnesium source and the vanadium source, and rigid support is provided in the subsequent preparation process, so that the use stability and the thermal stability are improved. The silane gas source and the carbon gas source are vapor-deposited on the base material to generate silicon-carbon active substances in situ, so that the silicon atoms, the carbon atoms and the carbon atoms on the surface of the base material form firm chemical bonds, the stress generated when the silicon expands is absorbed by the internal structure of the silicon-carbon negative electrode material, and thus the silicon-carbon negative electrode material with high use stability is prepared.

The invention provides a trench isolation structure for improving dislocation, which comprises a substrate, a trench is formed on the substrate, and a strained silicon layer is formed on the surface of the trench; a linear liner oxide layer is formed on the surface of the strained silicon layer in the groove; and the high-density plasma oxide layer is used for filling the residual groove. The strained silicon layer is used for resisting the internal stress of the high-density plasma oxide layer, and the strained silicon layer can bear the subsequent high-temperature process to keep the internal stress.

The present invention discloses a high-precision non-destructive detection method and system for ion implantation defects, relating to the technical field of non-destructive detection. The method includes: selecting a measurement light source to collect reflected light intensity data, representing the intensity distribution of polarized light using the Stokes vector, calculating the ellipsometry parameters and determining the refraction angle data, calculating the complex refractive index through the Fresnel formula and determining the refractive index and extinction coefficient, and analyzing the overall complex dielectric constant of the material; dividing the crystal material region, obtaining the complex dielectric constant of the optimized region using the non-linear regression method, and constructing a three-layer composite medium model in combination with the region occupancy ratio. The method of the present invention can reveal the microscopic inhomogeneity inside the material through numerical analysis by calculating the Stokes parameters, improve the resolution of the damaged region, and can accurately distinguish the distributions of crystalline silicon, amorphous silicon and strained silicon after ion implantation by dividing the crystal material region, thereby improving the analysis ability of the microscopic structural changes of the material.

This invention discloses a temperature-dependent analytical method for the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET, relating to the field of semiconductor technology. The method includes: substituting the approximate expression of the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition to obtain a two-dimensional channel potential energy expression; substituting the two-dimensional channel potential energy expression into the Poisson equation and setting the coordinates perpendicular to the channel direction to 0 to obtain a temperature-dependent surface potential equation; solving the surface potential energy equation using the second, third, fourth, and fifth boundary conditions to obtain an analytical expression for the surface potential; obtaining the minimum surface potential by taking the first derivative of the analytical expression; and obtaining a temperature model for the threshold voltage based on the minimum surface potential and the definition of the threshold voltage; and solving the temperature model to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET. This method improves the analytical accuracy of the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

A strain-relaxed silicon / silicon germanium (Si / SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.

The application provides a semiconductor structure preparation method and a semiconductor structure, and the semiconductor structure preparation method comprises the following steps: sequentially growing a SiGe relaxation buffer layer and a fully relaxed SiGe strain relaxation layer on a second silicon substrate, bonding the SiGe strain relaxation layer on the second silicon substrate on a dielectric layer on a first silicon substrate, then removing the second silicon substrate and the SiGe relaxation buffer layer, thinning the SiGe strain relaxation layer, and finally epitaxially growing a tensile-strained silicon layer on the thinned SiGe strain relaxation layer, so as to realize a high-mobility tensile-strained silicon layer SOI structure, and a new nanosheet substrate platform with high-mobility, less impurity contamination, low impurity contamination and high-quality stacked structure and channel structure is manufactured. The application is convenient for subsequent preparation of structures such as but not limited to a tensile-strained silicon channel in the tensile-strained silicon layer according to application scenarios, and provides an excellent substrate for an FD / GAAOI device.