107 results about "Short-channel effect" patented technology

The invention discloses an ultra-short channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure capable of resisting a short channel effect and a manufacturing process thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the core design is that a side symmetric P layer forms a strong depletion region, and drain induced barrier lowering (DIBL) and threshold voltage drift are directly inhibited; the top P-layer, the combined P-layer, the rectangular P-layer, the long-strip P-layer and the like form an auxiliary depletion region to further compress channel edge electric field distortion and cooperatively strengthen suppression on a short channel effect, so that the problem of performance degradation caused by shortening of the channel length in an ultra-short channel structure is solved, and the device can still keep stable electrical characteristics under the condition of small size.

The present invention discloses a field-effect transistor device having a blocking region, for use in solving the problem of short-channel effects of field-effect transistors in the prior art. The field-effect transistor device includes an active layer, and the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is switched on, an effective channel and an equivalent source region and an equivalent drain region that are distant from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field-effect transistor device supplies an working current by connecting the source region and the drain region by means of the effective channel, the equivalent source region, and the equivalent drain region; the field-effect transistor further includes a carrier blocking region, and in a plane perpendicular to the length direction of the effective channel, the vertical projections of the equivalent source region and the equivalent drain region are located in the vertical projection of the carrier blocking region.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The embodiment of the invention provides a semiconductor device, a preparation method, a packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for suppressing the short channel effect of the semiconductor device and improving the reliability of the semiconductor device. The semiconductor device comprises a first electrode and a second electrode which are arranged at the top of a substrate, and a first grid electrode arranged between the first electrode and the second electrode, the substrate comprises a fin structure extending towards the top of the substrate, and the top of the fin structure is flush with the top of the substrate; the semiconductor device further comprises a third electrode arranged on the top of the fin structure, a fourth electrode arranged on the side wall of the fin structure and a second grid electrode, and the second grid electrode is located between the third electrode and the fourth electrode.

A semiconductor device and an electronic device are provided. A through hole is formed in an insulating layer and located on a first active layer. A thin-film transistor layer includes a third active layer. At least part of the third active layer is located on a sidewall of the through hole. One side of the third active layer is connected to a first active layer, and the other side of the third active layer is connected to a second active layer, so that a channel length is reduced, short channel effect is reduced, on-state current is increased, and power consumption is reduced.

The invention provides a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. According to the semiconductor device, a first gate structure is arranged in a buried layer on a substrate, and a second gate structure is arranged on the top surface of the first gate structure and the side wall and the top surface of a channel structure; the second gate structure and the first gate structure can be connected and jointly surround the surface of the channel structure, so that a four-side ring gate structure is formed, four-side control of the channel structure can be realized, the control capability of the gate is improved, the short-channel effect is reduced, the structure is simple, the manufacturing process is not complicated, the plane process and the SOI process are compatible, and the manufacturing cost is low. According to the invention, the process difficulty and cost can be greatly reduced, the design has high flexibility and expansibility, the integration with millimeter waves and high-power radio frequency based on the SOI process is easier, and the cost and power consumption can be further reduced.

The invention discloses a vertical channel thin film transistor for a 2T0C DRAM (Dynamic Random Access Memory) and a manufacturing method of the vertical channel thin film transistor. Comprising a substrate, a source electrode deposited on the substrate, an interlayer dielectric layer covering the source electrode, a gate dielectric layer deposited on the surface of the interlayer dielectric layer and a drain electrode arranged in the gate dielectric layer, and the drain electrode forms a conical ring shape; a vertical cylindrical channel is formed in the interlayer dielectric layer, and the bottom of the channel is located in the source electrode; and the vertical cylindrical channel is filled with an active layer. According to the invention, the regulation and control capability of the grid electrode is obviously enhanced through distributed grid electrode control, the short-channel effect is effectively inhibited, the saturation current density is greatly improved, the performance of the transistor is obviously improved, and the transistor is suitable for the fields of artificial intelligence accelerators, storage and calculation integrated chips, high-bandwidth memories and the like and has wide application prospects. And the requirements of high-performance calculation and storage application can be met.

The present application discloses a semiconductor device comprising: a substrate including a first surface and a second surface opposing each other; a gate located on the first surface of the substrate; a source region and a drain region in the substrate located on either side of the gate; and an anti-punchthrough structure in the substrate, the anti-punchthrough structure including a third surface and a fourth surface opposing each other, the third surface being adjacent to and lower than the first surface, the anti-punchthrough structure being located between the source region and the drain region. By providing the anti-punchthrough structure between the source region and the drain region in the substrate, the present application can reduce or avoid the effects of short channel effects, thereby improving device performance.

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate; an effective fin which is suspended above the substrate; and a device gate structure which is located above the substrate and crosses and surrounds the effective fin. By using the above technical scheme, the effective fin can be suspended above the substrate, the device gate structure can cross and surround the effective fin, the contact area between the device gate structure and the effective fin can be increased, the control ability of the device gate structure to the channel can be improved, the short channel effect can be reduced, and thus the performance of the semiconductor structure can be improved.

The embodiment of the present disclosure provides a thin film transistor, a substrate and a preparation method thereof, and a display device. The thin film transistor comprises: a first electrode located on the upper side of a substrate; a first insulating layer located on the upper side of the first electrode; a protruding structure located on the upper side of the first insulating layer and extending along a first direction; an active layer located on the upper side of the protruding structure and comprising a first conductive region, a second conductive region and a channel, the channel crossing the protruding structure along a second direction, and the first conductive region being connected with the first electrode; a second insulating layer located on the upper side of the active layer; a gate electrode located on the upper side of the second insulating layer, and the orthographic projection of the channel on the substrate being located within the orthographic projection of the gate electrode on the substrate; a third insulating layer located on the upper side of the gate electrode; and a second electrode located on the upper side of the third insulating layer and connected with the second conductive region. The technical scheme of the present disclosure can increase the length of the channel and reduce the short channel effect.

According to the gallium nitride device and the electronic equipment provided by the invention, the back barrier layer with non-uniform thickness in the direction from the source electrode to the drain electrode is arranged in the channel layer below the P-GaN layer, the thickness close to the source electrode is larger, and the thickness close to the drain electrode is smaller, so that the region with large thickness can improve the confinement of 2DEG, and the reliability of the device is improved. The channel resistance can be reduced by the area with small thickness, so that the problem that the channel resistance is relatively large or the short channel effect is relatively obvious due to the fact that only the back barrier layer with single thickness is adopted in the traditional design can be avoided by adjusting the thickness of the back barrier layer below the P-GaN layer; according to the invention, the compromise relationship between the short channel effect and the conduction characteristic can be effectively balanced.

The present application relates to the field of semiconductor manufacturing process technology, and provides a dual-gate MOS structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; the substrate comprising a substrate precursor and a shallow trench isolation structure; wherein the substrate precursor comprises an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; a first gate structure precursor is formed in the recessed hole, and a second gate structure is formed on the surface of the active area between the first gate structure precursor and the shallow trench isolation structure; the first gate structure precursor and the substrate precursor are cut using a plane perpendicular to the arrangement direction of the active area as a cutting plane to obtain the substrate, first gate structure, and second gate structure of the dual-gate MOS structure; wherein the contact surface between the first gate structure and the substrate is non-planar. In this way, the short channel effect problem can be improved without occupying additional wafer area.

The invention discloses a memory structure and a forming method thereof. The memory structure comprises a substrate; the channel structure is located on the substrate, the channel structure comprises a bit line region and a source line region, and the material of the channel structure comprises transition metal sulfide; the erasure gate is located on the source line area, the floating gate is located on the source line area, the control gate structure is located on the floating gate, the word line gate is located on the source line area, the floating gate is located between the erasure gate and the word line gate, and the floating gate is made of a graphene material; and the bit line is positioned on the bit line region. Transition metal sulfide is used as a channel material, and a graphene material is used as a floating gate, so that the short channel effect caused by shortening of the channel length is reduced, the problem of electric leakage between the channel and the floating gate is solved, the performance of the memory structure is improved, and the memory area is reduced.

The application discloses a biosensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, and mainly solves the problems of low sensitivity and complex manufacturing process in the prior art. The biosensor comprises, from bottom to top, a substrate (1), a channel region (4), a gate insulating dielectric layer (5), a gate ferroelectric layer (7), a gate titanium nitride layer (8), a gate metal layer (9), a source region (3) and a conductive layer (11). The channel region is provided with drain regions (6) on both sides, the drain regions are provided with isolation grooves (2) on both sides, the gate insulating dielectric layer is provided with biological filling layers (10) on both sides of a vertical part, the channel region adopts an inverted T-shaped structure, the gate insulating dielectric layer adopts a symmetrical L-shaped structure, and the gate metal layer is composed of a lower metal hafnium and an upper metal aluminum. The biosensor has high sensitivity and on-state current, can effectively inhibit short channel effect and bipolar effect, has simple manufacturing process and low manufacturing cost, and can be used for label-free detection of biomolecules.

The application relates to the technical field of semiconductor storage, and discloses a 3D chain ferroelectric storage array structure and a preparation method thereof. The 3D chain ferroelectric storage array structure comprises an alternating medium stack as a base body, a horizontal cavity formed through wet etching, a ring channel transistor prepared in the cavity and surrounding a vertical bit line, and a storage unit formed by integrating a ferroelectric capacitor. The vertical bit line serves as a source-drain electrode, and a horizontal metal gate forms a word line, so that a three-dimensional stacked structure is realized. The preparation process of the application is compatible with the existing NAND process, the gate control capability is effectively improved, the short channel effect is inhibited, and the storage density and the device reliability are improved.

The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a gallium oxide-based fin type solar-blind ultraviolet photoelectric transistor and a preparation method thereof. Comprising a substrate; the Ga2O3 thin film is arranged on the substrate; the periodic fin-type channel structure is located in the region of the Ga2O3 film and is formed by an etching process, the width of a single fin is the same as the interval between adjacent fins, and the height of the fins is equal to the thickness of the Ga2O3 film; the source electrode and the drain electrode are located at the two ends of the fin array of the periodic fin type channel structure respectively and form ohmic contact with the Ga2O3 thin film; the gate dielectric layer covers the surface of the periodic fin type channel structure; and the metal gate electrode covers the surface of the gate dielectric layer to form a surrounding type gate control structure. The method has the advantages that the short channel effect is effectively inhibited through the three-dimensional grid-control structure of the fin-type transistor, and extremely low dark current is kept while the submicron channel length is realized; localization and absorption of solar-blind ultraviolet light in a channel are remarkably enhanced, and quantum efficiency and photoelectric gain are improved.

The application provides a vertical fiber-based organic electrochemical transistor and a preparation method thereof. The transistor comprises a conductive fiber, a first conductive layer as a source electrode is arranged on one end surface of the conductive fiber, an insulating layer is arranged on the surface of the conductive fiber, and the insulating layer is coaxially arranged with the conductive fiber; a second conductive layer as a drain electrode is arranged on the surface of the insulating layer, a source layer as a channel is arranged between the drain electrode and the source electrode; the transistor further comprises a second conductive fiber as a gate electrode, and a gel electrolyte is arranged between the gate electrode and the source electrode and the drain electrode. The vertical transistor structure is prepared, the thickness of the insulating layer is controlled to realize the adjustment of the channel length, the short channel effect is reduced while the short channel is beneficial to the transmission and migration of electrons, and compared with a traditional fiber-based transistor, the vertical fiber-based organic electrochemical transistor has reduced traps caused by the structure, the performance of the transistor is improved, and the transistor can be widely applied to the fields of intelligent wearable and biosensors.

The present invention discloses a transistor with low leakage current and a method for manufacturing the same. The transistor includes a substrate, a gate, multiple spacer layers, multiple liner dielectric layers, a source, and a drain. The gate has a first dielectric constant. The multiple spacer layers have a second dielectric constant. The multiple liner dielectric layers have a third dielectric constant. The source and the drain are adjacent to the multiple spacer layers and are arranged in opposite directions relative to the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other. Therefore, compared with the prior art, the present invention can more effectively reduce gate-induced drain leakage current, short channel effect, off current, or junction leakage current.

The invention relates to the technical field of semiconductor devices, and discloses a power semiconductor device and a preparation method thereof. The method comprises the following steps of: deeply forming a first doped region in a first surface of a substrate, wherein a first spacing distance is formed between the surface of the first doped region and the first surface; a second doped region is deeply formed in the first doped region, the surface of the second doped region is flush with the first surface, and the second doped region and the first doped region are of a second conduction type; a third doped region is formed in the second doped region, the surface of the third doped region is flush with the first surface, and the third doped region and the substrate are of the first conduction type; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface. In the invention, buried layer injection and surface injection are combined to obtain the first doped region and the second doped region, the channel width is effectively reduced, and the problem of physical source-electric field control imbalance of a short channel effect is solved by remodeling the doped structure.

The present invention relates to a semiconductor device structure and a method for fabricating the same. The semiconductor device structure comprises a semiconductor substrate; a gate structure formed on the substrate and first gate sidewall spacers formed on both sides of the gate structure; a channel region formed in the semiconductor substrate below the gate structure, lightly doped regions on both sides of the channel region, and epitaxially grown source and drain regions on both sides of the lightly doped regions; and at least one diffusion barrier region formed below and adjacent to the source and drain regions, respectively, wherein the doping concentration of the diffusion barrier region is higher than that of the channel region. By embedding heavily doped diffusion barrier structures below and between the source and drain regions on both sides of the substrate channel region and below the lightly doped regions, the distribution of doping impurities used to reduce short channel effects and doping impurities used to form source and drain regions is concentrated in a defined region. This effectively reduces short channel effects while maintaining the device's driving capability (Idsat), achieving a balance between device performance and power consumption.

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device and a preparation method, and a packaging structure and an electronic device, which are used for improving the reliability of a semiconductor device while suppressing the short-channel effect of the semiconductor device. The semiconductor device comprises: a first electrode and a second electrode that are arranged on the top of a substrate, and a first gate arranged between the first electrode and the second electrode, wherein the substrate includes a fin structure extending in a direction towards the top of the substrate, and the top of the fin structure is flush with the top of the substrate. The semiconductor device further comprises: a third electrode arranged on the top of the fin structure, a fourth electrode arranged on a side wall of the fin structure, and a second gate, wherein the second gate is located between the third electrode and the fourth electrode.

A transistor, a semiconductor device, a method for manufacturing the same, and an electronic device are disclosed. The transistor is located on a substrate and includes: a first electrode, a second electrode, a first semiconductor layer located between the first electrode and the second electrode, a first gate insulating layer, a second gate insulating layer, and a first gate electrode; the second gate insulating layer is located between the first semiconductor layer and the first gate insulating layer, and is in contact with the semiconductor layer; the second gate insulating layer is configured to provide holes or electrons to the first semiconductor layer under the condition of an electric field applied to the transistor, thereby converting the first semiconductor layer from a first polarity type to a second polarity type; the first polarity type and the second polarity type have opposite polarities; the first semiconductor layer includes a first two-dimensional semiconductor material. The transistor and semiconductor device of this application embodiment use a two-dimensional semiconductor material to form the channel, which improves carrier mobility and reduces the influence of short-channel effects.

The present application discloses a driving backplane, a preparation method thereof, and a display panel. The driving backplane includes a substrate, an oxide semiconductor layer, an aluminum oxide layer, a silicon oxide layer, a source electrode, a drain electrode, and a gate electrode. The oxide semiconductor layer is arranged on the substrate and includes a channel and a source contact portion and a drain contact portion located on opposite sides of the channel; the aluminum oxide layer covers the surface of the oxide semiconductor layer, and an opening is provided in the aluminum oxide layer, exposing the channel; the silicon oxide layer is arranged on the side of the aluminum oxide layer away from the oxide semiconductor layer, the silicon oxide layer fills the opening, and contacts with the surface of the channel; the source electrode and the drain electrode are arranged on the side of the silicon oxide layer away from the aluminum oxide layer; the gate electrode is arranged on the side of the oxide semiconductor layer close to the substrate or the side of the silicon oxide layer close to the source electrode. The present application improves the short channel effect in the existing driving backplane and realizes the miniaturized design of thin film transistors.

Provided in the present application is a manufacturing method for a semiconductor device. A buried oxide layer and a channel layer are sequentially stacked on a substrate. A gate electrode on the channel layer, a source electrode in contact with one end of the channel layer, and a drain electrode in contact with the other end of the channel layer are formed. A first dimension of the channel layer in a first direction on the surface of the substrate is greater than a second dimension of the gate electrode in the first direction, the difference between the first dimension and the second dimension is negatively correlated with the second dimension, and the first direction is the direction of a connecting line between the source electrode and the drain electrode. That is to say, the length of the channel layer is greater than the length of the gate electrode, and the greater the length of the gate electrode, the smaller the length difference between the two, bringing the channel layer and the gate electrode closer to each other. Thus, as the length of the gate electrode decreases, the extent of reduction in the channel layer is relatively small, which is conducive to suppressing short-channel effects. Moreover, for scenarios where the length of the gate electrode is relatively large, the length of the channel layer approximates that of the gate electrode, which avoids the problem of excessive series resistance caused by an overly long channel layer, thereby effectively providing a short-channel effect suppression capability and a higher on-state current.

The invention discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device comprises a semiconductor substrate, a drain electrode, a source electrode and a grid electrode, the grid electrode comprises at least one layer of polycrystalline silicon; a source region corresponding to the source electrode and a drain region corresponding to the drain electrode are arranged in the semiconductor substrate, and a channel region is arranged between the source region and the drain region; the grid electrode is arranged on the channel region; gate oxide layers are arranged at the connection position of the grid electrode and the channel region and the connection position of the grid electrode and the source electrode; the surface of the gate and the surface of the source are at the same height, and the surface of the gate is higher than the surface of the drain and forms a step structure. By means of the technical scheme, the hot carrier effect and the short channel effect can be improved, and the electrical performance of the semiconductor device is improved.

An embodiment inverter circuit may include a gate electrode formed over an interlayer dielectric layer, a gate dielectric layer formed over the gate electrode, a first-conductivity-type semiconductor layer formed over the gate dielectric layer, a second-conductivity-type semiconductor layer formed over the gate dielectric layer and laterally displaced from the first-conductivity-type semiconductor layer, a first source electrode formed in contact with the first-conductivity-type semiconductor layer, a second source electrode formed in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode formed in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer may include a metal-oxide semiconductor and / or a multi-layer structure formed in a back-end-of-line (BEOL) process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.

The present invention discloses an equivalent source and drain region optimized field-effect transistor device for solving the problem of short-channel effects of a field-effect transistor in the prior art. The field-effect transistor device includes an active layer, and the active layer includes a source region, a drain region and a channel region located between the source region and the drain region; when the device is on, an effective channel and an equivalent source region and an equivalent drain region away from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field-effect transistor device communicates the source region and the drain region via the effective channel and the equivalent source region and the equivalent drain region to contribute a working current, wherein the length of the equivalent source region is greater than that of the equivalent drain region.

The application provides an image sensor pixel structure, comprising a plurality of arrayed pixel units, each pixel unit comprising: a semiconductor substrate having opposite first and second surfaces; a photoelectric conversion region extending into the semiconductor substrate from the first surface to form a photoelectric conversion element; a floating diffusion region extending into the semiconductor substrate from the first surface; and a transfer transistor coupled between the photoelectric conversion region and the floating diffusion region, the transfer transistor comprising a transfer gate, wherein the extension path of the transfer gate passes through the center point of the first surface, and the extension direction of the transfer gate forms an angle Q with the first diagonal direction of the first surface, 0°≤Q<5°. The application also provides an image sensor. In the application, the pixel array is rotated by a certain angle, the transfer gate is arranged in the diagonal direction of the pixel unit surface, the area of the transfer gate is increased in the lateral length, and the problems of short channel effect and narrow channel effect caused by the too small size of the transfer gate are solved.

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate containing silicon, and forming a grid electrode and a grid electrode side wall on the surface of the substrate; a protective layer is formed, the protective layer is made of the same material as the grid electrode side wall, the protective layer covers the surface of the substrate, the top of the grid electrode and the grid electrode side wall, and the protective layer and the substrate have different etching selection ratios; the sum of the thickness of the protective layer and the thickness of the gate side wall is equal to the target thickness; and after the doping process and the annealing process are executed, removing the protective layer located at the top of the grid electrode and on the surface of the substrate, and reserving the protective layer covering the side wall of the grid electrode. According to the semiconductor structure, oxidation of the silicon surface of the substrate and material loss caused by the photoresist removing and cleaning steps in the doping process are solved, the short-channel effect is restrained, the substrate is prevented from being damaged in the process of removing the protection layer, and the electrical stability of the semiconductor structure is improved through collaborative design of the protection layer and the grid side wall.

The invention provides a semiconductor device and a preparation method thereof, a substrate is internally provided with a plurality of source and drain trenches which are distributed at intervals, and the source and drain trenches extend into the substrate from the surface of the substrate; forming a first embedded epitaxial layer in the source-drain groove, wherein the source-drain groove is filled with the first embedded epitaxial layer; forming a second embedded epitaxial layer on the first embedded epitaxial layer, wherein the second embedded epitaxial layer covers the top surface of the first embedded epitaxial layer and the exposed part of the top surface of the substrate; and forming a cap layer on the second embedded epitaxial layer. According to the invention, the substrate and the cap layer are separated by using the second embedded epitaxial layer, and the cap layer cannot be in contact with the substrate, so that doped ions in the cap layer are prevented from being diffused into a channel in the substrate, and the short-channel effect is further improved; the first embedded epitaxial layer and the second embedded epitaxial layer can provide pressure stress for the channel together without causing adverse effects on the device, and the process for preparing the second embedded epitaxial layer is relatively simple and low in cost.