140 results about "Short-channel effect" patented technology

The invention discloses an ultra-short channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure capable of resisting a short channel effect and a manufacturing process thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the core design is that a side symmetric P layer forms a strong depletion region, and drain induced barrier lowering (DIBL) and threshold voltage drift are directly inhibited; the top P-layer, the combined P-layer, the rectangular P-layer, the long-strip P-layer and the like form an auxiliary depletion region to further compress channel edge electric field distortion and cooperatively strengthen suppression on a short channel effect, so that the problem of performance degradation caused by shortening of the channel length in an ultra-short channel structure is solved, and the device can still keep stable electrical characteristics under the condition of small size.

Device scaling has increased the device density of integrated circuits (ICs) and reduced the cost of circuits. Today development of new device structures, use of new materials and complex process steps are implemented to continue scaling of the semiconductor devices. The added manufacturing steps and complexity have increased cost of ICs directly impacting the implementation of IoT devices that need low cost and high yields to be successful. ALEFT-M-LTSEE is a device that reduces cost while improving device performance by S / D resistance reduction. ALEFT-M-LTSEE enable scaling of gate and channel lengths while reducing impact of random threshold variation due to discrete dopants in and around the channel. By creating a flat field profile at the gate by use of low temperature epitaxy as source / drain extension, the short channel effects, and the impact of line edge variations of the gate are reduced.

The present invention discloses a field-effect transistor device having a blocking region, for use in solving the problem of short-channel effects of field-effect transistors in the prior art. The field-effect transistor device includes an active layer, and the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is switched on, an effective channel and an equivalent source region and an equivalent drain region that are distant from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field-effect transistor device supplies an working current by connecting the source region and the drain region by means of the effective channel, the equivalent source region, and the equivalent drain region; the field-effect transistor further includes a carrier blocking region, and in a plane perpendicular to the length direction of the effective channel, the vertical projections of the equivalent source region and the equivalent drain region are located in the vertical projection of the carrier blocking region.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a plurality of gate structures on the substrate, and forming a preprocessing groove in the substrate between two adjacent gate structures; forming an expansion layer on the inner wall of the pretreatment groove; etching to remove the part, located at the bottom of the pretreatment groove, in the expansion layer, so that the residual expansion layer covers the side wall of the pretreatment groove, and etching the substrate below the pretreatment groove to form an initial groove based on the pretreatment groove; etching the part, which is not covered by the expansion layer, in the initial groove and forming a sigma groove; removing the residual expansion layer; an epitaxial layer is formed in the sigma groove, the epitaxial layer comprises a buffer layer, a middle layer and a cap layer which are sequentially stacked from bottom to top, and the buffer layer completely covers the inner wall of the sigma groove. The diffusion of elements in the intermediate layer into the substrate is reduced or avoided, so that the short-channel effect of the semiconductor device is reduced or even avoided.

The embodiment of the invention provides a semiconductor device, a preparation method, a packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for suppressing the short channel effect of the semiconductor device and improving the reliability of the semiconductor device. The semiconductor device comprises a first electrode and a second electrode which are arranged at the top of a substrate, and a first grid electrode arranged between the first electrode and the second electrode, the substrate comprises a fin structure extending towards the top of the substrate, and the top of the fin structure is flush with the top of the substrate; the semiconductor device further comprises a third electrode arranged on the top of the fin structure, a fourth electrode arranged on the side wall of the fin structure and a second grid electrode, and the second grid electrode is located between the third electrode and the fourth electrode.

The invention discloses a two-dimensional semiconductor device and a preparation method thereof, the device comprises a substrate, a two-dimensional semiconductor material layer and a gate structure, the gate structure comprises a gate dielectric layer and a gate layer, and the gate dielectric layer comprises a part covered by the bottom of the gate and a part not covered by the bottom of the gate. Parts which are not covered by the bottom of the grid respectively extend outwards along the surface of the semiconductor layer; side walls cover the part, not covered by the bottom of the grid electrode, of the grid dielectric layer and the two sides of the grid electrode; supporting layers are arranged on the surfaces of the side walls; and the side wall, the two-dimensional semiconductor material layer and the substrate penetrate through the active drain metal contact layer from top to bottom along the supporting layer. According to the invention, the metal yttrium is deposited on the two-dimensional semiconductor material layer and cleaned to leave the yttrium seed crystal, and the high-performance gate structure is obtained by taking the metal yttrium as the seed crystal, so that the sub-threshold swing and contact resistance of the device are remarkably reduced, the short channel effect is effectively inhibited, the channel defect is reduced, and the overall performance, yield and reliability of the device are remarkably improved.

A semiconductor device and an electronic device are provided. A through hole is formed in an insulating layer and located on a first active layer. A thin-film transistor layer includes a third active layer. At least part of the third active layer is located on a sidewall of the through hole. One side of the third active layer is connected to a first active layer, and the other side of the third active layer is connected to a second active layer, so that a channel length is reduced, short channel effect is reduced, on-state current is increased, and power consumption is reduced.

The invention discloses a vertical silicon nanowire-based full-gate-around photovoltaic field effect transistor and a preparation method thereof, the photovoltaic field effect transistor takes a vertical silicon nanowire as a channel, transforms a transverse width into a longitudinal depth, is easier to realize physical isolation of a single device in a large-scale array, and improves the reliability of the whole-gate-around photovoltaic field effect transistor. And meanwhile, the integration level of the photovoltaic field effect transistor is greatly improved. The silicon nanowires penetrate through the two-dimensional material film, and the two-dimensional material film wraps the silicon nanowires in a full surrounding mode according to the atomic layer thickness to form a ring gate structure. The ring gate structure depends on the excellent mechanical flexibility of the two-dimensional material and the nanoscale lossless modification of the spherical probe of the atomic force microscope. By means of an atomic force microscope ball probe interface processing technology, the invention provides a novel method for preparing a transistor with a sub-nanometer size grid electrode, and the photovoltaic transistor structure not only effectively inhibits the short channel effect, but also remarkably improves the efficient integration capability of a two-dimensional material and a silicon-based CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device.

The present invention discloses an SGT MOSFET device for suppressing short channel effect and a preparation method thereof, wherein the device comprises a substrate, a first epitaxial layer, a second epitaxial layer, and a metal layer stacked in sequence from bottom to top; a first groove extending into the first epitaxial layer is provided on the upper surface of the second epitaxial layer, and a first ion implantation region and a second ion implantation region are provided on the upper surface of the second epitaxial layer on both sides of the first groove; the second epitaxial layer between the first ion implantation region and the first epitaxial layer and the second epitaxial layer between the first ion implantation region and the first groove form a first ion isolation region, and the second epitaxial layer between the second ion implantation region and the first epitaxial layer and the second epitaxial layer between the second ion implantation region and the first groove form a second ion isolation region. In the SGT MOSFET device provided by the present invention, the N isolation layer can reduce the doping concentration of the device drift region, improve the electric field distribution, thereby suppressing the short channel effect and improving the device performance.

The invention provides a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. According to the semiconductor device, a first gate structure is arranged in a buried layer on a substrate, and a second gate structure is arranged on the top surface of the first gate structure and the side wall and the top surface of a channel structure; the second gate structure and the first gate structure can be connected and jointly surround the surface of the channel structure, so that a four-side ring gate structure is formed, four-side control of the channel structure can be realized, the control capability of the gate is improved, the short-channel effect is reduced, the structure is simple, the manufacturing process is not complicated, the plane process and the SOI process are compatible, and the manufacturing cost is low. According to the invention, the process difficulty and cost can be greatly reduced, the design has high flexibility and expansibility, the integration with millimeter waves and high-power radio frequency based on the SOI process is easier, and the cost and power consumption can be further reduced.

The invention discloses a vertical channel thin film transistor for a 2T0C DRAM (Dynamic Random Access Memory) and a manufacturing method of the vertical channel thin film transistor. Comprising a substrate, a source electrode deposited on the substrate, an interlayer dielectric layer covering the source electrode, a gate dielectric layer deposited on the surface of the interlayer dielectric layer and a drain electrode arranged in the gate dielectric layer, and the drain electrode forms a conical ring shape; a vertical cylindrical channel is formed in the interlayer dielectric layer, and the bottom of the channel is located in the source electrode; and the vertical cylindrical channel is filled with an active layer. According to the invention, the regulation and control capability of the grid electrode is obviously enhanced through distributed grid electrode control, the short-channel effect is effectively inhibited, the saturation current density is greatly improved, the performance of the transistor is obviously improved, and the transistor is suitable for the fields of artificial intelligence accelerators, storage and calculation integrated chips, high-bandwidth memories and the like and has wide application prospects. And the requirements of high-performance calculation and storage application can be met.

The present application discloses a semiconductor device comprising: a substrate including a first surface and a second surface opposing each other; a gate located on the first surface of the substrate; a source region and a drain region in the substrate located on either side of the gate; and an anti-punchthrough structure in the substrate, the anti-punchthrough structure including a third surface and a fourth surface opposing each other, the third surface being adjacent to and lower than the first surface, the anti-punchthrough structure being located between the source region and the drain region. By providing the anti-punchthrough structure between the source region and the drain region in the substrate, the present application can reduce or avoid the effects of short channel effects, thereby improving device performance.

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate; an effective fin which is suspended above the substrate; and a device gate structure which is located above the substrate and crosses and surrounds the effective fin. By using the above technical scheme, the effective fin can be suspended above the substrate, the device gate structure can cross and surround the effective fin, the contact area between the device gate structure and the effective fin can be increased, the control ability of the device gate structure to the channel can be improved, the short channel effect can be reduced, and thus the performance of the semiconductor structure can be improved.

The embodiment of the present disclosure provides a thin film transistor, a substrate and a preparation method thereof, and a display device. The thin film transistor comprises: a first electrode located on the upper side of a substrate; a first insulating layer located on the upper side of the first electrode; a protruding structure located on the upper side of the first insulating layer and extending along a first direction; an active layer located on the upper side of the protruding structure and comprising a first conductive region, a second conductive region and a channel, the channel crossing the protruding structure along a second direction, and the first conductive region being connected with the first electrode; a second insulating layer located on the upper side of the active layer; a gate electrode located on the upper side of the second insulating layer, and the orthographic projection of the channel on the substrate being located within the orthographic projection of the gate electrode on the substrate; a third insulating layer located on the upper side of the gate electrode; and a second electrode located on the upper side of the third insulating layer and connected with the second conductive region. The technical scheme of the present disclosure can increase the length of the channel and reduce the short channel effect.

According to the gallium nitride device and the electronic equipment provided by the invention, the back barrier layer with non-uniform thickness in the direction from the source electrode to the drain electrode is arranged in the channel layer below the P-GaN layer, the thickness close to the source electrode is larger, and the thickness close to the drain electrode is smaller, so that the region with large thickness can improve the confinement of 2DEG, and the reliability of the device is improved. The channel resistance can be reduced by the area with small thickness, so that the problem that the channel resistance is relatively large or the short channel effect is relatively obvious due to the fact that only the back barrier layer with single thickness is adopted in the traditional design can be avoided by adjusting the thickness of the back barrier layer below the P-GaN layer; according to the invention, the compromise relationship between the short channel effect and the conduction characteristic can be effectively balanced.

The present application relates to the field of semiconductor manufacturing process technology, and provides a dual-gate MOS structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; the substrate comprising a substrate precursor and a shallow trench isolation structure; wherein the substrate precursor comprises an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; a first gate structure precursor is formed in the recessed hole, and a second gate structure is formed on the surface of the active area between the first gate structure precursor and the shallow trench isolation structure; the first gate structure precursor and the substrate precursor are cut using a plane perpendicular to the arrangement direction of the active area as a cutting plane to obtain the substrate, first gate structure, and second gate structure of the dual-gate MOS structure; wherein the contact surface between the first gate structure and the substrate is non-planar. In this way, the short channel effect problem can be improved without occupying additional wafer area.

The invention provides a flash memory type storage and calculation integrated circuit, an error elimination method of the flash memory type storage and calculation integrated circuit and a medium, the flash memory type storage and calculation integrated circuit comprises a plurality of flash memory transistors, and the flash memory transistors have a short channel effect, so that the current of the flash memory transistors in a saturation region is not in a saturation state any more; the non-linear error of the flash memory type storage and calculation integrated circuit can be reduced by directly utilizing the short channel effect of the plurality of flash memory transistors, so that the calculation precision of the flash memory type storage and calculation integrated circuit is further improved.

The invention discloses a memory structure and a forming method thereof. The memory structure comprises a substrate; the channel structure is located on the substrate, the channel structure comprises a bit line region and a source line region, and the material of the channel structure comprises transition metal sulfide; the erasure gate is located on the source line area, the floating gate is located on the source line area, the control gate structure is located on the floating gate, the word line gate is located on the source line area, the floating gate is located between the erasure gate and the word line gate, and the floating gate is made of a graphene material; and the bit line is positioned on the bit line region. Transition metal sulfide is used as a channel material, and a graphene material is used as a floating gate, so that the short channel effect caused by shortening of the channel length is reduced, the problem of electric leakage between the channel and the floating gate is solved, the performance of the memory structure is improved, and the memory area is reduced.

The present invention relates to a CMOS image sensor and an associated forming method, the CMOS image sensor having a doped isolation structure separating a photodiode from a pixel device. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode from a pixel device. The photodiode is disposed within the substrate on the front side away from the substrate. The pixel device is disposed at the front side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Compared to previous image sensor designs in which the upper portion of the photodiode is typically disposed at the top surface of the front side of the substrate, the photodiode is now disposed away from the top surface and more space is left for the pixel device. Accordingly, larger pixel devices can be disposed in the sensing pixels, and the short channel effect and the noise level can be improved.

In some implementations, a buffer layer is formed under a source / drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source / drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a substrate with a projection structure; the channel structure layer is suspended on the convex structure, the channel structure layer comprises one or more channel layers which are sequentially arranged at intervals from bottom to top, and the length of the channel layers is larger than that of the convex structure; the source-drain doping layer is located on the substrate on the two sides of the channel structure layer along the length direction of the channel layer and is connected with the two ends of the channel layer; and the gate structure is located between the source and drain doping layers, the gate structure stretches across the channel structure layer and surrounds the channel layer, and the gate structure further covers the tops of the protruding structures and the side walls of the protruding structures. According to the embodiment of the invention, the length of the gate structure and the length of the channel are increased, the control force of the gate structure on the channel is correspondingly increased, the short channel effect is improved, and the leakage current of a sub-threshold device is reduced, so that larger driving current can be obtained, and the performance of the semiconductor structure is improved.

The application discloses a biosensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, and mainly solves the problems of low sensitivity and complex manufacturing process in the prior art. The biosensor comprises, from bottom to top, a substrate (1), a channel region (4), a gate insulating dielectric layer (5), a gate ferroelectric layer (7), a gate titanium nitride layer (8), a gate metal layer (9), a source region (3) and a conductive layer (11). The channel region is provided with drain regions (6) on both sides, the drain regions are provided with isolation grooves (2) on both sides, the gate insulating dielectric layer is provided with biological filling layers (10) on both sides of a vertical part, the channel region adopts an inverted T-shaped structure, the gate insulating dielectric layer adopts a symmetrical L-shaped structure, and the gate metal layer is composed of a lower metal hafnium and an upper metal aluminum. The biosensor has high sensitivity and on-state current, can effectively inhibit short channel effect and bipolar effect, has simple manufacturing process and low manufacturing cost, and can be used for label-free detection of biomolecules.

Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

The application relates to the technical field of semiconductor storage, and discloses a 3D chain ferroelectric storage array structure and a preparation method thereof. The 3D chain ferroelectric storage array structure comprises an alternating medium stack as a base body, a horizontal cavity formed through wet etching, a ring channel transistor prepared in the cavity and surrounding a vertical bit line, and a storage unit formed by integrating a ferroelectric capacitor. The vertical bit line serves as a source-drain electrode, and a horizontal metal gate forms a word line, so that a three-dimensional stacked structure is realized. The preparation process of the application is compatible with the existing NAND process, the gate control capability is effectively improved, the short channel effect is inhibited, and the storage density and the device reliability are improved.

The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a gallium oxide-based fin type solar-blind ultraviolet photoelectric transistor and a preparation method thereof. Comprising a substrate; the Ga2O3 thin film is arranged on the substrate; the periodic fin-type channel structure is located in the region of the Ga2O3 film and is formed by an etching process, the width of a single fin is the same as the interval between adjacent fins, and the height of the fins is equal to the thickness of the Ga2O3 film; the source electrode and the drain electrode are located at the two ends of the fin array of the periodic fin type channel structure respectively and form ohmic contact with the Ga2O3 thin film; the gate dielectric layer covers the surface of the periodic fin type channel structure; and the metal gate electrode covers the surface of the gate dielectric layer to form a surrounding type gate control structure. The method has the advantages that the short channel effect is effectively inhibited through the three-dimensional grid-control structure of the fin-type transistor, and extremely low dark current is kept while the submicron channel length is realized; localization and absorption of solar-blind ultraviolet light in a channel are remarkably enhanced, and quantum efficiency and photoelectric gain are improved.

The application provides a vertical fiber-based organic electrochemical transistor and a preparation method thereof. The transistor comprises a conductive fiber, a first conductive layer as a source electrode is arranged on one end surface of the conductive fiber, an insulating layer is arranged on the surface of the conductive fiber, and the insulating layer is coaxially arranged with the conductive fiber; a second conductive layer as a drain electrode is arranged on the surface of the insulating layer, a source layer as a channel is arranged between the drain electrode and the source electrode; the transistor further comprises a second conductive fiber as a gate electrode, and a gel electrolyte is arranged between the gate electrode and the source electrode and the drain electrode. The vertical transistor structure is prepared, the thickness of the insulating layer is controlled to realize the adjustment of the channel length, the short channel effect is reduced while the short channel is beneficial to the transmission and migration of electrons, and compared with a traditional fiber-based transistor, the vertical fiber-based organic electrochemical transistor has reduced traps caused by the structure, the performance of the transistor is improved, and the transistor can be widely applied to the fields of intelligent wearable and biosensors.

The present invention discloses a transistor with low leakage current and a method for manufacturing the same. The transistor includes a substrate, a gate, multiple spacer layers, multiple liner dielectric layers, a source, and a drain. The gate has a first dielectric constant. The multiple spacer layers have a second dielectric constant. The multiple liner dielectric layers have a third dielectric constant. The source and the drain are adjacent to the multiple spacer layers and are arranged in opposite directions relative to the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other. Therefore, compared with the prior art, the present invention can more effectively reduce gate-induced drain leakage current, short channel effect, off current, or junction leakage current.

The invention relates to the technical field of semiconductor devices, and discloses a power semiconductor device and a preparation method thereof. The method comprises the following steps of: deeply forming a first doped region in a first surface of a substrate, wherein a first spacing distance is formed between the surface of the first doped region and the first surface; a second doped region is deeply formed in the first doped region, the surface of the second doped region is flush with the first surface, and the second doped region and the first doped region are of a second conduction type; a third doped region is formed in the second doped region, the surface of the third doped region is flush with the first surface, and the third doped region and the substrate are of the first conduction type; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface. In the invention, buried layer injection and surface injection are combined to obtain the first doped region and the second doped region, the channel width is effectively reduced, and the problem of physical source-electric field control imbalance of a short channel effect is solved by remodeling the doped structure.

The present invention relates to a semiconductor device structure and a method for fabricating the same. The semiconductor device structure comprises a semiconductor substrate; a gate structure formed on the substrate and first gate sidewall spacers formed on both sides of the gate structure; a channel region formed in the semiconductor substrate below the gate structure, lightly doped regions on both sides of the channel region, and epitaxially grown source and drain regions on both sides of the lightly doped regions; and at least one diffusion barrier region formed below and adjacent to the source and drain regions, respectively, wherein the doping concentration of the diffusion barrier region is higher than that of the channel region. By embedding heavily doped diffusion barrier structures below and between the source and drain regions on both sides of the substrate channel region and below the lightly doped regions, the distribution of doping impurities used to reduce short channel effects and doping impurities used to form source and drain regions is concentrated in a defined region. This effectively reduces short channel effects while maintaining the device's driving capability (Idsat), achieving a balance between device performance and power consumption.