67 results about "Short-channel effect" patented technology

The present invention discloses a field-effect transistor device having a blocking region, for use in solving the problem of short-channel effects of field-effect transistors in the prior art. The field-effect transistor device includes an active layer, and the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is switched on, an effective channel and an equivalent source region and an equivalent drain region that are distant from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field-effect transistor device supplies an working current by connecting the source region and the drain region by means of the effective channel, the equivalent source region, and the equivalent drain region; the field-effect transistor further includes a carrier blocking region, and in a plane perpendicular to the length direction of the effective channel, the vertical projections of the equivalent source region and the equivalent drain region are located in the vertical projection of the carrier blocking region.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

A semiconductor device and an electronic device are provided. A through hole is formed in an insulating layer and located on a first active layer. A thin-film transistor layer includes a third active layer. At least part of the third active layer is located on a sidewall of the through hole. One side of the third active layer is connected to a first active layer, and the other side of the third active layer is connected to a second active layer, so that a channel length is reduced, short channel effect is reduced, on-state current is increased, and power consumption is reduced.

The invention provides a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. According to the semiconductor device, a first gate structure is arranged in a buried layer on a substrate, and a second gate structure is arranged on the top surface of the first gate structure and the side wall and the top surface of a channel structure; the second gate structure and the first gate structure can be connected and jointly surround the surface of the channel structure, so that a four-side ring gate structure is formed, four-side control of the channel structure can be realized, the control capability of the gate is improved, the short-channel effect is reduced, the structure is simple, the manufacturing process is not complicated, the plane process and the SOI process are compatible, and the manufacturing cost is low. According to the invention, the process difficulty and cost can be greatly reduced, the design has high flexibility and expansibility, the integration with millimeter waves and high-power radio frequency based on the SOI process is easier, and the cost and power consumption can be further reduced.

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate; an effective fin which is suspended above the substrate; and a device gate structure which is located above the substrate and crosses and surrounds the effective fin. By using the above technical scheme, the effective fin can be suspended above the substrate, the device gate structure can cross and surround the effective fin, the contact area between the device gate structure and the effective fin can be increased, the control ability of the device gate structure to the channel can be improved, the short channel effect can be reduced, and thus the performance of the semiconductor structure can be improved.

The embodiment of the present disclosure provides a thin film transistor, a substrate and a preparation method thereof, and a display device. The thin film transistor comprises: a first electrode located on the upper side of a substrate; a first insulating layer located on the upper side of the first electrode; a protruding structure located on the upper side of the first insulating layer and extending along a first direction; an active layer located on the upper side of the protruding structure and comprising a first conductive region, a second conductive region and a channel, the channel crossing the protruding structure along a second direction, and the first conductive region being connected with the first electrode; a second insulating layer located on the upper side of the active layer; a gate electrode located on the upper side of the second insulating layer, and the orthographic projection of the channel on the substrate being located within the orthographic projection of the gate electrode on the substrate; a third insulating layer located on the upper side of the gate electrode; and a second electrode located on the upper side of the third insulating layer and connected with the second conductive region. The technical scheme of the present disclosure can increase the length of the channel and reduce the short channel effect.

According to the gallium nitride device and the electronic equipment provided by the invention, the back barrier layer with non-uniform thickness in the direction from the source electrode to the drain electrode is arranged in the channel layer below the P-GaN layer, the thickness close to the source electrode is larger, and the thickness close to the drain electrode is smaller, so that the region with large thickness can improve the confinement of 2DEG, and the reliability of the device is improved. The channel resistance can be reduced by the area with small thickness, so that the problem that the channel resistance is relatively large or the short channel effect is relatively obvious due to the fact that only the back barrier layer with single thickness is adopted in the traditional design can be avoided by adjusting the thickness of the back barrier layer below the P-GaN layer; according to the invention, the compromise relationship between the short channel effect and the conduction characteristic can be effectively balanced.

The application discloses a biosensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, and mainly solves the problems of low sensitivity and complex manufacturing process in the prior art. The biosensor comprises, from bottom to top, a substrate (1), a channel region (4), a gate insulating dielectric layer (5), a gate ferroelectric layer (7), a gate titanium nitride layer (8), a gate metal layer (9), a source region (3) and a conductive layer (11). The channel region is provided with drain regions (6) on both sides, the drain regions are provided with isolation grooves (2) on both sides, the gate insulating dielectric layer is provided with biological filling layers (10) on both sides of a vertical part, the channel region adopts an inverted T-shaped structure, the gate insulating dielectric layer adopts a symmetrical L-shaped structure, and the gate metal layer is composed of a lower metal hafnium and an upper metal aluminum. The biosensor has high sensitivity and on-state current, can effectively inhibit short channel effect and bipolar effect, has simple manufacturing process and low manufacturing cost, and can be used for label-free detection of biomolecules.

The application relates to the technical field of semiconductor storage, and discloses a 3D chain ferroelectric storage array structure and a preparation method thereof. The 3D chain ferroelectric storage array structure comprises an alternating medium stack as a base body, a horizontal cavity formed through wet etching, a ring channel transistor prepared in the cavity and surrounding a vertical bit line, and a storage unit formed by integrating a ferroelectric capacitor. The vertical bit line serves as a source-drain electrode, and a horizontal metal gate forms a word line, so that a three-dimensional stacked structure is realized. The preparation process of the application is compatible with the existing NAND process, the gate control capability is effectively improved, the short channel effect is inhibited, and the storage density and the device reliability are improved.

The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a gallium oxide-based fin type solar-blind ultraviolet photoelectric transistor and a preparation method thereof. Comprising a substrate; the Ga2O3 thin film is arranged on the substrate; the periodic fin-type channel structure is located in the region of the Ga2O3 film and is formed by an etching process, the width of a single fin is the same as the interval between adjacent fins, and the height of the fins is equal to the thickness of the Ga2O3 film; the source electrode and the drain electrode are located at the two ends of the fin array of the periodic fin type channel structure respectively and form ohmic contact with the Ga2O3 thin film; the gate dielectric layer covers the surface of the periodic fin type channel structure; and the metal gate electrode covers the surface of the gate dielectric layer to form a surrounding type gate control structure. The method has the advantages that the short channel effect is effectively inhibited through the three-dimensional grid-control structure of the fin-type transistor, and extremely low dark current is kept while the submicron channel length is realized; localization and absorption of solar-blind ultraviolet light in a channel are remarkably enhanced, and quantum efficiency and photoelectric gain are improved.

The application provides a vertical fiber-based organic electrochemical transistor and a preparation method thereof. The transistor comprises a conductive fiber, a first conductive layer as a source electrode is arranged on one end surface of the conductive fiber, an insulating layer is arranged on the surface of the conductive fiber, and the insulating layer is coaxially arranged with the conductive fiber; a second conductive layer as a drain electrode is arranged on the surface of the insulating layer, a source layer as a channel is arranged between the drain electrode and the source electrode; the transistor further comprises a second conductive fiber as a gate electrode, and a gel electrolyte is arranged between the gate electrode and the source electrode and the drain electrode. The vertical transistor structure is prepared, the thickness of the insulating layer is controlled to realize the adjustment of the channel length, the short channel effect is reduced while the short channel is beneficial to the transmission and migration of electrons, and compared with a traditional fiber-based transistor, the vertical fiber-based organic electrochemical transistor has reduced traps caused by the structure, the performance of the transistor is improved, and the transistor can be widely applied to the fields of intelligent wearable and biosensors.

The invention relates to the technical field of semiconductor devices, and discloses a power semiconductor device and a preparation method thereof. The method comprises the following steps of: deeply forming a first doped region in a first surface of a substrate, wherein a first spacing distance is formed between the surface of the first doped region and the first surface; a second doped region is deeply formed in the first doped region, the surface of the second doped region is flush with the first surface, and the second doped region and the first doped region are of a second conduction type; a third doped region is formed in the second doped region, the surface of the third doped region is flush with the first surface, and the third doped region and the substrate are of the first conduction type; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface. In the invention, buried layer injection and surface injection are combined to obtain the first doped region and the second doped region, the channel width is effectively reduced, and the problem of physical source-electric field control imbalance of a short channel effect is solved by remodeling the doped structure.

A transistor, a semiconductor device, a method for manufacturing the same, and an electronic device are disclosed. The transistor is located on a substrate and includes: a first electrode, a second electrode, a first semiconductor layer located between the first electrode and the second electrode, a first gate insulating layer, a second gate insulating layer, and a first gate electrode; the second gate insulating layer is located between the first semiconductor layer and the first gate insulating layer, and is in contact with the semiconductor layer; the second gate insulating layer is configured to provide holes or electrons to the first semiconductor layer under the condition of an electric field applied to the transistor, thereby converting the first semiconductor layer from a first polarity type to a second polarity type; the first polarity type and the second polarity type have opposite polarities; the first semiconductor layer includes a first two-dimensional semiconductor material. The transistor and semiconductor device of this application embodiment use a two-dimensional semiconductor material to form the channel, which improves carrier mobility and reduces the influence of short-channel effects.

Provided in the present application is a manufacturing method for a semiconductor device. A buried oxide layer and a channel layer are sequentially stacked on a substrate. A gate electrode on the channel layer, a source electrode in contact with one end of the channel layer, and a drain electrode in contact with the other end of the channel layer are formed. A first dimension of the channel layer in a first direction on the surface of the substrate is greater than a second dimension of the gate electrode in the first direction, the difference between the first dimension and the second dimension is negatively correlated with the second dimension, and the first direction is the direction of a connecting line between the source electrode and the drain electrode. That is to say, the length of the channel layer is greater than the length of the gate electrode, and the greater the length of the gate electrode, the smaller the length difference between the two, bringing the channel layer and the gate electrode closer to each other. Thus, as the length of the gate electrode decreases, the extent of reduction in the channel layer is relatively small, which is conducive to suppressing short-channel effects. Moreover, for scenarios where the length of the gate electrode is relatively large, the length of the channel layer approximates that of the gate electrode, which avoids the problem of excessive series resistance caused by an overly long channel layer, thereby effectively providing a short-channel effect suppression capability and a higher on-state current.

The invention discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device comprises a semiconductor substrate, a drain electrode, a source electrode and a grid electrode, the grid electrode comprises at least one layer of polycrystalline silicon; a source region corresponding to the source electrode and a drain region corresponding to the drain electrode are arranged in the semiconductor substrate, and a channel region is arranged between the source region and the drain region; the grid electrode is arranged on the channel region; gate oxide layers are arranged at the connection position of the grid electrode and the channel region and the connection position of the grid electrode and the source electrode; the surface of the gate and the surface of the source are at the same height, and the surface of the gate is higher than the surface of the drain and forms a step structure. By means of the technical scheme, the hot carrier effect and the short channel effect can be improved, and the electrical performance of the semiconductor device is improved.

The present invention discloses an equivalent source and drain region optimized field-effect transistor device for solving the problem of short-channel effects of a field-effect transistor in the prior art. The field-effect transistor device includes an active layer, and the active layer includes a source region, a drain region and a channel region located between the source region and the drain region; when the device is on, an effective channel and an equivalent source region and an equivalent drain region away from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field-effect transistor device communicates the source region and the drain region via the effective channel and the equivalent source region and the equivalent drain region to contribute a working current, wherein the length of the equivalent source region is greater than that of the equivalent drain region.

The application provides an image sensor pixel structure, comprising a plurality of arrayed pixel units, each pixel unit comprising: a semiconductor substrate having opposite first and second surfaces; a photoelectric conversion region extending into the semiconductor substrate from the first surface to form a photoelectric conversion element; a floating diffusion region extending into the semiconductor substrate from the first surface; and a transfer transistor coupled between the photoelectric conversion region and the floating diffusion region, the transfer transistor comprising a transfer gate, wherein the extension path of the transfer gate passes through the center point of the first surface, and the extension direction of the transfer gate forms an angle Q with the first diagonal direction of the first surface, 0°≤Q<5°. The application also provides an image sensor. In the application, the pixel array is rotated by a certain angle, the transfer gate is arranged in the diagonal direction of the pixel unit surface, the area of the transfer gate is increased in the lateral length, and the problems of short channel effect and narrow channel effect caused by the too small size of the transfer gate are solved.

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate containing silicon, and forming a grid electrode and a grid electrode side wall on the surface of the substrate; a protective layer is formed, the protective layer is made of the same material as the grid electrode side wall, the protective layer covers the surface of the substrate, the top of the grid electrode and the grid electrode side wall, and the protective layer and the substrate have different etching selection ratios; the sum of the thickness of the protective layer and the thickness of the gate side wall is equal to the target thickness; and after the doping process and the annealing process are executed, removing the protective layer located at the top of the grid electrode and on the surface of the substrate, and reserving the protective layer covering the side wall of the grid electrode. According to the semiconductor structure, oxidation of the silicon surface of the substrate and material loss caused by the photoresist removing and cleaning steps in the doping process are solved, the short-channel effect is restrained, the substrate is prevented from being damaged in the process of removing the protection layer, and the electrical stability of the semiconductor structure is improved through collaborative design of the protection layer and the grid side wall.

The invention provides a semiconductor device and a preparation method thereof, a substrate is internally provided with a plurality of source and drain trenches which are distributed at intervals, and the source and drain trenches extend into the substrate from the surface of the substrate; forming a first embedded epitaxial layer in the source-drain groove, wherein the source-drain groove is filled with the first embedded epitaxial layer; forming a second embedded epitaxial layer on the first embedded epitaxial layer, wherein the second embedded epitaxial layer covers the top surface of the first embedded epitaxial layer and the exposed part of the top surface of the substrate; and forming a cap layer on the second embedded epitaxial layer. According to the invention, the substrate and the cap layer are separated by using the second embedded epitaxial layer, and the cap layer cannot be in contact with the substrate, so that doped ions in the cap layer are prevented from being diffused into a channel in the substrate, and the short-channel effect is further improved; the first embedded epitaxial layer and the second embedded epitaxial layer can provide pressure stress for the channel together without causing adverse effects on the device, and the process for preparing the second embedded epitaxial layer is relatively simple and low in cost.

The invention discloses a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductor devices.According to the semiconductor device structure, through the synergistic effect of a full-surrounding gate structure, a junction-free structure and a core-shell conducting channel, the uniform medium-high doping condition of the junction-free structure is guaranteed, and meanwhile the conductivity of the semiconductor device structure is improved. A combined conductive mechanism of a body conductive path of a core part and a high-mobility conductive path of a shell part in a conductive channel is realized, so that the device obtains higher driving current and lower on resistance in an on state, and keeps good grid control capability and excellent short channel suppression performance in an off state; and pn junctions between the source / drain regions and the channels do not need to be formed in the process, so that the problems of instable doping, short channel effect, insufficient carrier mobility, complex process and the like in a traditional device are effectively solved, the electrostatic control capability and the performance consistency of the device are remarkably improved, and the device has the advantages of high performance, high reliability and low cost.

The application provides a transistor and a manufacturing method thereof, wherein an oxide semiconductor layer such as indium tin oxide (ITO) and a gate dielectric layer are sequentially and fully surrounded on the sidewall of at least part of the height of an oxide insulating core, and the gate is surrounded on the sidewall of part of the height of the gate dielectric layer, so that the oxide semiconductor layer in the gate-surrounded area is used as a conductive channel of a MOS transistor, and the oxide semiconductor layers on the lower side and the upper side of the gate are used as a source region and a drain region of the MOS transistor respectively, thereby on one hand, the gate is fully surrounded on the conductive channel, and the regulation of the transistor by the gate can be enhanced, and on the other hand, the MOS transistor with a vertical channel structure is formed, the channel length-width ratio of the transistor can be controlled by controlling the height of the gate and the circumference of the oxide insulating core, so that the further miniaturization of the transistor size can be facilitated, the short channel effect can be improved, and the performance of the miniaturized transistor can be ensured.

The invention relates to the technical field of semiconductor devices, and provides a side gate ferroelectric reconfigurable field effect transistor, which is characterized in that ferroelectric dielectric layers are arranged in side surface areas of insulating layers, an upper gate and a lower gate, and the ferroelectric dielectric layers completely cover the first insulating layer, the second insulating layer, the third insulating layer and the side surface areas; a Z-shaped vertical channel layer is arranged on the side face of the ferroelectric dielectric layer, by means of the Z-shaped vertical channel structure, the area efficiency of an integrated circuit is improved, meanwhile, the short channel effect is effectively restrained by prolonging the channel length, miniaturization and high performance are both considered, the upper split grid electrode and the lower split grid electrode can independently regulate and control the orientation of the upper ferroelectric domain and the lower ferroelectric domain, and when the polarization states of the upper split grid electrode and the lower split grid electrode are opposite, the ferroelectric domain effect is effectively restrained. And a controllable PN or NP junction is formed in the channel, so that a diversified reconfigurable function is realized.

The present application provides an integrated circuit with a transistor, which has an oxide semiconductor layer such as indium tin oxide (ITO) and a gate dielectric layer successively fully surrounding the sidewall of at least part of the height of the oxide insulating core, and the gate electrode surrounds part of the gate dielectric layer, so that the oxide semiconductor layer in the gate electrode surrounding area serves as the conductive channel of the MOS transistor, and the oxide semiconductor layer on both sides of the gate electrode serves as the source region and the drain region of the MOS transistor, thereby facilitating the further miniaturization of the transistor size, improving the short channel effect, ensuring the performance of the miniaturized transistor, and further facilitating the miniaturization and performance improvement of the integrated circuit with the transistor.

Embodiments of the present application provide a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device. The present application relates to the technical field of semiconductor. The semiconductor structure comprises a semiconductor layer, a gate insulating layer and a gate. The semiconductor layer comprises a source region, a first channel region and a drain region, the first channel region is arranged between the source region and the drain region, the gate is located at least one side of the first channel region, and the gate insulating layer is located between the first channel region and the gate; along the extension direction of the first channel region, one end of the gate insulating layer forms isolation between the gate and at least part of the source region, and / or the other end of the gate insulating layer forms isolation between the gate and at least part of the drain region. Embodiments of the present application increase the length of the effective channel region, can inhibit the short channel effect, and reduce the on-state current.

Epitaxial source / drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source / drain structures, are disclosed herein. An exemplary source / drain structure extends from a topmost channel layer to a depth into a semiconductor substrate. The source / drain structure includes an undoped epitaxial layer with a trough-shaped top surface, a first doped epitaxial layer over the undoped epitaxial layer, a second doped epitaxial layer over the first epitaxial layer, and a third doped epitaxial layer over the second doped epitaxial layer. A thickness of the undoped epitaxial layer is less than the depth of the epitaxial source / drain structure into the semiconductor substrate. The thickness and the depth are tuned based on a size of an active region to which the epitaxial source / drain structure belongs, such that the epitaxial source / drain structure mitigates short channel effects while optimizing performance.

The invention provides a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductors, the semiconductor device structure comprises a substrate, a bottom doped region, a drift region, a first doped region and a second doped region, and the drift region is adjacent to the upper part of the bottom doped region; the first doped region is located at one side of the bottom doped region and the drift region and is in contact with the drift region and the bottom doped region, and a first gate connection region is formed at the top of the first doped region; the second doped region is located in the drift region and is spaced from the bottom doped region in the direction perpendicular to the substrate, and a second gate connection region is formed at the top of the second doped region. Compared with the prior art, the embedded conducting channel can be formed, flicker noise can be greatly reduced, meanwhile, device parameters are more stable, and long-term reliability is better. Moreover, the second doped region and the bottom doped region can form a buried shielding layer together, so that the electric field distribution can be optimized, the short-channel effects such as DIBL can be effectively inhibited, and more ideal switching characteristics can be obtained.

The invention discloses a method for forming a small-size semiconductor device structure, which is characterized in that the small-size semiconductor structure simultaneously comprises a device needing to adjust the morphology of an LDD injection region and a device which does not need to adjust the morphology of the LDD injection region, and after a grid electrode is formed on a semiconductor substrate or an epitaxial layer, the LDD injection region is formed; dielectric layer deposition and etching are carried out on the two sides of the grid electrode to form a primary side wall; after the primary side wall is formed, ion implantation of an LDD injection region is directly carried out on a device of which the morphology of the LDD injection region does not need to be adjusted; for a device of which the morphology of the LDD injection region needs to be adjusted, performing a side wall widening process once, additionally growing a dielectric layer once, etching and widening a side wall once, and then performing ion injection of the LDD injection region; after injection of the LDD injection region is completed completely, a dielectric layer continues to grow and is etched to form a secondary side wall, and then ion injection of a source-drain region is carried out to form the source-drain region; and the deposition thickness of the secondary side wall needs to be reduced, namely the thickness of the secondary side wall is reduced. According to the forming method, the short-channel effect is inhibited under the condition that the size of the device is not changed.

A semiconductor device includes a silicon carbide epitaxial substrate, a plurality of well regions, a junction field effect region, a plurality of sources, a plurality of lightly doped regions, a plurality of heavily doped regions, a gate, and a drain electrode. Particularly, the lightly doped regions are arranged corresponding to the source electrodes, and each lightly doped region is provided with a first lightly doped layer and a second lightly doped layer, the first lightly doped layer faces downwards from the top surface of the silicon carbide epitaxial substrate and is positioned on the side edge of the corresponding source electrode, and the second lightly doped layer is positioned below the first lightly doped layer and is positioned below the second lightly doped layer. And the second lightly doped layer extends from the lower half part of the side edge of the source electrode to the bottom of the source electrode, the width of the second lightly doped layer corresponding to the side edge of the source electrode is greater than that of the first lightly doped layer, and the junction field effect region is formed downwards from the surface of the silicon carbide epitaxial substrate, is positioned between the adjacent well regions and is not in contact with the well regions. By means of the structural design of the semiconductor assembly, the short channel effect can be restrained, and the hot carrier problem can be reduced.

The invention provides a junction-free transistor with a planar core-shell structure, which comprises a substrate, a core layer, a shell layer, a source-drain region, a grid electrode and a first side wall, the substrate, the core layer, the shell layer and the source-drain region are sequentially stacked along the stacking direction, the grid electrode and the first side wall are arranged on the same layer, the first side wall is arranged between the grid electrode and the source-drain region, and the first dielectric constant of the first side wall is greater than 7.5. In the stacking direction, the projection area of the shell layer in the plane where the substrate is located at least covers the projection areas of the grid electrode and the side wall in the plane where the substrate is located. By arranging the first side wall with a relatively high dielectric constant, the trend that the threshold voltage drops along with the shortening of the channel length can be slowed down, the roll-off of the threshold voltage can be inhibited, and the first side wall with the relatively high dielectric constant can also enhance the control capability of the grid electrode on the channel, improve the switching characteristic and inhibit the subthreshold swing degradation. And the modulation of the leakage voltage on the threshold voltage can be effectively suppressed, the leakage induced barrier lowering effect is weakened, and the suppression effect on the short channel effect is realized.

The application provides a semiconductor device and an electronic device; the semiconductor device is characterized in that: by making the effective length of the part of the middle region corresponding to the channel part of the gate smaller than the effective length of the part of the edge region corresponding to the channel part of the gate in the second direction, the channel length of the middle region corresponding to the channel part of the semiconductor device is smaller than the channel length of the edge region corresponding to the channel part of the semiconductor device; thus, under the short channel effect, the middle region of the semiconductor device is opened prior to the edge region of the semiconductor device, thereby eliminating the hump current, reducing the sub-threshold swing of the semiconductor device, improving the performance of the semiconductor device, and improving the display uniformity.