770 results about "Scale down" patented technology

The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or detection of particles, such as cells and/or beads. The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or analysis of particles, such as cells, viruses, organelles, beads, and/or vesicles. The invention also provides microfluidic mechanisms for carrying out these manipulations and analyses. These mechanisms may enable controlled input, movement/positioning, retention/localization, treatment, measurement, release, and/or output of particles. Furthermore, these mechanisms may be combined in any suitable order and/or employed for any suitable number of times within a system. Accordingly, these combinations may allow particles to be sorted, cultured, mixed, treated, and/or assayed, among others, as single particles, mixed groups of particles, arrays of particles, heterogeneous particle sets, and/or homogeneous particle sets, among others, in series and/or in parallel. In addition, these combinations may enable microfluidic systems to be reused. Furthermore, these combinations may allow the response of particles to treatment to be measured on a shorter time scale than was previously possible. Therefore, systems of the invention may allow a broad range of cell and particle assays, such as drug screens, cell characterizations, research studies, and/or clinical analyses, among others, to be scaled down to microfluidic size. Such scaled-down assays may use less sample and reagent, may be less labor intensive, and/or may be more informative than comparable macrofluidic assays.

The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or detection of particles, such as cells and/or beads. The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or analysis of particles, such as cells, viruses, organelles, beads, and/or vesicles. The invention also provides microfluidic mechanisms for carrying out these manipulations and analyses. These mechanisms may enable controlled input, movement/positioning, retention/localization, treatment, measurement, release, and/or output of particles. Furthermore, these mechanisms may be combined in any suitable order and/or employed for any suitable number of times within a system. Accordingly, these combinations may allow particles to be sorted, cultured, mixed, treated, and/or assayed, among others, as single particles, mixed groups of particles, arrays of particles, heterogeneous particle sets, and/or homogeneous particle sets, among others, in series and/or in parallel. In addition, these combinations may enable microfluidic systems to be reused. Furthermore, these combinations may allow the response of particles to treatment to be measured on a shorter time scale than was previously possible. Therefore, systems of the invention may allow a broad range of cell and particle assays, such as drug screens, cell characterizations, research studies, and/or clinical analyses, among others, to be scaled down to microfluidic size. Such scaled-down assays may use less sample and reagent, may be less labor intensive, and/or may be more informative than comparable macrofluidic assays.

Methods, apparatuses and systems directed to improving the efficiency of bandwidth allocation schemes by adapting to slow-start mechanisms associated with network communications protocols, such as the TCP/IP protocol suite. In one implementation, the present invention scales down the initial target rate assigned to a data flow to a fraction of an initial estimate of the effective rate capacity of the communications path between two hosts. As packets are received, the target rate is gradually increased, eventually up to the detected rate capacity of the communications path. Implementations of the present invention improve the efficiency of bandwidth allocation by reducing the over-allocation of bandwidth to data flows during the slow-start phase, leaving more bandwidth available to other data flows.

A vascular implant formed of a compressible foam material has a compressed configuration from which it is expansible into a configuration substantially conforming to the shape and size of a vascular site to be embolized. Preferably, the implant is formed of a hydrophilic, macroporous foam material, having an initial configuration of a scaled-down model of the vascular site, from which it is compressible into the compressed configuration. The implant is made by scanning the vascular site to create a digitized scan data set; using the scan data set to create a three-dimensional digitized virtual model of the vascular site; using the virtual model to create a scaled-down physical mold of the vascular site; and using the mold to create a vascular implant in the form of a scaled-down model of the vascular site. To embolize a vascular site, the implant is compressed and passed through a microcatheter, the distal end of which has been passed into a vascular site. Upon entering the vascular site, the implant expands in situ substantially to fill the vascular site. A retention element is contained within the microcatheter and has a distal end detachably connected to the implant. A flexible, tubular deployment element is used to pass the implant and the retention element through the microcatheter, and then to separate the implant from the retention element when the implant has been passed out of the microcatheter and into the vascular site.

A method and apparatus are provided for enabling a UE to perform accurate and efficient cell reselection in a cellular mobile communications system. If reselection to the same cell is repeated, the UE releases itself from a high-speed UE state or excludes the number of reselections to the same cell from the number of cell changes counted for a duration set for deciding as to the high-speed UE state, according to a ping-pong duration threshold and a ping-pong occurrence number threshold. The UE uses a non-scaled down cell reselection time limit in a non-high-speed UE state, and a scaled-down cell reselection time limit in the high-speed UE state. Thus, the UE reselects to a non-serving cell having the highest ranking continuously for the cell reselection time limit.

First stage turbine buckets have airfoil profiles substantially in accordance with Cartesian coordinate values of X, Y and Z set forth Table I wherein X and Y values are in inches and the Z values are non-dimensional values from 0 to 1 convertible to Z distances in inches by multiplying the Z values by the height of the airfoil in inches. The X and Y values are distances which, when connected by smooth continuing arcs, define airfoil profile sections at each distance Z. The profile sections at each distance Z are joined smoothly to one another to form a complete airfoil shape. The X, Y and Z distances may be scalable as a function of the same constant or number to provide a scaled up or scaled down airfoil section for the bucket. The nominal airfoil given by the X, Y and Z distances lies within an envelop of ±0.055 inches in directions normal to the surface of the airfoil.

A mode of managing windows in a graphical user interface in which the application windows may be presented in a tiled manner is provided. Upon invocation of the mode inactive application windows may be scaled down and organized in a manner so as to set them aside from the currently active application window while the active application window may remain at or near full size and be positioned in a centralized location in the desktop space.

The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element. A flash memory element comprises: a first oxide film formed on a surface of a silicon substrate; a fin active area vertically formed on the first oxide film; a gate tunneling oxide film formed on the fin active area; a floating electrode formed on the surfaces of the gate tunneling oxide film and the first oxide film; a inter-gates oxide film formed on the surface of the floating electrode; and a control electrode formed on the surface of the inter-gates oxide film. With the above double-gate flash memory structure, a flash memory element in the present invention improves the scaling down characteristic and the programming and retention characteristic of a flash memory element.

The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

The present application discloses a semiconductor device formed on a SOI substrate which comprises a buried insulating layer and a semiconductor layer on the buried insulating layer and a method for manufacturing the same, wherein a fin of semiconductive material having two opposing sides perpendicular to a main surface of the SOI substrate is provided in the semiconductor layer, said semiconductor device comprising: a source region and a drain region provided at two ends of the fin respectively; a channel region provided at a central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, wherein the gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the SOI substrate. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

A mode of managing windows in a graphical user interface in which the application windows may be presented in a tiled manner is provided. Upon invocation of the mode each inactive application windows may be scaled down and organized in a manner so as to set them aside from the currently active application window while the active application window may remain at or near full size and be positioned in a centralized location in the desktop space.

A system and method of transmitting an image adapted to a first display area size, such as a standard computer screen having a particular pixel-by-pixel resolution, to an apparatus having a smaller second display area size by scaling the image through coefficient cropping its frequency domain representation. When the cropped frequency coefficients are used to display an image within the second smaller display area, a scaled version of the image is displayed. In a specific embodiment, frequency domain coefficients are cropped such that a region of interest of the image is scaled down less than the remainder of the image when displayed in the second smaller display area. Scaling in this manner provides the user with a readable region of interest with the remainder of the image scaled down so as to facilitate easy image navigation by the user.

This invention is about engineering approach to development of transactional workflow applications and about ability of this way produced applications to concurrently process large number of workflow requests of identical type with high speed. It provides methods and articles of manufacture: for graphical development of fully executable workflow application; for producing configuration of class objects and threads with capacity for concurrent processing of multitude of requests of identical type for transactional workflow and for concurrent execution and synchronization of parallel workflow-activity sequences within processing of a workflow request; for application self-scaling up and self-scaling down of its processing capacity; and for real-time visualization of application's thread structures, thread quantity, thread usage, and scaling-enacted changes in threads structure and quantity.

A remote optical measurement suitable for Raman and fluorescence detection uses one or more dielectric components and an optical configuration which affords significant miniaturization, in some cases resulting in a probe with dimensions on the order of one-half inch or less on a side. A primary application is the pharmaceutical market, wherein the reactors vessels are only 1-inch in diameter, causing a scale down of instrumentation due to space requirements.

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.

A system and method of intelligent navigation with collision avoidance for a vehicle is provided. The system includes a global positioning system and a vehicle navigation means in communication with the global positioning system. The system also includes a centrally located processor in communication with the navigation means, and an information database associated with the controller, for identifying a location of a first vehicle and a second vehicle. The system further includes an alert means for transmitting an alert message to the vehicle operator regarding a collision with a second vehicle. The method includes the steps of determining a geographic location of a first vehicle and a second vehicle within an environment using the global positioning system on the first vehicle and the global positioning system on the second vehicle, and modeling a collision avoidance domain of the environment of the first vehicle as a discrete state space Markov Decision Process. The methodology scales down the model of the collision avoidance domain, and determines an optimal value function and control policy that solves the scaled down collision avoidance domain. The methodology extracts a basis function from the optimal value function, scales up the extracted basis function to represent the unscaled domain, and determines an approximate solution to the control policy by solving the rescaled domain using the scaled up basis function. The methodology further uses the solution to determine if the second vehicle may collide with the first vehicle and transmits a message to the user notification device.

A process of forming a transistor with three vertical gate electrodes including a high-k gate dielectric and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes can be formed of different materials so that the workfunctions of the three electrodes can be tailored. The three electrodes are positioned over a single channel and operate as a single gate having outer and inner gate regions.