588 results about "Charge retention" patented technology

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.

Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.

A solid state imaging device includes: multiple unit pixels including a photoelectric converter generating electrical charge in accordance with incident light quantity and accumulating the charge, a first transfer gate transferring the accumulated charge, a charge holding region holding the transferred charge, a second transfer gate transferring the held charge, and a floating diffusion region converting the transferred charge into voltage; an intermediate charge transfer unit transferring, to the charge holding region, a charge exceeding a predetermined charge amount as a first signal charge; and a pixel driving unit setting the first transfer gate to a non-conducting state, set the second transfer gate to a conducting state, transfer the first signal charge to the floating diffusion region, set the second transfer gate to a non-conducting state, set the first transfer gate to a conducting state, and transfer the accumulated charge to the charge holding region as a second signal charge.

Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

An imager has one or more pixel circuits arranged to receive negatively biased control signals at one or more gates associated with charge holding regions to reduce dark current generation and flow.

An object is to provide a nonvolatile semiconductor memory device which is excellent in a writing property and a charge retention property. In addition, another object is to provide a nonvolatile semiconductor memory device capable of reducing writing voltage. A nonvolatile semiconductor memory device includes a semiconductor layer or a semiconductor substrate including a channel formation region between a pair of impurity regions that are formed apart from each other, and a first insulating layer, a plurality of layers formed of different nitride compounds, a second insulating layer, and a control gate that are formed in a position which is over the semiconductor layer or the semiconductor substrate and overlaps with the channel formation region.

Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced by utilization of nano-crystals and/or bulk trapping materials in a composite non-conductive trapping layer and a high K dielectric insulating layers. The band-gap engineered gate-stack with asymmetric direct tunneling or crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage high speed tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. Memory cell embodiments of the present invention allow multiple levels of bit storage in a memory cell through multiple charge centroids and/or multiple threshold voltage levels.

The present invention provides methods and structures for improving refresh power efficiency of dynamic random access memory devices. By measuring charge retention properties of reference cells that have substantially the same structures as normal DRAM memory cells, the refresh rate of DRAM devices can be adjusted with better reliability. The reliability is further improved by using ECC circuits and/or field programmable redundancy circuits.

A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining transistors for controlling the application of the necessary read, program, and erase signals. Erase count registers, each of the erase count registers associated with one block of the array of the charge retaining transistors for storing an erase count for the associated block for determining whether a refresh operation is to be executed. Groupings on each column of the array of charge retaining transistors are connected as NAND series strings where each NAND string has a select gating charge retaining transistor connected to the top charge retaining transistor for connecting the NAND series string to the bit lines.

Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.

An ultrasonic transducer cell according to the present invention includes: a substrate; a charge holding portion provided on the substrate; a lower electrode provided on the charge holding portion and used to input and output a signal; and a vibration membrane provided above the lower electrode to be separated from the lower electrode with a cavity, and configured to include at least an insulating film and an upper electrode provided on the insulating film.

Provided is a solid-state imaging device including: a first-conductivity-type substrate; a second-conductivity-type well formed in a surface side of the first-conductivity-type substrate; a photoelectric conversion area configured with a first-conductivity-type-impurity area formed in the second-conductivity-type well to convert incident light to charges; a first-conductivity-type-charge retaining area configured with the first-conductivity-type-impurity area formed in the second-conductivity-type well to retain the charges converted by the photoelectric conversion area until the charges are read out; a charge voltage conversion area configured with the first-conductivity-type-impurity area formed in the second-conductivity-type well to convert the charges retained in the charge retaining area to a voltage; and a first-conductivity-type-layer area configured by forming a first-conductivity-type-in a convex shape from a boundary between the first-conductivity-type substrate and the second-conductivity-type well to a predetermined depth of the surface side under at least one portion of the charge retaining area and the charge voltage conversion area.

A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.