70 results about "Gate insulator" patented technology

Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

Electronic devices employing thin-gate insulator transistors coupled to varactors to reduce gate-to-source / drain voltage to avoid voltage breakdown, and related fabrication methods. The electronic device includes thin-gate insulator transistors coupled in series to provide a single output node, and with their gates controlled by a single, input node to provide an effective three (3) terminal, single transistor device. The electronic device includes varactors each coupled in series between a respective gate of a thin-gate insulator transistor and the input node to support a single input signal for the electronic device. Each series coupled varactor and thin-gate insulator transistor are coupled to the input node in parallel to each other. Each varactor creates a voltage division between the input signal voltage and its series connected gate of a respective thin-gate insulator transistor to prevent the respective gate-to-source / drain voltage of the thin-gate insulator transistor from exceeding its breakdown voltage.

The invention relates to a MOSFET transistor. The present specification relates to a transistor including a channel region extending in a first direction between a drain region and a source region of a semiconductor layer; the gate structure is located on the top of the channel forming region, and the gate structure comprises a gate insulator with the top covered with a gate region; a channel formation region including a first epitaxial channel region having a first length in the first direction and a second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and the gate insulator includes a first portion having a first thickness on the second channel region on either side of the first channel region, and a second portion having a second thickness over the first channel region, the second thickness being less than the first thickness.

Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.

A capacitor-less stacked DRAM cell based on a vertical transistor includes a first vertical transistor and a second vertical transistor, and each of the first vertical transistor and the second vertical transistor includes a spacer, a source disposed on an upper surface of the spacer, a drain disposed adjacent to a lower portion of a side surface of the spacer, a channel disposed along an upper surface of the drain, an upper portion of the side surface of the spacer, and an upper surface of the source, a gate insulator disposed along a side surface and an upper surface of the channel, and a gate electrode disposed along a side surface and an upper surface of the gate insulator.

Disclosed herein are high electron mobility transistors (HEMTs) with hysteretic gates, and related IC structures, devices, and techniques. In one aspect, a HEMT may include a channel structure comprising a heterojunction of a first semiconductor material and a second semiconductor material, a gate electrode material, and a gate insulator material, wherein the gate insulator material is between the channel structure and the gate electrode material and includes a hysteretic element.

A metal-oxide-semiconductor (MOS) transistor includes a substrate including a well region, an insulator layer coupled to the substrate, and a source including a source region, a source contact passing through the insulator layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor also includes a gate region including a gate insulator layer and a gate contact and a drain including a drain region and a drain contact passing through the insulator layer to the drain region. The MOS transistor can be an LDMOS transistor, for example, an LNDMOS or LPDMOS transistor.

A silicon carbide semiconductor device includes a drift layer, a first doped region, a second doped region, a gate trench, a third doped region and a gate electrode. The drift layer is disposed on a SiC substrate. The first doped region is disposed on the drift layer. The second doped region is disposed on the first doped region. The gate trench is extended from an upper surface of the second doped region through the first doped region and into the drift layer. The gate trench is formed in a manner dividing the drift layer into a plurality of mesas encircled by the gate trench, each of the mesas comprises a center portion and a plurality of leg portions extended from the center portion. The third doped region is arranged in the center portion of the mesa, and is disposed in the first doped region and adjacent to the second doped region. The gate electrode is arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator.

A method for making a trench field effect transistor (TFET) may include forming a trench in a semiconductor layer, and forming a superlattice layer in the semiconductor layer extending along bottom and sidewall portions of the trench, the superlattice layer comprising a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions defining, along with the superlattice layer, a channel region extending between the source and drain regions, and forming a gate within the trench comprising a gate insulator lining the trench and a gate electrode within the gate insulator.

Embodiments of the invention provide a method comprising generating a first electric field strength at a first point at a first interface between a gate insulator and a semiconductor layer of a thin film transistor having an amorphous metal gate; generating a second electric field strength at a second point at the first interface; and minimizing the difference between the first electric field strength and the second electric field strength by: forming a first surface roughness value at a first surface of the amorphous metal gate; and forming a second surface roughness value at a second surface of the gate insulator, the first and second surface roughness values being less than 10% different from each other.

One aspect of the present disclosure pertains to a method. The method forms a stack of semiconductor channels over a semiconductor fin. Each of the semiconductor channels are squared-shaped with rounded corners, and the rounded corners interface between vertical and horizontal surfaces of the semiconductor channels. The method forms a nonconformal interfacial layer over and wrapping around each semiconductor channel of the stack of semiconductor channels. The interfacial layer has a thicker portion at corner portions of the semiconductor channels and a thinner portion at non-corner portions of the semiconductor channels. The method forms a nonconformal high-k dielectric layer over and wrapping around the nonconformal interfacial layer. The high-k dielectric layer has a thicker portion on the thicker portion of the interfacial layer and a thinner portion on the thinner portion of the of the interfacial layer. The method forms a gate electrode over the high-k dielectric layer.

A display device includes a substrate having a transistor disposed thereon. A gate insulator is disposed on the transistor. A plurality of conductive layers is disposed on the gate insulator. The plurality of conductive layers is spaced apart from one another. An interlayer dielectric layer is disposed on the plurality of conductive layers. The interlayer dielectric layer comprises an inorganic material. A planarization layer is disposed on the interlayer dielectric layer and defines an opening. The opening exposes the interlayer dielectric layer. The planarization layer comprises an inorganic material. 1

An active matrix substrate includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate, in which each of oxide semiconductor TFT includes an oxide semiconductor layer including a first region and a second region having a specific resistance lower than a specific resistance of the first region, and a gate electrode disposed on at least a part of the first region with a gate insulating layer interposed therebetween, the gate insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and, when viewed from a normal direction of the substrate, the first insulating layer overlaps with the first region and does not overlap with the second region and the second insulating layer overlaps with the first region and at least a part of the second region.

Memory circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers, the stack comprising laterally-spaced memory blocks comprising sub-blocks in an upper portion thereof. A conductive-material tier is in the upper portions and conductive material thereof extends downwardly therefrom. Select gates of select-gate transistors are in individual of the sub-blocks operatively alongside channel material of the select-gate transistors. A gate insulator layer is laterally-between the select gates and the channel material of the select-gate transistors. The gate insulator layer extends laterally to be vertically-between the channel material and the select gates directly under the select gates. Other embodiments, including method, are disclosed.

The present disclosure relates to a ferroelectric transistor, memory circuitry including a ferroelectric transistor, and a method for forming memory circuitry including memory cells individually including horizontal ferroelectric transistors. The ferroelectric transistor comprises two source electrode / drain electrode regions, and a channel region is horizontally arranged between the two source electrode / drain electrode regions. The channel region has opposite front and back sides along a horizontal current flow direction through the channel region. A front gate is on the front side of the channel region. A front gate insulator is horizontally between the front gate and the front side of the channel region. The front gate insulator includes a dielectric material and a ferroelectric material each directly abutting the front gate. The ferroelectric material directly against the front gate is more than the dielectric material. Other embodiments including the methods are disclosed.

To provide a semiconductor device having stable electrical characteristics. Or, to provide a semiconductor device having normally-off electrical characteristics. To provide a semiconductor device having normally-off electrical characteristics. 【Solution means】A semiconductor device having a gate electrode, a gate insulator, and an oxide semiconductor, where the oxide semiconductor has fluorine in the channel formation region, and the fluorine concentration in the channel formation region is 1×1 0 0 20 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less. Also, the addition of fluorine is performed by ion implantation. There is such a semiconductor device. Also, the addition of fluorine is performed by ion implantation.

Embodiments relate to devices, circuits, and systems including s-bit generators constructed from memtransistors. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. The s-bit generator can be used to construct s-bit generator circuits that exploit the different sources of inherent stochasticity in 2D memtransistors (e.g., cycle-to-cycle fluctuations in the carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor, random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor, etc.) and combine it with an inverting amplifier and a programmable thresholding inverter to obtain s-bits. Additional embodiments relate to integration of s-bit generators with 2D memtransistor based logic gates such as AND, MUX, XOR, and OR gates to perform arithmetic operations such as addition, subtraction, multiplication, and / or sorting.

An exemplary semiconductor structure includes first, second and third field effect transistor (PET) stack on a substrate. Each of the first, second and third FET stacks includes a top and a bottom transistor. Each transistor has a channel region, a gate insulator and a gate work function layer. Each of the gate work function layers in the top transistors of the first, second and third FETs having a different composition.

Field-Effect Transistor. This description relates to a transistor (10) comprising, on a semiconductor layer (11), a stack of a gate insulator (13) and a conductive gate (17) arranged on and in contact with the gate insulator, wherein: - the conductive gate has a lower portion (171) and an upper portion (173), the lower portion of the conductive gate having a length shorter than the length of the upper portion of the conductive gate; and - two cavities (27) filled with a gas or a vacuum are disposed between the upper portion of the conductive gate and the gate insulator, on either side of the lower portion of the conductive gate, the transistor further comprising spacers (29) covering the flanks of the upper portion of the conductive gate, said spacers being separated from the flanks of the lower portion of the conductive gate by the cavities. Figure for the abbreviation: Fig. 1

A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150° C. to about 275° C.

A display device includes a semiconductor layer on an opposite side to a light-blocking layer, the semiconductor layer including an active layer overlapping the light-blocking layer, a first gate insulator on an opposite side to a buffer film with the active layer therebetween, and a first gate electrode on an opposite side to the active layer with the first gate insulator therebetween, a side surface of the first gate insulator includes a first inclined portion contacting a first surface of the semiconductor layer, and a second inclined portion contacting the first inclined portion and the first gate electrode, and a first angle between the first surface of the semiconductor layer and the first inclined portion is less than a second angle between the first surface of the semiconductor layer and the second inclined portion.

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes a transistor. The transistor comprises a vertical channel, a first source / drain electrode, a second source / drain electrode, a first grid electrode and a second grid electrode, a first sacrificial layer removal area is arranged between the first source / drain electrode and the second source / drain electrode in the vertical direction, the vertical channel is located in the first sacrificial layer removal area and provided with a first end and a second end which are oppositely arranged in the vertical direction, the first source / drain electrode is located at the first end and electrically connected with the first end, and the second source / drain electrode is located at the second end and electrically connected with the second end. The second source / drain electrode is positioned at the second end and is electrically connected with the second end; the first gate insulator is over the first source / drain and covers a first sidewall of the vertical channel in an insulating manner. The second gate insulator is over the first source / drain and covers a second sidewall of the vertical channel in an insulating manner. The performance and uniformity of the memory can be improved, so that the performance of the memory is further improved.

Apparatuses including a semiconductor transistor and methods for forming same are described. An example apparatus includes an active region in a semiconductor substrate, an isolation region configured to isolate the active region, and a gate structure on the active region. The isolation region includes a dielectric material with an addition of a metal material in the dielectric material. The gate structure has portions overlapping the isolation region. The gate structure includes a gate, and further includes a gate insulator that includes a film of the metal material and is disposed between the active region and the gate.

A display device includes a semiconductor layer on an opposite side to a light-blocking layer, the semiconductor layer including an active layer overlapping the light-blocking layer, a first gate insulator on an opposite side to a buffer film with the active layer therebetween, and a first gate electrode on an opposite side to the active layer with the first gate insulator therebetween, a side surface of the first gate insulator includes a first inclined portion contacting a first surface of the semiconductor layer, and a second inclined portion contacting the first inclined portion and the first gate electrode, and a first angle between the first surface of the semiconductor layer and the first inclined portion is less than a second angle between the first surface of the semiconductor layer and the second inclined portion.

A ferroelectric transistor comprises two source / drain regions having a channel region horizontally there-between. The channel region has opposing front and back sides along a horizontal current-flow direction through the channel region. A front gate is on the front side of the channel region. A front-gate insulator is horizontally between the front gate and the front side of the channel region. The front-gate insulator comprises a dielectric material and a ferroelectric material that are each directly against the front gate. More of the ferroelectric material is directly against the front gate than is the dielectric material. Other embodiments, including methods, are disclosed.

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device includes a transistor and an insulator, the insulator is provided on one of a source and a drain of the transistor, the other of the source and the drain of the transistor is provided on the insulator, and an opening portion reaching the one of the source and the drain is provided in the insulator and the other of the source and the drain. An oxide semiconductor included in the transistor is in contact with a top surface of one of the source and the drain in the opening, a side surface of the insulator, and a side surface of the other of the source and the drain, a gate insulator of the transistor is provided on the oxide semiconductor, and a gate of the transistor is provided on the gate insulator. The oxide semiconductor includes a first region in contact with one of the source and the drain, a second region in contact with the insulator, and a third region in contact with the other of the source and the drain, the first and third regions having a lower resistance than the second region, and the second region having a lower resistance than the first and third regions.

Provided is a display including a substrate including a display area and a non-display area; a first transistor comprising a first semiconductor layer disposed on the display area of the substrate and a first gate electrode disposed on the first semiconductor layer; and a first gate insulator disposed between the first semiconductor layer and the first gate electrode, wherein the first semiconductor layer includes a first layer and a second layer stacked on one another each other in a direction perpendicular to the substrate, and wherein an indium content of the second layer is higher than an indium content of the first layer, and a height of the first layer is lower than a height of the second layer.

Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.

Electronic devices employing thin-gate insulator transistors coupled to varactors to reduce gate-to-source / drain voltage to avoid voltage breakdown, and related fabrication methods. The electronic device includes thin-gate insulator transistors coupled in series to provide a single output node, and with their gates controlled by a single, input node to provide an effective three (3) terminal, single transistor device. The electronic device includes varactors each coupled in series between a respective gate of a thin-gate insulator transistor and the input node to support a single input signal for the electronic device. Each series coupled varactor and thin-gate insulator transistor are coupled to the input node in parallel to each other. Each varactor creates a voltage division between the input signal voltage and its series connected gate of a respective thin-gate insulator transistor to prevent the respective gate-to-source / drain voltage of the thin-gate insulator transistor from exceeding its breakdown voltage.

In at least one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, and the well region (22) comprises a channel region (220) starting directly at the source region (21), and - a gate insulator (4) directly between the semiconductor body (2) and a gate electrode (31), wherein the gate insulator (4) has a non-uniform gate dielectric constant profile along the channel region (220), such that a relative dielectric constant (eox) of the gate insulator (4) is lowest in a first section (61) of the channel region (220) remote from the source region (21).