Recesses in a
semiconductor structure are selectively plated by providing electrical insulating layer over the
semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the
barrier layer; depositing and patterning a
photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the
photoresist remaining in the recesses; and then
electroplating the patterned seed layer with a conductive
metal using the
barrier layer to carry the current during the
electroplating to thereby only plate on the seed layer. In an
alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After
electroplating, the
resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a
semiconductor structure obtained by the above processes.