2641results about "Transistor" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

This invention provides a driving device and its control method. The driving device is used to drive a power switch. The driving device includes a power supply, a first bridge arm coupled to the power supply, a second bridge arm coupled in parallel to the first bridge arm, and a resonant inductor. The first bridge arm includes a first switch and a second switch connected to a first midpoint. The second bridge arm includes a first semiconductor device and a second semiconductor device connected to a second midpoint. The resonant inductor is coupled between the first midpoint and the second midpoint. The control method includes: turning on the first switch for a first time period to charge the gate of the power switch; and, in response to the current of the resonant inductor dropping to a first threshold, turning on the first switch again for a second time period to make the potential of the first midpoint equal to the potential of the second midpoint. Compared with conventional technical solutions, this invention can effectively reduce driving losses and suppress oscillations.

The invention belongs to the technical field of vehicle-mounted power supplies, and particularly relates to a driving circuit of a safety switch of a low-voltage battery, a low-voltage battery power supply system and a vehicle power system, and the driving circuit comprises a driving module, a reference end of which is used for being connected with a source electrode of the safety switch and is grounded; one end of the driving resistor is connected with the output end of the driving module, and the other end is connected with the grid of the safety switch; one end of the limiting capacitor is connected with the other end of the driving resistor, and the other end of the limiting capacitor is connected with the drain electrode of the safety switch or grounded; wherein the capacitance value of the limiting capacitor at least exceeds the capacitance value of a parasitic Miller capacitor of the safety switch with the preset first multiplying power, so that the grid current of the safety switch is limited, and the Miller plateau area of the safety switch is prolonged. The Miller platform area of the safety switch is prolonged, so that the drain current iD of the safety switch can charge the inner side capacitor in an approximate constant current mode, triggering of a reverse over-current fault is prevented, and charging of the inner side capacitor cannot be interrupted.

Manufacturing integrated circuit (IC) devices having adjacent transistors with different channel materials. A transistor includes a stack of nanoribbons coupling source and drain bodies, and a nanoribbon has a thickness at a midpoint of the nanoribbon greater than a thickness away from the midpoint. A second transistor may include a stack of nanoribbons coupling source and drain bodies, and the first transistor nanoribbons may have larger thickness variations than the second transistor nanoribbons. The first transistor nanoribbons may have a first element also in the second transistor nanoribbons and a second element absent in the second transistor nanoribbons. The second element may be added into the first transistor nanoribbons by depositing on the first transistor nanoribbons a layer having the second element, depositing a retaining layer over the second-element layer, and diffusing the second element into the first transistor nanoribbons.

The present disclosure provides a semiconductor structure, a system, and a method of forming a stacked transistor structure with vertically staggered contact vias. The semiconductor structure may include a first stacked transistor cell including a first backside contact having a first contact thickness. The semiconductor structure may also include a second stacked transistor cell including a second backside contact having a second contact thickness different from the first contact thickness. The system may include a semiconductor structure. The method may include forming a first bottom epi and a second bottom epi, filling a first opening in the first stacked transistor cell with one or more metal materials, recessing the one or more metal materials, and filling a second opening in the second stacked transistor cell with the one or more metal materials.

A method of forming a device comprises forming sacrificial pillar structures over conductive structures overlying a barrier structure substantially impermeable to hydrogen. The sacrificial pillar structures are separated from one another by trenches linearly extending in a first lateral direction orthogonal to a second lateral direction in which the conductive structures linearly extend. Gate electrodes are formed within the trenches and laterally adjacent sidewalls of the sacrificial pillar structures. The sacrificial pillar structures are removed to form openings between the gate electrodes. Dielectric liner structures are formed within the openings and laterally adjacent sidewalls of the gate electrodes. Channel structures are formed within the openings after forming the dielectric liner structures. The channel structures comprise a semiconductive material having a band gap larger than that of polycrystalline silicon. Conductive contacts are formed on the channel structures. A device, a memory device, and an electronic system are also described.

A system includes: an inverter configured to convert DC power to AC power, wherein the inverter includes: a power module including: a first substrate, a second substrate including a source plane and a gate plane separated from the source plane by a full trench, the source plane including a step trench, and the gate plane including an electrical connection through the second substrate to a gate input connection of the power module, a semiconductor die disposed between the first substrate and the second substrate, the step trench formed in a portion of the source plane corresponding to an edge of the semiconductor die, and the semiconductor die including a gate connected to the gate plane, and a sinter element disposed between the semiconductor die and the second substrate to connect the semiconductor die to the second substrate; a battery; and a motor.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and / or to cause a voltage across the first gate terminal to be reduced.

A switching circuit includes a power switch, a first driver configured to drive the power switch based on a first input signal, a delay circuit configured to output a delayed input signal, and a second driver configured to drive the power switch based on the delayed input signal. The first driver has a first driving strength and is configured to drive the power switch in a first stage of operation. The delayed input signal is delayed by a delay value relative to a second input signal. The second driver has a second driving strength higher than the first driving strength and is configured to drive the power switch in a second stage of operation, which is subsequent to the first stage of operation.

Embodiments include a semiconductor structure having a first lower transistor and a second lower transistor. Upper transistors are formed above the first and second lower transistors, the first lower transistor having a first work function material, the second lower transistor having a second work function material different from the first work function material. A portion of the second work function material extends below a bottom surface of the first work function material.

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source / drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

A method includes forming a first nanostructure stack and a second nanostructure stack over a substrate, wherein the first nanostructure stack and the second nanostructure stack include alternating layers of a first semiconductor material and a second semiconductor material; performing a first etching process, wherein the first etching process removes the first semiconductor material of the first nanostructure stack to form first openings and recesses the first semiconductor material of the second nanostructure stack to form second openings; depositing a first dielectric material in the first openings and on the second semiconductor material in the second openings; performing a second etching process, wherein the second etching process removes the first dielectric material from the first openings, wherein the first dielectric material remains on the second semiconductor material in the second openings after performing the second etching process; and forming gate structures in the first openings.

The present disclosure discloses an electrical discharge circuit. A voltage-dividing circuit performs voltage division on a voltage input terminal. A detection circuit generates a boosted detection signal. A first inverter is coupled to a first voltage feeding terminal and a second inverter input terminal. A second inverter is coupled to a first inverter output terminal and a ground terminal. A capacitor circuit of a RC circuit is coupled to the first voltage feeding terminal through a resistor to be charged to provide electric charges to the inverter input terminals. A first switch circuit is coupled to one of the inverter input terminals and the ground terminal. The boosted detection signal turns on and off the first and the second switch circuits respectively when an ESD input occurs such that a first and a second discharge transistors controlled by the inverter output terminals turn on to discharge the voltage input terminal.

A semiconductor device includes a gate structure. The gate structure, form bottom to top, includes a gate insulating layer, a first barrier layer and a gate conductive layer. The gate insulating layer is disposed on a substrate. The first barrier layer is disposed on the gate insulating layer. The first barrier layer includes a transition metal nitride, and a concentration of nitrogen atom of a portion of the first barrier layer adjacent to the gate insulating layer is higher than a concentration of nitrogen atom of a portion of the first barrier layer away from the gate insulating layer. The gate conductive layer is disposed on the first barrier layer.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent sources or drained coupled to different nanoribbons or subsets of nanoribbons in the stack. In previous nanoribbon transistors, source / drain regions join the ends of a stack of nanoribbons together, thus electrically shorting the source ends together and the drain ends together. To achieve a stack of semiconductor regions with independent sources or drains, adjacent nanoribbons in the stack may be set at different distances apart, or the source side and drain side may be deposited in separate deposition processes.

An integrated circuit includes a first transistor and a second transistor. A first gate spacer is along a first portion of the common gate structure, the first gate spacer having a first width. A first inner spacer is between the first semiconductor channel layers and having a second width, the first width being greater than the second width. A second gate spacer is along a second portion of the common gate structure and having a third width. A second inner spacer is between the second semiconductor channel layers and having a fourth width, and the third width is greater than the fourth width, and the second width is greater than the fourth width. An isolation structure is in contact with one end of the common gate structure, the isolation structure having a fifth width, and the fifth width is greater than the first width and the third width.

To provide a semiconductor device with elasticity that can reduce an influence of expansion and contraction on a semiconductor element to stabilize characteristics of the semiconductor element.SOLUTION: A semiconductor device comprises: an elastic resin substrate 2 which includes an acrylic adhesive composition with adhesiveness; a plurality of non-elastic resin substrates 3 which are arranged side by side in a plane of the elastic resin substrate 2; and a plurality of semiconductor elements 4 which are arranged on respective planes of the plurality of non-elastic resin substrates 3, wherein the elastic resin substrate 2 has adjacent non-elastic resin substrates of the plurality of non-elastic resin substrates 3 made to freely expand and contract.SELECTED DRAWING: Figure 2

A method of forming an integrated circuit includes forming a sacrificial semiconductor nanostructure and a dielectric interposer adjacent to each other between two stacked channels of a gate all around transistor. The method includes forming an inner spacer in contact with the dielectric interposer. The channels are released by removing the sacrificial semiconductor nanostructure and the dielectric interposer.

The invention discloses a negative voltage driving circuit, a chip, electronic equipment and a vehicle, and belongs to the technical field of circuits. The negative voltage driving circuit comprises a monitoring module, a digital logic control module and a negative voltage generation module, the monitoring module is used for collecting a first working parameter of a transistor and transmitting the first working parameter to the digital logic control module; and the digital logic control module is used for determining a target negative voltage turn-off mode for the transistor according to the first working parameter, and controlling the negative voltage generation module to generate a corresponding negative voltage according to the target negative voltage turn-off mode. According to the technical scheme, the monitoring module collects the working parameters of the transistor in real time, the digital logic control module determines the optimal target negative voltage turn-off mode for the transistor according to the working parameters collected in real time, and then the negative voltage generation module is controlled to rapidly and accurately generate the negative voltage. And the driving requirements of the transistor under different working conditions can be quickly responded.

A semiconductor structure according to the present disclosure includes a backside metal line, a backside dielectric layer over the backside metal line, a first source / drain feature and a second source / drain feature over the backside dielectric layer, a first backside contact extending through the backside dielectric layer to couple to a bottom surface of the first source / drain feature, a second backside contact extending through the backside dielectric layer to couple to a bottom surface of the second source / drain feature, a dielectric layer disposed over the backside dielectric layer, the first source / drain feature and the second source / drain feature, a common contact extending through the dielectric layer to electrically couple to the first source / drain feature and the second source / drain feature, an etch stop layer disposed over and interfacing the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive feature that extends through the etch stop layer.

The invention discloses a high-side driving circuit, an electronic device, a vehicle and a control method. False triggering of a short-circuit protection mechanism is avoided. The high-side driving circuit comprises a power distribution circuit, a sampling circuit and a fault protection circuit, the power distribution circuit comprises a PMOS transistor and a first resistance circuit; the grid electrode of the PMOS tube is grounded through the first resistance circuit, the drain electrode of the PMOS tube is connected with a load, and the source electrode of the PMOS tube and the input end of the fault protection circuit are connected with a power supply; the output end of the fault protection circuit is connected with the grid electrode of the PMOS tube; the sampling circuit is connected with the drain electrode of the PMOS tube and the ground; the output end of the sampling circuit and the control end of the fault protection circuit are connected to the control unit; the control unit judges whether load short circuit occurs or not according to the sampling voltage, if not, the fault protection circuit is forbidden to output voltage, and if yes, the fault protection circuit is controlled to convert input voltage into target voltage to be output; the PMOS tube is in a variable resistance region when the fault protection circuit has no voltage output, and enters a cut-off region when the PMOS tube outputs a target voltage.

To provide a display device capable of speeding up drive.SOLUTION: A display device includes: a first transistor connected between an image data signal line and a first node while switching is controlled by using a first control signal; a third transistor connected between the first node and a second node while switching is controlled by using a second control signal; a second transistor that has a gate electrode connected to the second node and is connected between a power line and a third node; a fourth transistor connected between a reference voltage power line and the second node while switching is controlled by using the second control signal; a fifth transistor connected between an initialization voltage power line and the third node while switching is controlled by using a third control signal; and a sixth transistor electrically connected between a precharge voltage power line and the first node while switching is controlled by using a fourth control signal.SELECTED DRAWING: Figure 5

A stack of semiconductor layers is formed. The semiconductor layers are spaced apart from one another in a vertical direction by a plurality of gaps in a cross-sectional side view. A plurality of gate dielectric layers is formed over the semiconductor layers. Each of the gate dielectric layers circumferentially surrounds a respective one of the semiconductor layers, and the gate dielectric layers are still spaced apart from one another in the vertical direction by the gaps in the cross-sectional side view. A dipole layer is formed that circumferentially surrounds each of the gate dielectric layers in the cross-sectional side view. The dipole layer contains dopants. The gaps are filled by different portions of the dipole layer in the cross-sectional side view. One or more annealing processes is performed to drive dopants of the dipole layer into the gate dielectric layers. The dipole layer is then removed.