5183results about "Transistor" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

A transient voltage surge protection circuit includes a discharge transistor having a drain coupled to a first point of a voltage input bus, and a source coupled to ground; an RC string having a first capacitor and a first resistor coupled in series; a first charge transistor having a drain coupled to the drain of the discharge transistor, a source coupled to the gate of the discharge transistor, and a gate coupled to a mid-point between the first capacitor and the first resistor; a second charge transistor having a drain coupled to the drain of the discharge transistor and a gate coupled to the gate of the first charge transistor; a Zener diode string coupled to a second point of the voltage input bus and coupled to a third and fourth resistors in series. A midpoint between the third and fourth resistors is coupled to the second resistor.

Semiconductor structures including stacked transistors are provided. The semiconductor structures can include a pair of stacked forksheet transistors that have a shared second (top) gate electrode, or the structures can include a pair of stacked forksheet transistors that have non-shared second (top) gate electrodes. In either of these embodiments, the second (top) gate electrode is separated from a first (bottom) gate electrode by a frontside gate cut structure.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

An integrated circuit device may include semiconductor regions; an insulating wall extending in a first lateral direction and passing in a vertical direction between a pair of semiconductor regions adjacent to each other in a second lateral direction among the semiconductor regions, a pair of nanosheet stacks overlapping the pair of semiconductor regions in the vertical direction and facing frontside surfaces of the pair of semiconductor regions, a pair of source / drain regions, and a backside contact. Each nanosheet stack may include a nanosheet having one end contacting a sidewall of the insulating wall in the second lateral direction. A contact end portion of the backside contact may be connected to one of the pair of source / drain regions. A contact sidewall of the backside contact may contact the insulating wall. The second lateral direction may be perpendicular to the first lateral direction.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, where a corrugated channel structure includes a first sidewall surface, a second sidewall surface and a top surface. In an example, the IC device includes a first contact region having a first conductivity type extending into a sidewall surface of the corrugated channel structure and a second contact region having an opposite second conductivity type extending into a horizontal surface adjacent to the sidewall surface.

A keyboard key structure comprising a key stem, a contact-based mechanical trigger, and a contactless analog key switch. The key stem is configured to be depressed and move along a linear path over a range of operation. The contact-based mechanical trigger is configured to activate after the key stem is depressed a threshold distance in the range of operation. In response to the contact-based mechanical trigger activating, the contactless analog key switch is configured to detect, at a sample rate, a position of the key stem between the threshold distance and an end of the range of operation after the key stem is depressed. The contact-based mechanical trigger can be a galvanic-type key switch. The contactless analog key switch can be one of an optical key switch, a magnetic key switch, or an inductive key switch.

Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a sacrificial gate structure over a portion of a fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked. The method also includes removing a portion of the fin structure not covered by the sacrificial gate structure, subjecting exposed surfaces of each first and second semiconductor layers to at least one radical species, removing an edge portion of the second semiconductor layers to form a cavity between two adjacent first semiconductor layers, and forming a dielectric spacer in the cavity.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

A semiconductor structure includes a first transistor including a first set of one or more channels, a second transistor vertically stacked over the first transistor, the second transistor including a second set of one or more channels, the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor. The semiconductor structure also includes a power plane at a first side of the semiconductor structure, and a contact extending from the first side of the semiconductor structure, through the power plane, to a source / drain region of the second transistor.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and / or to cause a voltage across the first gate terminal to be reduced.

Integrated circuit structures having multi-height cells, and methods of fabricating integrated circuit structures having multi-height cells, are described. For example, an integrated circuit structure includes a single height cell in a block, and a multi-height cell in the block, the multi-height cell having a single NMOS diffusion area and a single PMOS diffusion area, and the multi-height cell having a power rail above the single NMOS diffusion area and the single PMOS diffusion area, where the power rail is not shared between the multi-height cell and the single height cell. Another integrated circuit structure includes a row of relatively taller cells with relatively wider 2-stack nanosheets, and a row of relatively shorter cells with relatively narrower 2-stack nanosheet, the row of relatively shorter cells coupled to the row of relatively taller cells.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source / drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and / or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and / or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

A semiconductor device includes a source / drain region adjacent to a gate channel, a plurality of nanosheets extended vertically at the gate channel, and a source / drain extension (SDE) between the source / drain region and the plurality of nanosheets. Portions of the SDE in vicinity of the source / drain region are doped with a first dopant.

A semiconductor IC structure may include a first stacked transistor and a second stacked transistor. A conductive contact is at least partially between the first stacked transistor and the second stacked transistor. The conductive contact includes a deep via and an airgap spacer exists around the deep via and is in contact with respective source / drain regions and gates of the first stacked transistor and the second stacked transistor. The airgap spacer may reduce respective parasitic capacitances that exist between the conductive contact and the first and second stacked transistors. For example, the airgap spacer may relatively reduce capacitance between the deep via and the respective source / drain regions and gates of the first stacked transistor and the second stacked transistor.

Method to selectively diffuse dipole dopants into the high-k gate dielectric layer is provided. A method of the present disclosure includes an etching back process controlling DC and bias power, a periodical switching of the bias power is synchronized with a periodical switching of the DC power, leading to a balanced etching rate and uniform depth of recesses in dummy materials within the gate trenches for the subsequent selective diffusion process across different devices. Additionally, during the etching back process, a protective passivation layer can be formed as a barrier on the sidewall of the recess and / or at the bottom of the recess.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

A semiconductor structure including a first backside dielectric, a second backside dielectric, and an etch stop liner sandwiched between the first backside dielectric and the second backside dielectric.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

In one aspect of the disclosure, a variable-current gate driver includes a plurality of inputs for receiving pulse-width-modulation (PWM) control signals transmitted from a processing system. Current sources controlled based on the pulse-width modulation (PWM) signals are coupled to respective gates of at least two transistors of a hybrid switch in the power module (PM) including different semiconductor technologies. The current sources are coupled respectively to at least one other non-gate terminal of the transistors. The current sources provide the slew rate control of the PM using variable current values to compensate for differences in the at least two semiconductor technologies in real-time to reduce switching losses and maximize efficiency.