16495results about "Transistor" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

Gate-all-around integrated circuit structures having germanium-doped nanowire / nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire / nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.

The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

In certain aspects, a memory device includes a semiconductor layer, a peripheral circuit including a peripheral transistor in contact with the semiconductor layer, an array of memory cells disposed beside the semiconductor layer and the peripheral circuit, and bit lines coupled to the memory cells. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each of the bit lines extends in a second direction perpendicular to the first direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.

Gate isolation processes (e.g., gate-to-source / drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

To provide: a transistor with favorable electrical characteristics; a transistor with a high on-state current; a transistor with low parasitic capacitance; or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated.SOLUTION: There is provided a transistor including an oxide semiconductor layer, a semiconductor device, or a memory device. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region.SELECTED DRAWING: Figure 1

A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.

A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

The present disclosure comprises: a semiconductor switch unit including a first semiconductor switch having a drain terminal connected to a power grid, a second semiconductor switch having a drain terminal connected to a load, and first and second diodes each having a positive electrode and a negative electrode respectively connected to a source terminal and the drain terminal of each semiconductor switch; a bypass circuit which connects the drain terminal of the first semiconductor switch to the source terminal of the second semiconductor switch; and a control unit which, when the power grid is connected to the semiconductor circuit breaker, supplies a current to the load through the bypass circuit and the second diode by closing the bypass circuit while the first and second semiconductor switches are turned off, and which, when preset conditions are met, turns on the first and second semiconductor switches so as to open the bypass circuit so that a current is supplied to the load through the semiconductor switch unit.

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

A vertical high-electron-mobility transistor, HEMT (100), comprising: a substrate (310); a drain contact (410), the drain contact being a metal contact via through said substrate; a pillar layer (500) arranged above the drain contact (410) and comprising at least one vertical pillar (510) and a supporting material (520) laterally enclosing the at least one vertical pillar (510); a heterostructure mesa (600) arranged on the pillar layer (500), the heterostructure mesa (600) comprising an AlGaN-layer (610) and a GaN-layer (620), together forming a heterojunction (630); at least one source contact (420a, 420b) electrically connected to the heterostructure mesa (600); a gate contact (430) arranged on said heterostructure mesa (600), and above the at least one vertical pillar (510); wherein the at least one vertical pillar (510) is forming an electron transport channel between the drain contact (410) and the heterojunction (630).

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A plurality of nanosheet recesses are formed within a substrate. A placeholder structure is formed on a bottom surface within each nanosheet recess. A first source / drain region is formed within a first nanosheet recess. A second source / drain region is formed within the second nanosheet recess. The semiconductor structure is flipped. The substrate is removed respective to a sidewall spacer of the placeholder structure and a first etch stop layer of the placeholder structure. Backside interlayer dielectric is formed. A backside contact trench to the second source drain region is formed by removing a portion of the backside interlayer dielectric over the second source / drain region and removing exposed portions of the first etch stop layer, the sidewall spacer, and a silicon buffer layer of the placeholder structure. A backside contact is formed within the trench.

A method includes forming a first gate structure across a first active region on a substrate within a memory region, wherein the first gate structure is of a first transistor being of a first conductivity type; forming a second gate structure across a second active region on the substrate within a peripheral region, wherein the second gate structure is of a second transistor being of a second conductivity type, the second conductivity type is opposite to the first conductivity type; forming a first gate contact over the first gate structure, the first gate contact overlapping with the first active region; forming a second gate contact over the second gate structure, the second gate contact non-overlapping with the second active region.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving circuit and a control method thereof, the SiC MOSFET driving circuit comprises an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source inter-electrode voltage overshoot detection circuit, an analog-to-digital conversion module and an FPGA (Field Programmable Gate Array) module, and a self-adaptive adjustment algorithm is built in the FPGA module. The load current detection circuit and the drain-source inter-electrode voltage overshoot detection circuit have low requirements for real-time performance, use of high-speed simulation devices is avoided, hardware design cost is reduced, a self-adaptive adjustment algorithm can adjust SiC MOSFET gate drive parameters in real time according to output of the load current detection circuit and the drain-source inter-electrode voltage overshoot detection circuit, and the self-adaptive adjustment algorithm can adjust the gate drive parameters of the SiC MOSFET in real time according to the output of the drain-source inter-electrode voltage overshoot detection circuit. Therefore, overshoot and switching loss are self-adaptively balanced, and safe operation of the SiC MOSFET is ensured. The technical problems that a SiC MOSFET driving circuit driven by an active grid is high in hardware cost and is difficult to balance voltage and current overshoot and switching loss are solved.

Structures having registration marks for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer comprising a plurality of nanowire-based or fin-based transistors and a pad laterally adjacent to the plurality of nanowire-based or fin-based transistors, the pad having first grating structures aligned along an X-direction and second grating structures aligned along a Y-direction therein, the first and second grating structures exposed at a backside surface of the front side structure. The front-side also includes a plurality of metallization layers above the plurality of nanowire-based or fin-based transistors. The integrated circuit structure also includes a backside structure below the plurality of nanowire-based or fin-based transistors of the device layer of the front side structure, the backside structure comprising backside metal layers and vias.

Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

A semiconductor integrated-circuit (IC) chip includes: a first transistor, a second transistor at a same horizontal level as the first transistor, a first oxide layer at the same horizontal level as the first and second transistors, horizontally around the first and second transistors and having a portion horizontally between the first and second transistors; a frontside interconnection scheme under the first and second transistors and first oxide layer, a backside interconnection scheme over the first and second transistor and first oxide layer, and a metal interconnect vertically in the portion of the first oxide layer and coupling the frontside interconnection scheme to the backside interconnection scheme.

A semiconductor device comprises a gate cut portion disposed between a first gate region and a second gate region. The gate cut portion comprises a dielectric liner layer disposed around a vacant area. The dielectric liner layer encloses the vacant area, and the gate cut portion isolates the first gate region from the second gate region.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source / drain epitaxial layers on opposite sides of the first channel layer; forming second source / drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating depopulated channel structures using split source or drain approaches, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires, the first vertical arrangement of nanowires having one or more dielectric nanowires coupled to a dielectric source or drain structure. A first gate stack is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires having one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure laterally spaced apart from the dielectric source or drain structure. A second gate stack is over the second vertical arrangement of nanowires.

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, a first silicide liner directly beneath the first source drain region, and second silicide liner directly beneath the second source drain region, where the first silicide liner is a different material than the second silicide liner.

Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

A transistor includes a funneled interfacial source / drain (S / D) region that includes a narrow throat that is connected to or is an interface to the nanolayer channel. The funneled interfacial S / D region may also include a wide throat that is an interface to a remainder of the S / D region. The funneled interfacial source / drain (S / D) region may reduce parasitic resistance or impedance from the S / D region into or out of a nanolayer channel.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

A method includes forming a bottom-tier transistor and a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source / drain regions on opposite sides of the first channel layer; forming a first dielectric layer over the first source / drain regions of the top-tier transistor; etching the first dielectric layer to form a first opening exposing one of the first source / drain regions of the top-tier transistor; selectively forming a first metal silicide on the one of the first source / drain regions; selectively forming a first metal cap on the first metal silicide and not on the first dielectric layer; forming a front-side contact on the first metal cap.

A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.