731 results about "Superlattice" patented technology

The invention relates to the field of semiconductor optoelectronic device manufacturing, in particular to an LED epitaxial wafer growing method capable of reducing warping. Comprising the following steps of: growing a nucleating layer on a substrate at low temperature by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) process, and annealing to form a three-dimensional island-shaped structure to release stress; growing an AlGaN / GaN superlattice or gradient layer as a gradient buffer layer, and adjusting lattice constants layer by layer; a heavily doped or co-doped layer is inserted before growth of n-GaN, and thermal stress is pre-compensated by using local pressure stress; and finally, continuously growing a device layer and carrying out in-situ heat treatment to obtain the LED epitaxial wafer. The method effectively counteracts the macroscopic tensile stress caused by the difference of thermal expansion coefficients in the cooling process, and greatly improves the integrity of the epitaxial wafer.

The invention provides an anti-ferroelectric lanthanum ferrite, bismuth ferrite and strontium titanate superlattice film with high energy storage density as well as a preparation method and application thereof. The anti-ferroelectric lanthanum ferrite, bismuth ferrite and strontium titanate superlattice film with high energy storage density comprises a substrate layer, a bottom electrode layer and a plurality of stacked relaxation ferroelectric layers, wherein the bottom electrode layer and the multiple stacked relaxation ferroelectric layers are sequentially arranged on the substrate layer; each relaxor ferroelectric layer sequentially comprises a first functional layer, a second functional layer and a third functional layer from bottom to top; the first functional layer comprises LaFeO3, the second functional layer comprises BiFeO3, and the third functional layer comprises SrTiO3. The anti-ferroelectric lanthanum ferrite, bismuth ferrite and strontium titanate superlattice thin film with the high energy storage density has small electric leakage performance and high polarization value, and more excellent energy storage performance is achieved.

The invention provides an optimized II-type superlattice infrared detector chip bottom filling method, a preparation method and an infrared detector, and belongs to the field of infrared detectors. The problem that the performance of an infrared detector is affected due to the fact that the filling glue filled in an existing bottom filling process is prone to generating holes and finally causes defects during imaging of an infrared focal plane detector chip is solved. The method comprises the following steps that a dielectric layer is deposited on the surface of an epitaxial material after table top etching is completed, and the height of the dielectric layer is larger than the table top etching depth; after the dielectric layer is deposited, the surface of the dielectric layer is polished to be flat; opening holes in the dielectric layer on the surface of the table board; preparing an indium column in the opening of the dielectric layer, and then performing flip-chip bonding interconnection on the indium column at the epitaxial material end and the indium column on the readout circuit; filling bottom filling glue between the dielectric layer and the reading circuit after the reverse welding interconnection, and then curing the filling glue at high temperature; the invention is applied to the type-II superlattice infrared detector.

The invention discloses a P2-phase sodium ion positive electrode material with a superlattice ordered structure and a preparation method of the P2-phase sodium ion positive electrode material. The chemical formula of the P2-phase sodium ion positive electrode material is Na < x > M < 1-a-b > A B O < 2 >, wherein M is a transition metal element Mn or / and Ni; a doping sites are transition metal vacancies, and / or doped metal elements Mg and / or doped metal elements Li; the doping site of B is doped with a transition metal element Fe or doped with a transition metal element Cu or doped with a transition metal element Zn; 0.8 < = x < = 0.9, 0.25 < = a, 0.04 < = b < = 0.09. According to the P2 type material with the superlattice ordered structure, the layered structure stability and the sodium ion transmission efficiency of the material can be remarkably improved, so that the problems of poor structure stability and low ion diffusion rate of a traditional sodium ion positive electrode material are effectively solved; the P2 type material with the superlattice ordered structure can be suitable for preparing a sodium ion battery system with high energy density.

The invention relates to a method for improving epitaxial growth quality of a tunnel junction cascade semiconductor laser. The invention innovatively provides a strain superlattice gradient repair technology. By designing a low-temperature low-speed nucleation-high-temperature high-speed epitaxy composite growth mode, a periodic superlattice buffer layer is introduced to a tunnel junction interface. Wherein lattice strain relaxation is achieved at the rate of 0.5-2 / s in the low-temperature stage, defect coverage is completed at the rate of 4-8 / s in the high-temperature stage, and dislocation line bending is terminated on a superlattice interface through thermodynamic regulation and control. Compared with the traditional process, the scheme can obviously improve the crystal quality, and does not increase the specific contact resistance of the tunnel junction interface.

The invention relates to the technical field of chip preparation, and provides a chip based on an annular photonic crystal and a preparation method thereof. The preparation method comprises the following steps: growing a nucleating layer on a substrate; growing a superlattice structure on one side, away from the substrate, of the nucleating layer; sequentially growing an n-type coating layer, an n-type waveguide layer, a quantum well and a p-type electron blocking layer on one side, deviating from the nucleating layer, of the superlattice structure; etching a plurality of annular cavities on the p-type electron barrier layer to form an annular photonic crystal; growing a p-type extension contact layer on one side, deviating from the quantum well, of the p-type electron blocking layer; and carrying out in-situ annealing treatment. According to the preparation method, the directivity of the photonic band gap can be effectively adjusted, uniform light waves in all directions on the side face can be formed, so that leakage of laser from a non-light-emitting area on the side face is restrained, the light emitting efficiency is improved, the annular photonic crystals are periodically distributed, and the light beam quality is effectively guaranteed.

The invention provides a short-wave infrared detector digital alloy material and a preparation process thereof. The preparation process comprises the following steps: growing a GaSb buffer layer on the surface of an n-type GaSb substrate; starting a first In furnace, and growing an InAs layer on the surface of the GaSb buffer layer in cooperation with an As beam; starting a second In furnace, and growing a quaternary solid solution layer matched with a GaSb buffer layer lattice on the surface of the InAs layer in cooperation with the Ga furnace and the AsSb beam; and alternately growing an InAs layer and a quaternary solid solution layer on the surface of the quaternary solid solution layer to generate a superlattice structure until the total thickness of the superlattice structure reaches a set target thickness, thereby obtaining the digital alloy material. According to the digital alloy material for the short-wave infrared detector and the preparation technology of the digital alloy material, the short-wave infrared detector can be expanded to the wave band ranging from 2.4 micrometers to 2.8 micrometers at the 50% cut-off wavelength.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

The invention relates to the technical field of semiconductor light-emitting devices, and particularly discloses an epitaxial structure for improving the internal quantum efficiency of a green Micro LED. The epitaxial structure comprises a substrate, and a buffer layer, an undoped GaN layer, an n-type GaN layer, a stress release layer, an active layer, a low-temperature Mg heavily-doped GaN layer, an electron barrier layer, a p-type GaN layer and a p-type GaN contact layer which are sequentially arranged on the substrate. The active layer comprises a plurality of periods of InGaN quantum well layers and an InAlGaN / GaN superlattice quantum barrier layer alternating structure, and a CAP layer formed by an AlGaN / GaN superlattice is arranged behind each quantum well layer. By adopting a wide-well narrow-barrier structure, a superlattice CAP layer for neutralizing a polarization electric field and a quaternary InAlGaN barrier structure for lattice matching and hole injection enhancement, multiple regulation and control of a polarization field, dislocation density and hole transport are realized, the internal quantum efficiency of a green-light Micro LED is remarkably improved, and the green-light Micro LED epitaxial structure is suitable for epitaxial preparation of a high-performance Micro LED chip.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

The present invention relates to the field of optoelectronics, and discloses a light-emitting diode epitaxial wafer, a method for manufacturing the same, and an LED. The light-emitting diode epitaxial wafer comprises a substrate, on which a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially provided; the electron blocking layer comprises a BAlN / P-GaN superlattice layer, an AlGaN / P-InGaN superlattice layer, and a BN layer stacked in sequence. The light-emitting diode epitaxial wafer provided by the present invention reduces electron overflow, improves hole injection efficiency, replenishes hole concentration, and enhances the luminous efficiency of the light-emitting diode.

The invention, which relates to the technical field of the semiconductor laser chip, discloses a wide-temperature working high-power DFB semiconductor laser chip comprising a P-InGaAsP lower waveguide layer, an InGaAsP strain multiple quantum channel, an N-InGaAsP upper waveguide layer, an InAlAs-InP superlattice barrier layer, an N-InP spacing layer 1, an N-InGaAsP corrosion stop layer, an N-InP spacing layer 2, an N-InGaAsP grating layer, and an N-InP grating cover layer. According to the wide-temperature working high-power DFB semiconductor laser chip, a laser material structure is epitaxially grown on a P-InP substrate; a P-InP substrate is adopted, so that large-area back ohmic contact effectively reduces P-type series resistance of a device, and the problem of high heating of a traditional high-power laser is effectively solved; then, an InGaAsP strain compensation quantum well is adopted as a gain region, and wide-temperature single-mode work is realized by utilizing the advantage that an InGaAsP gain spectrum is insensitive to temperature; and the InAlAs-InP two-dimensional superlattice barrier structure is adopted to realize transverse and lateral limitation of carriers, so that the limiting efficiency of the carriers in a gain region is effectively improved, and the problem of low energy band difference of an InGaAsP conduction band is effectively solved.

The invention provides an ultrahigh strain material component and thickness control method for a quantum cascade laser, and relates to the technical field of semiconductor lasers. The control method is based on a strain compensation calibration method, a first superlattice layer and a second superlattice layer which are the same in thickness are constructed, a strain balance superlattice is formed, it is guaranteed that the whole epitaxial layer is free of strain relative to a substrate, the problem that the growth thickness of a large-strain material is small is solved, the peak position accuracy and the peak intensity during XRD testing are further improved, and the test accuracy is improved. And the half-peak width is narrow, so that the accuracy of the components of the backstepping material is improved.

The invention relates to the technical field of semiconductor materials, in particular to a low-working-current-density cyan LED epitaxial structure and a preparation method thereof.The low-working-current-density cyan LED epitaxial structure comprises a substrate, and a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum-well light-emitting layer and a P-type semiconductor layer which are sequentially stacked on the substrate; the multi-quantum well light-emitting layer comprises a first light blue light multi-quantum well sub-layer, a second blue light multi-quantum well sub-layer, a third blue light multi-quantum well sub-layer and a fourth light blue light multi-quantum well sub-layer which are sequentially stacked and grown from bottom to top; wherein each sub-layer is of a superlattice structure of an InGaN multi-quantum well layer and a multi-quantum barrier layer, and the barrier heights of the sub-layers decrease progressively in a gradient mode, namely, the high barrier, the middle barrier, the low barrier and the low barrier decrease progressively in sequence. The upper-layer low-potential barrier attracts holes to migrate downwards, and the lower-layer high-potential barrier blocks electrons from leaking, so that space matching of the electrons and the holes is realized, and the performances such as luminous efficiency and yield of the cyan LED chip under low working current density are improved.

The invention is suitable for the technical field of semiconductors, and provides a blue-green double-peak LED epitaxial growth method, which comprises the following steps: processing a substrate, growing a low-temperature GaN buffer layer, growing a non-doped GaN layer, growing a Si-doped N-type GaN layer, growing a multi-quantum well layer, growing an AlGaN electron barrier layer, growing a Mg-doped P-type GaN layer, and cooling. Wherein the growth of the multi-quantum well layer sequentially comprises the steps of growing a first MQWs, growing a tunnel junction layer, growing a second MQWs and growing an AlGaN / GaN superlattice layer, the tunnel junction layer is introduced into the multi-quantum well layer to enhance tunneling of holes, meanwhile, the AlGaN / GaN superlattice layer is introduced, gradual change of an Al component in AlGaN is controlled by controlling the introduction time of TMAl, the problem of light emitting peak broadening is solved, and the light emitting efficiency is improved. The quantum well is ensured to emit blue light and green light at the same time, the color saturation of the light is improved, and the color temperature is reduced.

The invention provides a manufacturing method of a type-II superlattice medium-wave infrared focal plane array chip and an infrared detector, and belongs to the field of infrared focal plane array chips. The problem that in the prior art, the surface leakage current of an infrared focal plane array chip is large due to the fact that the mesa etching depth is large is solved. The method comprises the following steps: growing and cleaning an epitaxial material; hard mask deposition, mesa photoetching and etching: obtaining a required mesa pattern on the hard mask through a photoetching technology, then etching an epitaxial material, etching the epitaxial material to form the mesa pattern, the mesa pattern comprising an upper electrode region and a lower electrode region, etching the upper electrode region to the boundary of the barrier layer and the absorption region, and etching the lower electrode region to the boundary of the barrier layer and the absorption region; etching a lower electrode region to the lower ohmic contact layer; manufacturing a metal electrode; a connecting piece is manufactured on the metal electrode to be connected with a reading circuit, and manufacturing of the infrared focal plane array chip is completed; the invention is applied to the II-type superlattice medium-wave infrared detector.

The invention provides an anti-radiation high-performance enhanced gallium nitride-based power device and a manufacturing method thereof, and belongs to the technical field of semiconductors. On the basis of a traditional enhanced P-GaN HEMT device structure, a P-type InaGa1-aN back barrier layer, an InbGa1-bN / GaN superlattice layer, a composite gate structure composed of a dielectric layer and a gate Schottky metal layer and a gradient-changing island-shaped P-GaN layer are innovatively introduced, and a pair of composite problems of dynamic resistance instability and radiation sensitivity are cooperatively solved. The device not only maintains the normally-off characteristic and the high threshold voltage of an enhanced device, but also remarkably improves the anti-irradiation capability, the breakdown voltage and the dynamic resistance stability, and is particularly suitable for power electronics in strong irradiation environments such as aerospace and nuclear energy detection.

The invention discloses an atomic layer deposition method and structure for an aluminum fluoride enhanced aluminum oxide passivation layer of a TOPCon solar cell. The method comprises the steps that after a boron-doped layer is formed on the front face of a crystal silicon wafer, a passivation layer is formed on the boron-doped layer through an atomic layer deposition technology, specifically, Al2O3 deposition circulation is conducted with trimethyl aluminum as an aluminum source and H2O as an oxygen source, AlF3 deposition circulation with aluminum chloride as the aluminum source and HF or NH4F as a fluorine source is periodically inserted, the proportion of the number of deposition circulation times of AlF3 to the number of deposition circulation times of Al2O3 is 1: (1-10), and the passivation layer is formed on the boron-doped layer through the atomic layer deposition technology. And an alternating layer structure with the total thickness of 5-10 nm is formed. According to the invention, an AlF3 layer is periodically inserted in an Al2O3 deposition cycle, so that an Al2O3 / AlF3 superlattice structure is formed. According to the structure, the interface passivation effect is remarkably improved, hydrogen atom overflow is reduced, and the ultraviolet aging resistance is enhanced. The method is compatible with an existing ALD production line, is suitable for high-efficiency TOPCon battery manufacturing, and has a good industrial application prospect.

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include forming an internal spacer liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) arranged alternately in a plurality of stacked pairs. The internal spacer liner includes a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner can be doped with a dopant (e.g., with a p-type dopant or an n-type dopant). One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

The invention provides a nitride semiconductor laser. The laser comprises a substrate, a lower coating layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper coating layer which are sequentially arranged from bottom to top. And the lower waveguide layer comprises any one or a combination of more of InGaN, GaN, InN, AlInGaN, an InGaN / GaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlInN superlattice and an InGaN / AlInGaN superlattice. The peak rate electric field distribution of the lower waveguide layer has an arc distribution, and the peak rate electric field distribution has a curve distribution of a function y = logax (a > 1). The drift rate distribution of the saturated electrons of the lower waveguide layer has an arc-shaped distribution, and the drift rate distribution of the saturated electrons has a curve distribution of a third quadrant of a function y = x-b (b > 1, b is an odd number). The density distribution of valence band effective states of the lower waveguide layer has a curve distribution of a third quadrant of a function y = (cx + 1) / (cx-1) (c > 1).

The invention provides an etching method of a double-color second-class superlattice infrared detector, and belongs to the technical field of chip manufacturing. The method comprises the following steps: providing a double-color second-class superlattice infrared detector, and forming a photoresist mask on the surface of the double-color second-class superlattice infrared detector; under the condition that the ratio of the longitudinal etching rate to the transverse etching rate is not less than 5: 1, performing dry etching on the surface of the double-color second-class superlattice infrared detector to obtain an initial mesa structure; the initial mesa structure is subjected to wet etching, a middle mesa structure is obtained, the wet etching time is smaller than or equal to 2 min, and the wet etching temperature is smaller than or equal to 10 DEG C; and post-processing the middle table-board structure to obtain the table-board structure. Through organic combination of a high-anisotropy forming effect of dry etching and a low-damage repairing effect of wet etching, the low surface damage characteristic is considered while high aspect ratio etching is realized, the dark current of the device is fundamentally reduced, and the intrinsic detection performance of the device is improved.

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

The invention relates to the technical field of semiconductor material preparation, in particular to an InAs / GaSb superlattice material and an epitaxial growth method thereof, and the method comprises the following steps: S1, providing a substrate; s2, epitaxially growing a buffer layer on the substrate; s3, a plurality of periods of InAs / GaSb superlattice structures are sequentially grown on the buffer layer in an epitaxial mode, each period of InAs / GaSb superlattice structure comprises an I-type InSb interface layer, a first InAs layer, a second InAs layer, a third InAs layer, an II-type InSb interface layer and a GaSb layer which are sequentially grown in an epitaxial mode, and the growth rate of the first InAs layer and the growth rate of the third InAs layer are lower than the growth rate of the second InAs layer. The InAs layer is divided into three layers to grow, and the growth rate of the first InAs layer and the third InAs layer is designed to be smaller than the growth rate of the second InAs layer in the middle, so that the influence of MBE cavity As background beam on the superlattice quality in the superlattice growth process can be effectively inhibited, the interface layer quality is improved, the growth interruption time does not need to be increased, the interface growth complexity is reduced, and the production efficiency is improved. And the repeatability of the MBE growth process is improved.

Described are methods for forming complementary field-effect transistor (CFET), or other vertically aligned semiconductor structures, utilizing a sequential self-aligning process. In one example, a method of forming a complementary field-effect transistor (CFET) is provide. The method includes replacing top sacrificial layers interleaved between channel layers in a top superlattice of a top device structure with top replacement metal gate layers, the top device structure disposed on a bottom device structure, the bottom device structure disposed on a first substrate layer; securing a second substrate layer to the top device structure and removing the first substrate layer from the bottom device structure; and replacing bottom sacrificial layers interleaved between channel layers in a bottom superlattice of the bottom device structure with bottom replacement metal gate layers.

The invention discloses a surface coating for prolonging the fatigue life of metal and a preparation method of the surface coating. According to the coating, face-centered cubic structure layers and hexagonal system structure layers are alternately stacked to form a superlattice structure, the total thickness ranges from 1.0 micrometer to 1.5 micrometers, and a base material is titanium alloy. The thickness of the face-centered cubic structure layer is 4-6 nm, the thickness of the hexagonal system structure layer is 1-3 nm, the Mohs hardness difference between the two layers is not larger than 2, and the average grain size is 1-2 nm. According to the coating, a stable high-toughness interface phase is obtained through a specific crystal structure and thickness regulation and control, and dislocation slippage and crack propagation are effectively prevented. A magnetron sputtering method is adopted for preparation, and the process comprises the steps of substrate surface pretreatment, bias cleaning and alternate deposition. The coating shows excellent anti-fatigue performance under the cyclic load condition, and the service life of the titanium alloy component can be remarkably prolonged.

The invention provides a single-mode 660nm semiconductor laser device with a superlattice structure and a preparation method of the single-mode 660nm semiconductor laser device, and belongs to the technical field of photoelectrons. The multi-quantum-well multi-quantum-well light-emitting diode sequentially comprises a GaAs substrate, a buffer layer, a sectional lower limiting layer, a lower waveguide layer, a multi-quantum-well active region, an AlInP / GaP superlattice, an upper waveguide layer, a sectional upper limiting layer, a band gap transition layer and a GaAs cap layer from bottom to top. The preparation method comprises the processes of substrate processing, buffer layer growth, V-group source switching, limiting layer and waveguide layer epitaxy, multi-quantum well and superlattice structure growth, cap layer deposition and the like. Through the segmented design of the superlattice structure and the limiting layer, the hole injection efficiency and the carrier limiting capability are improved, and the high-temperature working characteristic of the device is effectively improved. Stable output of single-mode laser in the 660nm wave band is achieved, reliable power output of 120mW can be kept in a high-temperature environment of 60 DEG C, and meanwhile, low loss, high conversion efficiency and excellent photoelectric performance are achieved.

The invention discloses a light-emitting diode chip for improving the polarization effect of a quantum well light-emitting layer and a preparation method of the light-emitting diode chip. Comprising a sapphire patterned substrate, a buffer layer, a defect barrier layer, an N-type gallium nitride layer, a current expansion layer, a stress release layer, a quantum well light-emitting layer, a polarization buffer layer, a P-type electron barrier layer, a P-type gallium nitride layer, a transparent conductive layer, an electrode layer and a protective layer which are sequentially arranged from bottom to top. The polarization buffer layer is arranged between the quantum well light-emitting layer and the P-type electron blocking layer, buffers energy level abrupt change, and improves the polarization effect. A composite structure of an In < x > Ga < 1-x > N / GaN superlattice and a GaN / Al < y > Ga < 1-y > N superlattice is inserted between the multi-quantum well layer and the electron blocking layer, mutation of energy level is buffered by adjusting gradient doping of In and Al, the polarization effect in quantum wells caused by high potential barriers of the electron blocking layer is effectively improved, and the luminous efficiency of the diode is further improved.

The invention provides a superlattice material and a growth method thereof, and the growth method comprises the following steps: S1, growing an AlSb / AlAsSb superlattice, and growing an AlSb layer; s2, infiltrating the grown AlSb / AlAsSb for a design time under the protection of an Sb beam, keeping an As shutter closed in the process, and opening an As valve to a proper opening degree at the same time, so that an As beam is gradually dispersed into a cavity; s3, adjusting the opening degree of an As valve step by step, introducing the As source into the growth cavity in a gradually increasing manner at the rate, and correspondingly reducing the Sb source flow step by step; s4, switching the background protection beam current into an As protection beam current; and S5, growing an InAs / InAsSb superlattice. According to the method, after the AlSb / AlAsSb superlattice is grown and before the InAs / InAsSb superlattice is initially grown, an Sb protection stage and a controlled As protection beam gradient conversion step are introduced, the interface between the AlSb / AlAsSb and the InAs / InAsSb can be close to an ideal atomic-scale steep interface through cooperative control over Sb and As, and accurate control over the multicomponent compound superlattice components is achieved.

The invention relates to the technical field of micro-nano processing of semiconductor devices, in particular to an InAs / GaSb class-II superlattice mesa wet etching solution and a using method thereof, the etching solution is an aqueous solution comprising citric acid, phosphoric acid and hydrogen peroxide, the citric acid is citric acid monohydrate, the mass concentration of the phosphoric acid is 85%, and the mass concentration of the hydrogen peroxide is 30%. By optimizing the proportion of the components of the corrosive liquid and introducing an adjustable corrosion time sequence and a post-treatment technique, high repeatability and high uniformity of the corrosion process can be realized on the premise of keeping the intrinsic electrical properties of the material, the morphology quality of the mesa structure can be remarkably improved, and the smooth and low-damage mesa side wall and surface can be obtained. The method lays a reliable process foundation for preparing a high-performance InAs / GaSb class-II super-crystal-based infrared detector, is particularly beneficial to suppressing electric leakage of the side wall of a device, reduces dark current, and finally improves the quantum efficiency and imaging performance of the device.

The invention provides a mesa side wall passivation method for a class-II superlattice infrared detector and the infrared detector, and belongs to the field of semiconductor manufacturing. The problems of high interface state density and large dark current caused by a natural oxide layer rich in Sb2O5 formed by exposing the side wall of the aluminum antimonide or arsenic aluminum antimonide barrier layer to the atmosphere are solved; the method comprises the following steps of: cleaning and drying a second-class superlattice infrared detector chip subjected to mesa etching, and then loading the second-class superlattice infrared detector chip into a sample cavity of ALD (Atomic Layer Deposition) equipment; vacuumizing and heating; introducing high-purity hydrogen into a remote plasma source, starting the remote plasma source, selectively reducing the unstable natural oxide layer on the surface of the side wall of the barrier layer of the chip into volatile gas through hydrogen plasma, and pumping away the volatile gas through a vacuum system; after hydrogen plasma treatment is finished, a gas path is switched to an ALD precursor to form a passive film on the side wall of the barrier layer; cooling and taking the sheet; the invention is applied to the infrared detector.