1155 results about "Superlattice" patented technology

The invention provides a superlattice infrared detector chip manufacturing method, and belongs to the technical field of infrared detector manufacturing. The problem that the product performance or the product yield is low due to the fact that the precision fluctuation of the photoetching technology when the hard mask is removed is not considered in the current hard mask removing scheme is solved; comprising the following steps: forming a hard mask: growing the hard mask with a certain thickness on the surface of a wafer made of a superlattice material; photoetching an upper electrode table top; etching a hard mask: taking the photoresist as a mask, and etching the hard mask by adopting an ICP (Inductively Coupled Plasma) technology to obtain an upper electrode mesa mask pattern; degumming and cleaning an upper electrode table board; photoetching a lower electrode table board: adopting photoresist as a mask of a lower electrode table board area, and manufacturing the lower electrode table board area through a photoetching technology; carrying out ICP etching on the table board; performing wet etching on the table board; degumming and cleaning a lower electrode table board; forming a passivation layer film; opening holes in the passivation layer; manufacturing a gold electrode; the method is applied to preparation of the superlattice infrared detector chip.

The invention relates to the field of semiconductor optoelectronic device manufacturing, in particular to an LED epitaxial wafer growing method capable of reducing warping. Comprising the following steps of: growing a nucleating layer on a substrate at low temperature by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) process, and annealing to form a three-dimensional island-shaped structure to release stress; growing an AlGaN / GaN superlattice or gradient layer as a gradient buffer layer, and adjusting lattice constants layer by layer; a heavily doped or co-doped layer is inserted before growth of n-GaN, and thermal stress is pre-compensated by using local pressure stress; and finally, continuously growing a device layer and carrying out in-situ heat treatment to obtain the LED epitaxial wafer. The method effectively counteracts the macroscopic tensile stress caused by the difference of thermal expansion coefficients in the cooling process, and greatly improves the integrity of the epitaxial wafer.

The invention relates to the technical field of photoelectricity, and discloses a Micro LED epitaxial wafer, a preparation method thereof and a Micro LED chip, the Micro LED epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, an N-type GaN layer, a multi-quantum well layer and a P-type GaN layer; the first multi-quantum well layer comprises at least one group of a first InGaN quantum well layer, a first AlGaN / GaN superlattice layer and a first GaN quantum barrier layer which are stacked in sequence, and the second multi-quantum well layer comprises at least one group of a second InGaN quantum well layer, a second AlGaN / GaN superlattice layer and a second GaN quantum barrier layer which are stacked in sequence. And the third multi-quantum well layer comprises at least one group of third InGaN quantum well layer, hole injection layer and third GaN quantum barrier layer which are stacked in sequence. According to the Micro LED epitaxial wafer provided by the invention, the lighting effect of a Micro LED chip under low working current density can be improved.

The invention discloses a high-durability superlattice wurtzite ferroelectric material and preparation and application thereof.The high-durability superlattice wurtzite ferroelectric material is of a stacked structure composed of wurtzite ferroelectric films and AlN films alternately, and the total layer number of the stacked structure is larger than two. The first layer and the last layer of the stacked structure are wurtzite ferroelectric films. The preparation method comprises the following steps: depositing a layer of wurtzite ferroelectric film on the substrate; depositing a layer of AlN thin film on the obtained wurtzite ferroelectric thin film; a layer of wurtzite ferroelectric film is deposited on the obtained AlN film; the steps are repeated until a required stacked structure is formed, and the material can be used for a ferroelectric memory. The AlN thin film with good lattice matching performance with the wurtzite ferroelectric thin film is inserted into the wurtzite ferroelectric thin film, so that the durability of the thin film is improved, the superlattice structure shows excellent performance of low defect, low electric leakage, high durability and the like, and the breakdown resistance and durability of the ferroelectric memory are improved when the superlattice structure is applied to the ferroelectric memory.

The invention provides an anti-ferroelectric lanthanum ferrite, bismuth ferrite and strontium titanate superlattice film with high energy storage density as well as a preparation method and application thereof. The anti-ferroelectric lanthanum ferrite, bismuth ferrite and strontium titanate superlattice film with high energy storage density comprises a substrate layer, a bottom electrode layer and a plurality of stacked relaxation ferroelectric layers, wherein the bottom electrode layer and the multiple stacked relaxation ferroelectric layers are sequentially arranged on the substrate layer; each relaxor ferroelectric layer sequentially comprises a first functional layer, a second functional layer and a third functional layer from bottom to top; the first functional layer comprises LaFeO3, the second functional layer comprises BiFeO3, and the third functional layer comprises SrTiO3. The anti-ferroelectric lanthanum ferrite, bismuth ferrite and strontium titanate superlattice thin film with the high energy storage density has small electric leakage performance and high polarization value, and more excellent energy storage performance is achieved.

The invention belongs to the technical field of solid hydrogen storage, and provides a solid alloy hydrogen storage device with high heat transfer performance and application thereof, and is characterized in that the device comprises a hydrogen storage container, a hydrogen storage alloy and a heat exchange structure assembly; a fin structure and a layering partition plate are arranged in the hydrogen storage container, by optimizing the layering partition plate and the fin structure, displacement and agglomeration of hydrogen storage alloy in a moving or vibrating environment are effectively prevented, the mass transfer and heat transfer performance in the hydrogen storage tank is remarkably improved, hydrogen and heat can be rapidly transferred to the hydrogen storage alloy, and the hydrogen storage effect is improved. Therefore, the hydrogen absorption and desorption efficiency is improved. The method is suitable for AB2 type alloys, AB5 type alloys, BCC type alloys, superlattice hydrogen storage alloys and the like, the hydrogen absorption and desorption process can be efficiently completed at a certain temperature and pressure, and the high efficiency and stability of the hydrogen absorption and desorption process are ensured. And the catalyst can be widely applied to various scenes such as traffic, hydrogen refueling stations, industrial processes and hydrogen energy storage.

The invention discloses an ultra-steep sub-threshold slope transistor and a preparation method thereof, and belongs to the technical field of integrated circuits. An ultra-steep sub-threshold slope transistor is realized by using a superlattice stacked high-kappa gate dielectric, the superlattice stacked high-kappa gate dielectric comprises a plurality of HfO2 / ZrO2 / HfO2 stacking units which are stacked together, and an insertion layer is arranged between every two adjacent stacking units. Growing the superlattice stacked high-kappa gate dielectric by adopting an atomic layer deposition method, performing annealing treatment, and adjusting the gate dielectric interface, the electric leakage characteristic and the proportion of a ferroelectric quadrature phase to an antiferroelectric tetragonal phase by adjusting the type of an insertion layer and / or adjusting an oxygen source and pulse time thereof during growth, so as to obtain the superlattice stacked high-kappa gate dielectric. An ultra-steep sub-threshold slope transistor with a high on-off ratio is achieved. Compared with a traditional transistor, the transistor provided by the invention has higher on-state current, lower sub-threshold swing and smaller electric leakage.

The invention provides an optimized II-type superlattice infrared detector chip bottom filling method, a preparation method and an infrared detector, and belongs to the field of infrared detectors. The problem that the performance of an infrared detector is affected due to the fact that the filling glue filled in an existing bottom filling process is prone to generating holes and finally causes defects during imaging of an infrared focal plane detector chip is solved. The method comprises the following steps that a dielectric layer is deposited on the surface of an epitaxial material after table top etching is completed, and the height of the dielectric layer is larger than the table top etching depth; after the dielectric layer is deposited, the surface of the dielectric layer is polished to be flat; opening holes in the dielectric layer on the surface of the table board; preparing an indium column in the opening of the dielectric layer, and then performing flip-chip bonding interconnection on the indium column at the epitaxial material end and the indium column on the readout circuit; filling bottom filling glue between the dielectric layer and the reading circuit after the reverse welding interconnection, and then curing the filling glue at high temperature; the invention is applied to the type-II superlattice infrared detector.

The invention discloses a P2-phase sodium ion positive electrode material with a superlattice ordered structure and a preparation method of the P2-phase sodium ion positive electrode material. The chemical formula of the P2-phase sodium ion positive electrode material is Na < x > M < 1-a-b > A B O < 2 >, wherein M is a transition metal element Mn or / and Ni; a doping sites are transition metal vacancies, and / or doped metal elements Mg and / or doped metal elements Li; the doping site of B is doped with a transition metal element Fe or doped with a transition metal element Cu or doped with a transition metal element Zn; 0.8 < = x < = 0.9, 0.25 < = a, 0.04 < = b < = 0.09. According to the P2 type material with the superlattice ordered structure, the layered structure stability and the sodium ion transmission efficiency of the material can be remarkably improved, so that the problems of poor structure stability and low ion diffusion rate of a traditional sodium ion positive electrode material are effectively solved; the P2 type material with the superlattice ordered structure can be suitable for preparing a sodium ion battery system with high energy density.

The invention discloses a strong spin-orbit torque metal superlattice thin film material, and belongs to the technical field of new spin electron materials. The superlattice thin film material comprises a thin film system formed by heavy metal layers with strong spin-orbit coupling and light metal layers with high-orbit Hall conductivity, wherein the heavy metal layers periodically grow on a substrate; in each period, the thickness of the heavy metal layer with strong spin-orbit coupling is 1-3nm, and the thickness of the light metal layer with high-orbit Hall conductivity is 1-3nm. Electron orbital angular momentum flow accumulation is generated on the surface of the light metal layer, the orbital current is injected into heavy metal with strong spin-orbit coupling, and the orbital current is converted into spin current by utilizing the strong spin-orbit coupling characteristic of the heavy metal layer. Therefore, the spin current generation efficiency of the strong spin orbit torque metal superlattice thin film material can be improved, and the giant damping spin orbit torque efficiency and the low-current-density turnover ferromagnetic layer magnetic moment are realized.

The invention relates to a method for improving epitaxial growth quality of a tunnel junction cascade semiconductor laser. The invention innovatively provides a strain superlattice gradient repair technology. By designing a low-temperature low-speed nucleation-high-temperature high-speed epitaxy composite growth mode, a periodic superlattice buffer layer is introduced to a tunnel junction interface. Wherein lattice strain relaxation is achieved at the rate of 0.5-2 / s in the low-temperature stage, defect coverage is completed at the rate of 4-8 / s in the high-temperature stage, and dislocation line bending is terminated on a superlattice interface through thermodynamic regulation and control. Compared with the traditional process, the scheme can obviously improve the crystal quality, and does not increase the specific contact resistance of the tunnel junction interface.

The invention discloses an InGaN red light LED device based on a variable Al component electron barrier layer to enhance a polarization effect and a preparation method thereof. The InGaN red light LED device sequentially comprises a substrate, a low-temperature buffer layer, a high-temperature buffer layer, a non-doped GaN layer, an n-type doped GaN layer, a superlattice layer and / or a low-temperature GaN layer, a quantum well active region, a p-type AlGaN electron barrier layer and a p-type region from bottom to top, wherein the atomic percentage content of Al in the p-type AlGaN electron barrier layer is 22%-30%, and the thickness of the p-type AlGaN electron barrier layer is 5 nm to 15 nm. By controlling the p-type AlGaN electron barrier layer, long-wavelength emission of the low-In-component active region can be achieved, and the problems that a high-In-component active region of an existing long-wavelength InGaN red light LED is poor in crystal quality and difficult to obtain and the like are solved.

The invention relates to the technical field of chip preparation, and provides a chip based on an annular photonic crystal and a preparation method thereof. The preparation method comprises the following steps: growing a nucleating layer on a substrate; growing a superlattice structure on one side, away from the substrate, of the nucleating layer; sequentially growing an n-type coating layer, an n-type waveguide layer, a quantum well and a p-type electron blocking layer on one side, deviating from the nucleating layer, of the superlattice structure; etching a plurality of annular cavities on the p-type electron barrier layer to form an annular photonic crystal; growing a p-type extension contact layer on one side, deviating from the quantum well, of the p-type electron blocking layer; and carrying out in-situ annealing treatment. According to the preparation method, the directivity of the photonic band gap can be effectively adjusted, uniform light waves in all directions on the side face can be formed, so that leakage of laser from a non-light-emitting area on the side face is restrained, the light emitting efficiency is improved, the annular photonic crystals are periodically distributed, and the light beam quality is effectively guaranteed.

The invention relates to the technical field of semiconductor devices, in particular to an epitaxial structure of an LED quantum well and a growth method of the epitaxial structure. Comprising an active layer, the active layer is formed by periodically stacking a plurality of unit structures, each unit structure comprises a quantum well layer, a cover layer and a quantum barrier layer which grow in sequence, and the quantum well layer comprises a superlattice structure formed by an indium gallium nitride layer and a processing layer which grow alternately. The growth time of indium gallium nitrogen is short, the thickness of a single layer is 5%-15% of the thickness of traditional indium gallium nitrogen, the pressure stress borne by indium gallium nitrogen is greatly reduced, and the crystal quality of the quantum well is improved. Moreover, after the indium gallium nitrogen grows for a short time, the ammonia gas and indium are kept for treatment, so that the nitrogen vacancy defect can be reduced, the decomposition of indium in the indium gallium nitrogen can be reduced, and the defects in a quantum well are reduced. According to the invention, the crystal quality of the quantum well is obviously improved, and the luminous efficiency of an LED under low current density is obviously improved.

The invention discloses a preparation method of a large-area and distance-adjustable gold nanoparticle single-layer superlattice film and a product and application thereof, and belongs to the technical field of nanomaterials, the method comprises the following steps: modifying the surfaces of gold nanoparticles by using sulfydryl polystyrene and 1, 8-octyldithiol to obtain double-ligand co-modified gold nanoparticles; an interface assembly strategy is adopted to enable the double-ligand co-modified gold nanoparticles to form a film at the interface of toluene and diethylene glycol, and after toluene volatilizes, the large-area gold nano single-layer superlattice film with the adjustable distance is obtained. According to the method disclosed by the invention, by accurately regulating and controlling double-ligand modification on the surfaces of the gold nanoparticles and optimizing interaction among the particles in the assembly process, accurate regulation and control of the particle spacing of the gold nanoparticle single-layer superlattice film from 1nm to 8nm are realized. The electromagnetic field intensity can be obviously enhanced by accurately regulating and controlling the particle gaps to the sub-nanometer scale, so that the material becomes an ideal SERS substrate, and possibility is provided for developing a metamaterial with a high optical index.

According to the hafnium oxide-based ferroelectric crystal phase modulation method based on the superlattice structure, each hafnium oxide layer in a hafnium oxide-based ferroelectric film is designed to be formed by stacking m hafnium oxide sub-layers, and each doped element layer is designed to be formed by stacking n doped element sub-layers; the hafnium oxide layer and the doping element layer are stacked to form a superlattice structure, and the hafnium oxide-based ferroelectric crystal phase is modulated as o phase dominant, t phase dominant or o / t mixed phase by determining the values of m and n, and the method is as follows: by volume, when the content of o phase is greater than 60%, o phase dominant, m is greater than or equal to 2 and less than or equal to 10, and n is 1.5 * m; when the content of the t phase is greater than 60%, the t phase is dominant, m is greater than or equal to 20 and less than or equal to 30, and n is equal to 2.5 * m; when the difference between the content of the o phase and the content of the t phase does not exceed 20%, the phase is an o / t mixed phase, m is more than 10 and less than 20, and n is equal to 2 * m; wherein m is an even number. According to the invention, the crystalline phase of the hafnium oxide-based ferroelectric film can be modulated, the electric leakage is extremely low, and the reliability is high.

The invention provides a short-wave infrared detector digital alloy material and a preparation process thereof. The preparation process comprises the following steps: growing a GaSb buffer layer on the surface of an n-type GaSb substrate; starting a first In furnace, and growing an InAs layer on the surface of the GaSb buffer layer in cooperation with an As beam; starting a second In furnace, and growing a quaternary solid solution layer matched with a GaSb buffer layer lattice on the surface of the InAs layer in cooperation with the Ga furnace and the AsSb beam; and alternately growing an InAs layer and a quaternary solid solution layer on the surface of the quaternary solid solution layer to generate a superlattice structure until the total thickness of the superlattice structure reaches a set target thickness, thereby obtaining the digital alloy material. According to the digital alloy material for the short-wave infrared detector and the preparation technology of the digital alloy material, the short-wave infrared detector can be expanded to the wave band ranging from 2.4 micrometers to 2.8 micrometers at the 50% cut-off wavelength.

The invention relates to the technical field of battery materials, in particular to a sodium-ion battery positive electrode material with a high-entropy superlattice structure and a preparation method of the sodium-ion battery positive electrode material, and the general formula of the sodium-ion battery positive electrode material is Na < 0.67 > MnaNibFecLidCueTifO2, a < lt >; 0.6, 0.1 lt; blt; 0.3, 0.01 lt, 0.01 lt, 0.01 lt; clt; ct; 0, 0.2, 0.03 lt; dlt; 0, 0.2, 0.03 lt; lt, lt; 0.2, 0.01 lt, 0.01 lt, 0.01 lt; flt; 0.2, a + b + c + d + e + f = 1; according to the invention, a plurality of ions with similar sizes are introduced into the sodium ion layered oxide transition metal layer, so that a short-range disordered honeycomb-shaped high-entropy superlattice structure is formed; by means of the hysteresis diffusion effect of the high-entropy material, the oxidation-reduction reaction of oxygen anions activated by lithium is effectively regulated and controlled, and the phenomena of voltage decline and structure degradation caused by the migration process of manganese ions in the transition metal layer are inhibited.

The invention provides an epitaxial wafer of a high-luminous-efficiency infrared light-emitting diode and a manufacturing method of the epitaxial wafer. The epitaxial wafer comprises a GaAs substrate, an N-type semiconductor structure, a quantum well active region and a P-type semiconductor structure, wherein the N-type semiconductor structure, the quantum well active region and the P-type semiconductor structure are formed on the substrate. The N-type semiconductor structure comprises an N-type AlGaAs stacking layer, diethyl tellurium (DETe) and disilane (Si2H6) are adopted for co-doping, the N-type semiconductor structure is designed to be of a superlattice structure, and the doping concentration in the vertical direction is periodically alternated from high to low; and a doping concentration gradient is arranged at a position close to the quantum well region, so that the tellurium doping concentration is gradually increased. Through the design, the content of carbon impurities in the material and the non-radiative recombination probability are reduced, a better current expansion effect and quantum well stress release are achieved, and the luminous efficiency and performance of an infrared LED are greatly improved.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

The invention discloses an epitaxial layer of a lattice transition type gallium nitride HEMT device and a manufacturing method of the epitaxial layer. The epitaxial layer comprises a substrate, and an AlN nucleating layer, an AlGaN buffer layer, a superlattice buffer layer, an AlGaN transition layer, a high-carbon GaN layer, a low-carbon GaN channel layer, an AlGaN barrier layer and a cap layer which are sequentially stacked on the surface of the substrate in the longitudinal direction. According to the invention, after the AlGaN transition layer is inserted between the superlattice buffer layer and the high-carbon GaN layer, the superlattice buffer layer with high aluminum content is firstly transited to the AlGaN transition layer with medium aluminum content and then transited to the high-carbon GaN layer without aluminum, so that lattice mismatch between layers is reduced, and deformation and warping of a wafer are reduced.

The invention relates to the technical field of semiconductor light-emitting devices, and particularly discloses an epitaxial structure for improving the internal quantum efficiency of a green Micro LED. The epitaxial structure comprises a substrate, and a buffer layer, an undoped GaN layer, an n-type GaN layer, a stress release layer, an active layer, a low-temperature Mg heavily-doped GaN layer, an electron barrier layer, a p-type GaN layer and a p-type GaN contact layer which are sequentially arranged on the substrate. The active layer comprises a plurality of periods of InGaN quantum well layers and an InAlGaN / GaN superlattice quantum barrier layer alternating structure, and a CAP layer formed by an AlGaN / GaN superlattice is arranged behind each quantum well layer. By adopting a wide-well narrow-barrier structure, a superlattice CAP layer for neutralizing a polarization electric field and a quaternary InAlGaN barrier structure for lattice matching and hole injection enhancement, multiple regulation and control of a polarization field, dislocation density and hole transport are realized, the internal quantum efficiency of a green-light Micro LED is remarkably improved, and the green-light Micro LED epitaxial structure is suitable for epitaxial preparation of a high-performance Micro LED chip.

A nitride semiconductor device includes a nitride semiconductor layer including a first superlattice buffer layer, a second superlattice buffer layer formed above the first superlattice buffer layer, an electron transit layer formed above the second superlattice buffer layer and composed of a first nitride semiconductor, and an electron supply layer formed above the electron transit layer and composed of a second nitride semiconductor. The first superlattice buffer layer has a first superlattice structure including a first layer and a second layer alternately arranged. The first layer is composed of AlxGa1−xN, where 0<x<1. The second layer is composed of GaN. The second superlattice buffer layer has a second superlattice structure including a third layer and a fourth layer alternately arranged. The third layer is composed of AlyGa1−yN, where 0<y<x. The fourth layer is composed of GaN.

The invention discloses a Micro-LED epitaxial wafer, a preparation method of the Micro-LED epitaxial wafer and a Micro-LED, and relates to the field of semiconductor photoelectric devices. The Micro-LED epitaxial wafer sequentially comprises a substrate, a buffer layer, a first warping regulation and control layer, a non-doped GaN layer, a second warping regulation and control layer, an N-type GaN layer, a third warping regulation and control layer, a multi-quantum well layer and a P-type GaN layer. The first warping regulation and control layer is a three-dimensional GaN layer, the second warping regulation and control layer comprises a first Si-doped GaN layer and a Si-doped AlGaN layer which are alternately stacked, the third warping regulation and control layer comprises a Si-doped AlInGaN layer and a superlattice layer which are sequentially stacked on the N-type GaN layer, and the superlattice layer comprises a second Si-doped GaN layer and an InGaN layer which are alternately stacked. By implementing the invention, the luminous efficiency and wavelength uniformity of the Micro-LED can be improved.

The invention provides a preparation method of a novel second-class superlattice infrared detector, and belongs to the field of infrared detectors. The problems that an inorganic film layer of an existing II-type superlattice infrared detector usually contains large stress and cracks are prone to occurring are solved. Comprising the following steps: depositing an inorganic mask layer on an epitaxial layer; coating photoresist on the inorganic mask layer, and developing to form patterned photoresist; performing etching on the inorganic mask layer to form a through hole structure; forming a mesa patterning photoresist above the inorganic mask layer of the through hole structure; forming a mesa pattern on the inorganic mask layer of the through hole structure; etching the epitaxial layer, and forming a patterned epitaxial layer below the inorganic mask layer of the through hole structure; depositing an inorganic passivation layer; photoetching trepanning or etching trepanning is carried out on the table top, and the inorganic mask layer and the inorganic passivation layer of the through hole structure are etched; the method is used for preparing the infrared detector.

The invention belongs to the technical field of two-dimensional material preparation, and particularly relates to a two-dimensional fullerene covalent network, an electrochemical synthesis method and a photoelectric detector. The method comprises the following steps: by taking a fullerene superlattice material as a cathode, an inert material as an anode and a mixed solution of quaternary ammonium salt containing hydrogen protons and a polar aprotic solvent as an electrolyte solution, performing electrochemical stripping under constant potential to obtain a large batch of two-dimensional fullerene networks within a short time. Based on intercalation and expansion of layered fullerene superlattices, in combination with an in-situ reduction assisting effect of solvated protons at the edge of Mg4C60 crystals, quaternary ammonium salt cations are electrically driven to perform rapid intercalation expansion, generated hydrogen bubbles destroy relatively strong interaction force between layers, rapid and uniform intercalation of the quaternary ammonium salt cations between the layers is promoted, and the performance of the Mg4C60 crystal is improved. The stripping efficiency is as high as 83%, the single-layer stripping rate is as high as 30%, and the stripped two-dimensional C60 covalent network keeps a complete crystal structure and a large size.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

The invention belongs to the field of reconfigurable on-chip spectrometers, and particularly discloses a reconfigurable on-chip spectrometer based on a low-loss GST superlattice phase change material. According to the invention, the GST-SL2 material is combined with the double-cascade micro-ring array architecture, so that the performance of the device is improved in a breakthrough manner, a large amount of spectral response can be generated only through a limited number of micro-ring resonators on a chip, the flexible regulation and control of the spectral resolution and the working bandwidth are supported, and the customization requirements of different application scenes are met; a resolution regulation and control array is formed by cascading # imgabs0 first MRRs which are arranged at equal intervals in the extension direction of a bus waveguide, the lengths of resonance micro-rings of the first MRRs are increased progressively, and due to the cascading design, through the synergistic effect of the multiple MRRs, the overall regulation and control capacity is remarkably enhanced, and it is ensured that sampling points can uniformly cover the whole working bandwidth of an on-chip spectrometer; the measurement bandwidth regulation and control array divides the working bandwidth into a plurality of channels, the irrelevance of a system response function is successfully enhanced, and a reliable basis is provided for spectrum reconstruction.

A sodium battery precursor, and a preparation method therefor and the use thereof. The preparation method comprises the following steps: (1) mixing a nickel salt, a manganese salt and an iron salt with a solvent to obtain a solution A, mixing a copper salt, a complexing agent and a solvent to obtain a solution B, and mixing one or more of a lithium salt, a zinc salt, a titanium salt or a magnesium salt with a solvent to obtain a solution C; (2) injecting an alkali liquor, ammonia water and the solution A into a base solution in parallel flow for a first-step co-precipitation reaction, and injecting ammonia water, the alkali liquor and the solution B in parallel flow for a second-step co-precipitation reaction; and (3) injecting a precipitant solution and the solution C in parallel flow for a third-step co-precipitation reaction, thereby obtaining the sodium battery precursor. A high-entropy superlattice sodium battery precursor is prepared by means of step-by-step co-precipitation, and the sodium battery precursor enables the improvement of the sodium-ion intercalation and de-intercalation capability of the precursor while reducing the material cost, thereby improving the capacity retention ratio and cycling performance of the material.

The present invention relates to the field of optoelectronics, and discloses a light-emitting diode epitaxial wafer, a method for manufacturing the same, and an LED. The light-emitting diode epitaxial wafer comprises a substrate, on which a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially provided; the electron blocking layer comprises a BAlN / P-GaN superlattice layer, an AlGaN / P-InGaN superlattice layer, and a BN layer stacked in sequence. The light-emitting diode epitaxial wafer provided by the present invention reduces electron overflow, improves hole injection efficiency, replenishes hole concentration, and enhances the luminous efficiency of the light-emitting diode.