1465results about How to "Low mobility" patented technology

A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

A thin-film transistor including an oxide semiconductor layer is disclosed. The oxide semiconductor layer includes a first area, a second area and a third area forming a well-type potential in the film-thickness direction. The first area forms a well of the well-type potential and has a first electron affinity. The second area is disposed nearer to the gate electrode than the first area and has a second electron affinity smaller than the first electron affinity. The third area is disposed farther from the gate electrode than the first area and has a third electron affinity smaller than the first electron affinity. At least an oxygen concentration at the third area is lower than an oxygen concentration at the first area.

External power source, charger, system and method for an implantable medical device having therapeutic componentry and a secondary coil operatively coupled to the therapeutic componentry. A primary charging coil is capable of transcutaneously inductively energizing the secondary coil when externally placed in proximity of the secondary coil. Drive circuitry is operatively coupled to the primary charging coil for exciting the primary charging coil. A rechargeable power source is operatively coupled to the drive circuitry. A secondary recharging coil is operatively coupled to the rechargeable power source. A primary recharging coil is adapted to be coupled to a source of AC power which when placed in proximity of the secondary recharging coil can inductively energize the secondary recharging coil in order to charge the rechargeable power source.

The present invention relates to a remote control (107; 201; 301) for controlling at least one device (101, 102, 103; 302) with connectivity to a service delivery network (105, 106). The remote control (107; 201; 301) comprising one or more displays (202) for showing display items which are indicative for one or more control instructions and the remote control (107; 201; 301) is able to adapt the display items and/or the control instructions in real-time depending on a selected service (303).

Thin film transistors including an oxide semiconductor containing indium, gallium, and zinc are easily arranged in a matrix over a large substrate and have small characteristic variations. With amplifier circuits and driver circuits of display elements which include the thin film transistors including an oxide semiconductor containing indium, gallium, and zinc with small characteristic variations, intensity distribution of light received by the photodiodes arranged in a matrix is converted into electrical signals with high reproducibility and output, and the display elements arranged in a matrix can be uniformly driven.

A structural reinforcement for a hollow member comprising a rigid reinforcing member having a shape that substantially conforms to the cross section of the hollow member to be reinforced with an expandable adhesive material over at least a portion of the surface of the structural reinforcement having one or more extensions on its external surface which control and direct the direction in which the adhesive material expands to bond the reinforcing member to the internal surface of the hollow member, some of the extensions also provide improved reinforcement.

The present invention provides orthotic devices for use in managing the treatment and prevention of lower extremity injuries, including foot ulcers. In various aspects, the present invention provides foot-worn orthotics which provide for improved compliance monitoring, and methods of their manufacture and use.

An implant for the correction and stabilization of the spinal column, comprising pedicle screws that can be screwed into the vertebrae of a spine, and of at least one connection element that connects the pedicle screws at the screw heads. This connection element is formed by a spiral whose spiral windings are arranged offset in the axial direction, following a screw line.

A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

The present invention provides a device structure and method of forming a finFet device having stacked fins. The method of the present invention comprises: providing a substrate with a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; forming a first fin and a second fin in the second semiconductor layer; masking the first fin; and forming a third fin in the first semiconductor layer, where the second fin is stacked on the third fin. The structure of the present invention comprises: a semiconductor substrate having a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; a first and second fin formed in the second semiconductor layer; and a third fin formed in the first semiconductor layer, where the second fin is stacked on the third fin.

Light emitting devices include an active region comprising a plurality of layers and a pit opening region on which the active region is disposed. The pit opening region is configured to expand a size of openings of a plurality of pits to a size sufficient for the plurality of layers of the active region to extend into the pits. In some embodiments, the active region comprises a plurality of quantum wells. The pit opening region may comprise a superlattice structure. The pits may surround their corresponding dislocations and the plurality of layers may extend to the respective dislocations. At least one of the pits of the plurality of pits may originate in a layer disposed between the pit opening layer and a substrate on which the pit opening layer is provided. The active region may be a Group III nitride based active region. Methods of fabricating such devices are also provided.

A halogen-free resin composition includes (A) 100 parts per hundred resin of epoxy resin; (B) 1 to 100 parts per hundred resin of benzoxazine resin; (C) 1 to 100 parts per hundred resin of styrene-maleic anhydride; (D) 0.5 to 30 parts per hundred resin of amine curing agent; and (E) 5 to 150 parts per hundred resin of halogen-free flame retardant. The composition obtains properties of low dielectric constant, low dissipation factor, high heat resistance and flame retardancy by specific composition and ratio. Thus, a prepreg or a resin film, which can be applied to a copper clad laminate and a printed circuit board, is formed.

An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also provided. The PMOS transistor has a second fin-shaped active region that extends in the semiconductor substrate. This second fin-shaped active region has a second channel region therein with a second height unequal to the first height.

Assays for detecting molecular modifications such as phosphate modifications and the presence and/or activity of enzymes and other agents involved in facilitating or otherwise regulating such modifications.

Methods for forming a tunnel oxide structure device and methods for forming the structure are described. A structure comprising nitrogen is formed on a semiconductor substrate. The structure is oxidized. Nitrogen of the oxide structure is redistributed to form a region of concentrated nitrogen. Oxidizing the structure and redistributing the nitrogen is performed via radical oxidation. Nitrogen is added to the oxide structure. The region of concentrated nitrogen helps to regulate the depth of the added nitrogen.

An electrochemical cell including at least one nitrogen-containing compound is disclosed. The at least one nitrogen-containing compound may form part of or be included in: an anode structure, a cathode structure, an electrolyte and/or a separator of the electrochemical cell. Also disclosed is a battery including the electrochemical cell.

A fixing device is disclosed for at least one operating element or fixing element suitable for application in sterile areas in surgical operations, which is largely freely positioned in three dimensions and supported for fixing, while the sterile area is separated from the non-sterile area substantially by a sheet-like covering. A holding device is provided which is located in the non-sterile area and which, while being at least separated by the covering, enters into an operative connection via an active surface with the operating or fixing element, with the operative connection being based on magnetic forces.

A field effect transistor including a semiconductor layer including a composite oxide which contains In, Zn, and one or more elements X selected from the group consisting of Zr, Hf, Ge, Si, Ti, Mn, W, Mo, V, Cu, Ni, Co, Fe, Cr, Nb, Al, B, Sc, Y and lanthanoids in the following atomic ratios (1) to (3):

In/(In+Zn)=0.2 to 0.8  (1)

In/(In+X)=0.29 to 0.99  (2)

Zn/(X+Zn)=0.29 to 0.99  (3).

The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.

A high electron mobility transistor is disclosed which has a main semiconductor region formed on a silicon substrate. The main semiconductor region is a lamination of a buffer layer on the substrate, an electron transit layer on the buffer layer, and an electron supply layer on the electron transit layer. A source, drain, and gate overlie the electron supply layer. Also formed on the electron supply layer is a surface-stabilizing organic semiconductor overlay which is of p conductivity type in contrast to the n type of the electron supply layer.