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162results about How to "Improve pressure resistance" patented technology

Vacuum switch tube

The invention provides a vacuum switch tube comprising an insulated case, an upper end cover, a lower end cover, a fixed conductive base, a first movable conducting rod and a second movable conducting rod, wherein the upper end cover is hermetically arranged at the upper end of the insulated case; the lower end cover is hermetically arranged at the lower end of the insulated case; the fixed conductive base comprises at least one joint and is fixedly arranged in the insulated case; the joints penetrate through the insulated case; the fixed conductive base is electrically and fixedly connected with a first fixed contact and a second fixed contact respectively; the first movable conducting rod penetrates through the upper end cover and first corrugated pipes connected with the inner sides of the upper end cover and is electrically and fixedly connected with a first movable contact arranged in a first vacuum chamber; and the second movable conducting rod penetrates through the lower end cover and second corrugated pipes connected with the inner sides of the lower end cover and is electrically and fixedly connected with a second movable contact arranged in a second vacuum chamber. The vacuum switch tube provided by the invention can realize three positions, thus improving the versatility.
Owner:BEIJING BOE VACUUM ELECTRONICS CO LTD

Non-contact protection ring single-photon avalanche diode and preparation method thereof

The invention discloses a non-contact protection ring single-photon avalanche diode and a preparation method thereof. The non-contact protection ring single-photon avalanche diode is composed of a light-sensitive PN junction formed by a P+/deep N well, and an annular P well protection ring. The light-sensitive PN junction and the annular P well protection ring are spaced apart at a certain distance. A protection ring is formed by means of the P well around the light-sensitive PN junction to inhibit the edge breakdown phenomenon. The P well protection ring plays the role of a voltage divider, and the increase of an edge electric field of a light-sensitive region is inhibited. Through the standard CMOS process, a lightly-doped deep N-well is formed on a P-type lightly-doped silicon substrate, so that the electrical isolation with other electronic devices is achieved. The mutual influence between devices is avoided. A cathode, an anode and a contact through hole are etched out, and then alayer of aluminum film is deposited. After that, an electrode pattern is formed through the photoetching process. A high-layer interconnection metal is prepared through photoetching, etching and metallization processes. The metal is used for leading an electrical signal of the SPAD to a contact pad. A silicon oxide/silicon nitride passivation layer is sequentially deposited on the upper surface of a chip. Therefore, the scratch of the chip and the influence of the external environment can be avoided.
Owner:TIANJIN UNIV

High-voltage-resistant and high-energy-density capacitor and preparation method thereof

The invention relates to a high-voltage-resistant and high-energy-density capacitor and a preparation method thereof. The high-voltage-resistant and high-energy-density capacitor comprises a substrate, a bottom electrode, a dielectric layer and a top electrode, wherein Si or SiO2/Si is taken as the substrate; the bottom electrode is a metal film, a conductive oxide film or a combination of both; the dielectric layer consists of a BaTiO3 ferroelectric film; and the top electrode is a metal film point electrode. A metal target or/and conductive oxide target is adopted, and a single target is used for depositing a metal film or a conductive oxide film, or depositing the meal film and the conductive oxide film in sequence on the substrate in a radio-frequency or direct current magnetron sputtering way; a ceramic BaTiO3 target is adopted, and a BaTiO3 layer is deposited on the bottom electrode in a radio-frequency magnetron sputtering way; and a metal target is adopted, and the top electrode is deposited in a radio-frequency magnetron sputtering way. The film capacitor prepared with the method has the advantages of small size, high voltage resistance and breakdown field strength Eb of higher than 1000kV/cm; the practical discharging energy density is not less than 10J/cm<3>; and the loss is low, and the dielectric performance is kept stable when the frequency and temperature change.
Owner:欧阳俊

Composite material, preparation method of composite material, and lithium ion battery comprising composite material

ActiveCN104078659AImprove pressure resistanceImprove safety performance and stability performanceCell electrodesSecondary cellsCoprecipitationCyclic stability
The invention discloses a composite material, a preparation method of the composite material, and a lithium ion battery comprising the composite material, and belongs to the field of lithium ion battery materials. The composite material is in a core-shell structure. A shell layer of the composite material comprises a middle layer and an outer layer coated outside the middle layer. An inner core of the composite material is Li(NixCoyAlz)O2; the middle layer is Li(Ni1/3Co1/3Mn1/3)O2; the outer layer is LiNi0.5Mn1.5O4; and a molar ratio of the inner core to the middle layer to the outer layer of the composite material is a:b:c, wherein a+b+c=1, b is greater than 0 and less than 0.5, c is greater than 0 and less than 0.5, x+y+z=1, y=0.15, and z is greater than or equal to 0.03 and is less than or equal to 0.05. The composite material has the characteristics of comparatively high capacity, low alkalinity and electrolyte resistance, has good cycling stability and safety performance, has an obvious cost performance advantage, and is more suitable for application of a power battery. Structural precursors of the layers of the composite material are sequentially formed by utilizing a coprecipitation synthesis technology, so that good consistency and good homogeneity are achieved and the layers are tightly connected with each other. Besides, the composite material can be obtained by a single roasting process; and the cost can be lowered effectively.
Owner:NEC (CHINA) CO LTD

Diode chip and processing technology thereof

ActiveCN102244045AImprove pressure resistanceAvoid circuit failureSemiconductor/solid-state device detailsSolid-state devicesHorizontal projectionIon
The invention provides a diode chip and a processing technology thereof, relating to a semiconductor discrete device and a processing technology thereof. The invention can overcome discharge in detection and creepage phenomenon in use. A circle of glassy protective layer is arranged at the edge of a chip, the horizontal projection of the chip is of a closed shape with no corner; the side edge is provided with a circle of semi-insulating polycrystalline silicon (SIPOS) film; and the glassy protective layer covers 70-95% of the upper part of the SIPOS film. The processing technology provided bythe invention comprises the following steps: 1) graving a wafer split pattern; 2) passivating the SIPOS film; 3) processing the glassy protective layer; 4) photoengraving three times; 5) cleaning; 6)removing photoresist; 7) splitting to obtain the chip. By the adoption of the invention, the point discharge of a square chip can be effectively prevented and the withstand voltage capacity of a diode can be improved. Before passivation with glass, passivation with an SIPOS film is carried out to absorb movable ions on the surface of the chip, thus the stability can be enhanced and the withstand voltage capacity can be improved; meanwhile, the bottoms of grooves still remains the SIPOS film and an SIO2 film, thus preventing Au layer adhesion in Au evaporation.
Owner:扬州杰利半导体有限公司

Gallium-nitride-based power heterojunction field effect transistor with local back barrier

The invention discloses a gallium-nitride-based power heterojunction field effect transistor with a local back barrier. The gallium-nitride-based power heterojunction field effect transistor is structurally composed of a substrate, an aluminum nitride nucleation buffering layer, an aluminum indium gallium nitride local back barrier layer, a gallium nitride channel layer and an aluminum indium gallium nitride barrier layer mainly from bottom to top, a source electrode, a drain electrode and a grid electrode are formed on the barrier layer, the source electrode and the drain electrode forms ohmic contact with the barrier layer, and the grid electrode forms schottky contact with the barrier layer. By introducing the aluminum indium gallium nitride local barrier layer with polarization intensity larger than the polarization intensity of the gallium nitride channel layer, negative polarization charges are left after interface charges of the aluminum indium gallium nitride barrier layer and the gallium nitride channel layer are balanced, effect of exhausting part of 2DEG of a grid-drain drift region channel is realized, and an LDD (low density drain) structure is formed, so that modulating of electric field distribution of the channel is realized to improve voltage resistance of a device.
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

LDMOS and manufacturing method thereof

The present invention relates to a LDMOS (Lateral Double-diffused metal oxide semiconductor) and a manufacturing method thereof. A first buried layer with an impurity total amount gradually decreasedfrom left to right is injected and formed on a substrate, in the later diffusion process, the left side of the first buried layer is diffused towards the upper portion of an epitaxial layer due to theimpurities, the effective junction depth of the left side of the epitaxial layer becomes shallow, N-type impurities are decreased, when reverse bias is applied between the source and the drain of theLDMOS, the epitaxial layer region at the left side is easily exhausted, the exhaust line in the epitaxial layer region is rapidly extended towards the right with the increasing of the reversed bias voltage so as to have an effect on reduction of a peak electric field of the region, the junction depth of the region at right side of the first buried layer becomes shallow, P-type impurities are gradually decreased, the exhaust line of the P-type region can be rapidly extended towards a substrate region with a relative light concentration so as to rapidly reduce the electric field intensity of the drift region, improve the voltage endurance capability of the drift region and allow the device not to be untimely broken down in a vertical direction.
Owner:SHENZHEN NANSHUO MINGTAI TECH CO LTD
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