41473 results about "Crystal" patented technology

A laminated structure comprises a first layer comprising a crystal with six-fold symmetry, and a second layer comprising a metal oxynitride crystal formed on the first layer, wherein the second layer comprises at least one element selected from the group consisting of In, Ga, Si, Ge and Al, N, O and Zn, as main elements, and wherein the second layer has in-plane orientation.

An ultraviolet laser apparatus having a single-wavelength oscillating laser generating laser light between an infrared band and a visible band, an optical amplifier for amplifying the laser light, and a wavelength converting portion converting the amplified laser light into ultraviolet light using a non-linear optical crystal. An exposure apparatus transfers a pattern image of a mask onto a substrate and includes a light source having a laser apparatus emitting laser light having a single wavelength, a first fiber optical amplifier for amplifying the laser light, a light dividing device for dividing or branching the amplified laser light into plural lights, and second fiber optical amplifiers for amplifying the plural divided or branched lights, respectively, and a transmission optical system for transmitting the laser light emitted from the light source to the exposure apparatus.

PCT No. PCT/JP98/01640 Sec. 371 Date Dec. 9, 1998 Sec. 102(e) Date Dec. 9, 1998 PCT Filed Apr. 9, 1998 PCT Pub. No. WO98/47170 PCT Pub. Date Oct. 22, 1998A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

A programmable metallization cell ("PMC") comprises a fast ion conductor such as a chalcogenide-metal ion and a plurality of electrodes (e.g., an anode and a cathode) disposed at the surface of the fast ion conductor and spaced a set distance apart from each other. Preferably, the fast ion conductor comprises a chalcogenide with Group IB or Group IIB metals, the anode comprises silver, and the cathode comprises aluminum or other conductor. When a voltage is applied to the anode and the cathode, a non-volatile metal dendrite grows from the cathode along the surface of the fast ion conductor towards the anode. The growth rate of the dendrite is a function of the applied voltage and time. The growth of the dendrite may be stopped by removing the voltage and the dendrite may be retracted by reversing the voltage polarity at the anode and cathode. Changes in the length of the dendrite affect the resistance and capacitance of the PMC. The PMC may be incorporated into a variety of technologies such as memory devices, programmable resistor/capacitor devices, optical devices, sensors, and the like. Electrodes additional to the cathode and anode can be provided to serve as outputs or additional outputs of the devices in sensing electrical characteristics which are dependent upon the extent of the dendrite.

A water soluble semiconductor nanocrystal capable of light emission is provided, including a quantum dot having a selected band gap energy, a layer overcoating the quantum dot, the overcoating layer comprised of a material having a band gap energy greater than that of the quantum dot, and an organic outer layer, the organic layer comprising a compound having a least one linking group for attachment of the compound to the overcoating layer and at least one hydrophilic group space apart from the linking group by a hydrophobic region sufficient to prevent electron charge transfer across the hydrophobic region. The particle size of the nanocrystal core is in the range of about 12.ANG. to about 150.ANG., with a deviation of less than 10% in the core. The coated nanocrystal exhibits photoluminescende having quantum yield of greater than 10% in water.

A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide semiconductor film may lead to high contact resistance. One cause of high contact resistance is that a Schottky junction is formed at a contact plane between the source and drain electrodes and the oxide semiconductor film. An oxygen-deficient oxide semiconductor layer which includes crystal grains with a size of 1 nm to 10 nm and has a higher carrier concentration than the oxide semiconductor film serving as a channel formation region is provided between the oxide semiconductor film and the source and drain electrodes.

An oxide semiconductor film which has more stable electric conductivity is provided. Further, a semiconductor device which has stable electric characteristics and high reliability is provided by using the oxide semiconductor film. An oxide semiconductor film includes a crystalline region, and the crystalline region includes a crystal in which an a-b plane is substantially parallel with a surface of the film and a c-axis is substantially perpendicular to the surface of the film; the oxide semiconductor film has stable electric conductivity and is more electrically stable with respect to irradiation with visible light, ultraviolet light, and the like. By using such an oxide semiconductor film for a transistor, a highly reliable semiconductor device having stable electric characteristics can be provided.

A semiconductor light emitting device includes a crystal layer formed on a substrate, the crystal layer having a tilt crystal plane tilted from the principal plane of the substrate, and a first conductive type layer, an active layer, and a second conductive type layer, which are formed on the crystal layer in such a manner as to extend within planes parallel to the tilt crystal plane, wherein the device has a shape formed by removing the apex and its vicinity of the stacked layer structure formed on the substrate. Such a semiconductor light emitting device is excellent in luminous efficiency even if the device has a three-dimensional device structure. The present invention also provides a method of fabricating the above semiconductor light emitting device.

An inventive system and method de-passivates a direct current (DC) power source of an Automatic External Defibrillator (AED), such as an AED lithium battery. The system includes a main processor and standby processor. The standby processor monitors the age and usage of the battery. Based on the status of the monitored parameters, the system executes a conditioning discharge to remove a layer of salt crystals on the DC power source.

An apparatus and packaging method for stacking a plurality of integrated circuit substrates, i.e., substrates having integrated circuits formed as integral portions of the substrates, which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantabie device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

A nanostructured composite material comprising semiconductor nanocrystals in a crystalline semiconductor matrix. Suitable nanocrystals include silicon, germanium, and silicon-germanium alloys, and lead salts such as PbS, PbSe, and PbTe. Suitable crystalline semiconductor matrix materials include Si and silicon-germanium alloys. A process for making the nanostructured composite materials. Devices comprising nanostructured composite materials.

Matrixes doped with semiconductor nanocrystals are provided. In certain embodiments, the semiconductor nanocrystals have a size and composition such that they absorb or emit light at particular wavelengths. The nanocrystals can comprise ligands that allow for mixing with various matrix materials, including polymers, such that a minimal portion of light is scattered by the matrixes. The matrixes of the present invention can also be utilized in refractive index matching applications. In other embodiments, semiconductor nanocrystals are embedded within matrixes to form a nanocrystal density gradient, thereby creating an effective refractive index gradient. The matrixes of the present invention can also be used as filters and antireflective coatings on optical devices and as down-converting layers. Processes for producing matrixes comprising semiconductor nanocrystals are also provided. Nanostructures having high quantum efficiency, small size, and/or a narrow size distribution are also described, as are methods of producing indium phosphide nanostructures and core-shell nanostructures with Group II-VI shells.

A substrate (10) has at least one recess (20) and/or protrusion (21) formed on the surface thereof so as to scatter or diffract the light generated in an active layer (12). The recess and/or protrusion is formed in such a shape that can reduce crystalline defect in semiconductor layers (11, 13).

Disclosed are Bacillus thuringiensis strains comprising novel crystal proteins which exhibit insecticidal activity against coleopteran insects including red flour beetle larvae (Tribolium castaneum) and Japanese beetle larvae (Popillia japonica). Also disclosed are novel B. thuringiensis crystal toxin genes, designated cryET33 and cryET34, which encode the colepteran-toxic crystal proteins, CryET33 (29-kDa) crystal protein, and the cryET34 gene encodes the 14-kDa CryET34 crystal protein. The CryET33 and CryET34 crystal proteins are toxic to red flour beetle larvae and Japanese beetle larvae. Also disclosed are methods of making and using transgenic cells comprising the novel nucleic acid sequences of the invention.

A capture device for remote, virtual on screen data input by hand annotation comprises at least three functional layers including a bottom rigid layer, a middle pressure sensor layer and a top flexible layer. The bottom rigid layer has a surface that provides a mechanical support for writing. The middle pressure sensor layer is adapted to measuring a pressure array or map on the capture active area and to send data representing the measured pressure to a personal computer. The top flexible touch-sensitive passive LCD display layer includes an LCD surface by which whatever is written down on the LCD is impressed graphically due to its liquid crystal physical properties wherein applied pressure changes the crystal particles orientation and light properties, such that when a stylus presses against a writing surface thereof, it leaves a visible trace allowing the user to produce a drawing though no real ink has flown.

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

Disclosed herein is a system for rapidly resolving position with centimeter-level accuracy for a mobile or stationary receiver [4]. This is achieved by estimating a set of parameters that are related to the integer cycle ambiguities which arise in tracking the carrier phase of satellite downlinks [5,6]. In the preferred embodiment, the technique involves a navigation receiver [4] simultaneously tracking transmissions [6] from Low Earth Orbit Satellites (LEOS) [2] together with transmissions [5] from GPS navigation satellites [1]. The rapid change in the line-of-sight vectors from the receiver [4] to the LEO signal sources [2], due to the orbital motion of the LEOS, enables the resolution with integrity of the integer cycle ambiguities of the GPS signals [5] as well as parameters related to the integer cycle ambiguity on the LEOS signals [6]. These parameters, once identified, enable real-time centimeter-level positioning of the receiver [4]. In order to achieve high-precision position estimates without the use of specialized electronics such as atomic clocks, the technique accounts for instabilities in the crystal oscillators driving the satellite transmitters, as well as those in the reference [3] and user [4] receivers. In addition, the algorithm accommodates as well as to LEOS that receive signals from ground-based transmitters, then re-transmit frequency-converted signals to the ground.

A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include a gate electrode formed on a substrate; an active layer made of an oxide semiconductor and insulated from the gate electrode by a gate insulating layer; source and drain electrodes coupled to the active layer; and an interfacial stability layer formed on one or both surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristic as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 μm/cm², wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

A photonic crystal optical switch having a periodic dielectric structure including at least one input waveguide. First and second waveguide arms branch from the input waveguide in which the relative optical path lengths of electromagnetic radiation within the arms are controlled by stimuli. At least one output waveguide that combines the electromagnetic radiation propagating within the first and second waveguide arms.

An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about −2 degrees to about 2 degrees towards (000-1) and less than about 0.5 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. A first cleaved c-face facet is provided on one end of the laser stripe region, and a second cleaved c-face facet is provided on the other end of the laser stripe region.

A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

An optoelectronic device grown on a miscut of GaN, wherein the miscut comprises a semi-polar GaN crystal plane (of the GaN) miscut x degrees from an m-plane of the GaN and in a c-direction of the GaN, where −15<x<−1 and 1<x<15 degrees.

This semiconductor light emitting device includes an optical cavity made of a group III nitride semiconductor having a major growth surface defined by a nonpolar plane and including a pair of cavity end faces parallel to c-planes, and a reflecting portion made of a group III nitride semiconductor having a major growth surface defined by a nonpolar plane and having a reflective facet opposed to one of the pair of cavity end faces and inclined with respect to a normal of the major growth surface. The optical cavity and the reflecting portion may be crystal-grown from the major surface of the substrate. The substrate is preferably a group III nitride semiconductor substrate having a major surface defined by a nonpolar plane.

An optical device, e.g., LED, laser. The device includes a non-polar gallium nitride substrate member having a slightly off-axis non-polar oriented crystalline surface plane. In a specific embodiment, the slightly off-axis non-polar oriented crystalline surface plane is up to about −0.6 degrees in a c-plane direction, but can be others. In a specific embodiment, the present invention provides a gallium nitride containing epitaxial layer formed overlying the slightly off-axis non-polar oriented crystalline surface plane. In a specific embodiment, the device includes a surface region overlying the gallium nitride epitaxial layer that is substantially free of hillocks.

An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

A photovoltaic device comprising a photovoltaic cell is provided. The photovoltaic cell includes an emitter layer comprising a crystalline semiconductor material and a lightly doped crystalline substrate disposed adjacent the emitter layer. The lightly doped crystalline substrate and the emitter layer are oppositely doped. Further, the photovoltaic device includes a back surface passivated structure coupled to the photovoltaic cell. The structure includes a highly doped back surface field layer disposed adjacent the lightly doped crystalline substrate. The highly doped back surface field layer includes an amorphous or a microcrystalline semiconductor material, wherein the highly doped back surface field layer and the lightly doped crystalline substrate are similarly doped, and wherein a doping level of the highly doped back surface field layer is higher than a doping level of the lightly doped crystalline substrate. Additionally, the structure may also include an intrinsic back surface passivated layer disposed adjacent the lightly doped crystalline substrate, where the intrinsic back surface passivated layer includes an amorphous or a microcrystalline semiconductor material.

An optoelectronic device, comprising an active region and a waveguide structure to provide optical confinement of light emitted from the active region; a pair of facets on opposite ends of the device, having opposite surface polarity; and one of the facets which has been roughened by a crystallographic chemical etching process, wherein the device is a nonpolar or semipolar (Ga,In,Al,B)N based device.