32 results about "3d integrated circuit" patented technology

A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

A vertically stacked 3D integrated circuit structure includes at least two chiplets: a first chiplet formed from a non-diamond semiconductor material, a second chiplet formed from diamond. The diamond chiplet is positioned vertically relative to the first chiplet and is electrically coupled thereto. Thermal vias are formed through one or more of the non-diamond chiplets and include material to form heat extraction pathways. These thermal vias are thermally coupled to a heat-spreading structure, which may include the diamond chiplet, a diamond interposer, or an encapsulating diamond-based packaging layer.

An integrated circuit package is provided in which a hybrid-bonded stack of memory dies couples through a plurality of through-mold vias to a redistribution layer. A logic die couples to the redistribution layer through a plurality of interconnects.

Methods of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors is on top of the first level; providing placement data of the second level; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; performing a routing of the first level using a router {part of the CAD tool or another CAD tool) executed by a computer, where at least one metal routing layer is disposed in-between the first transistors and the second transistors, and the second level includes repeating structures.

An integrated circuit package is provided in which a hybrid-bonded stack of memory dies couples through a plurality of through-mold vias to a redistribution layer. A logic die couples to the redistribution layer through a plurality of interconnects.

In an aspect there is provided a 3D IC device comprising: a package wiring plane comprising a global VDD voltage node and a global VSS voltage node; a die stack arranged over the package wiring plane and comprising a number of stacked dies stacked on top of each other; a metal interconnect layer arranged on top of a top stacked die of the die stack; and a pass-through interconnect extending vertically through each stacked die of the die stack and connecting the metal interconnect layer to the global VDD voltage node; wherein each stacked die of the die stack has a bottom side and a top side, a local VDD voltage contact on its top side and a local VSS voltage contact on its bottom side.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die transmits a test pattern to the second circuit die via the interconnect layer. Then, the second circuit die determines that a first interconnect has failed based on the test pattern and generates a signature. Finally, the second circuit die uses signatures to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

An apparatus of a ferromagnetic transformer in a 3D integrated circuit is described, which comprises a plurality of semiconductor chips stacked within the 3D integrated circuit. An individual semiconductor chip of the plurality of semiconductor chips comprises a substrate, a plurality of dielectric layers, and a plurality of metal layers in the plurality of dielectric layers. In at least one example, the apparatus comprises one or more ferromagnetic through silicon vias vertically positioned through the individual semiconductor chip.

A package substrate according to the present disclosure includes a package substrate, an interposer disposed over the package substrate, a photonic die disposed over the interposer, a memory structure disposed over the interposer and including a controller die, a system die disposed over the interposer and partially overlapping with the photonic die and the controller die, and a lid covering the system die, the memory structure, and photonic die. The system die includes micro bumps extending from a bottom surface of the system die to a top surface of the controller die.

A device includes a first device tier including a first set of active devices and a second device tier including a second set of active devices. The device also includes a clocked circuit including first active devices of the first set of active devices, and a clock distribution network including a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device also includes a set of active clock devices formed by second active devices of the second set of active devices. The clocked circuit is connected to the clock distribution network to receive a clock signal.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5 D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die emits a test pattern to the second circuit die via the interconnect layer. The second circuit die then determines, based on the test pattern, that a first interconnect has failed and generates a signature. Finally, the second circuit die uses a signature to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure, a first interposer, a second interposer, a first semiconductor die, and a second semiconductor die. The substrate structure has a first surface and a second surface opposite to the first surface. The first interposer is disposed over the first surface of the substrate structure. The second interposer is disposed over the first interposer. The first and the second semiconductor dies are disposed over the first surface of the substrate structure, and the first and the second semiconductor dies are bonded to two opposite sides of the second interposer, respectively. The substrate structure includes a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure.

A 3D IC device includes a first device tier including a first set of active devices, a second device tier including a second set of active devices, and a clock distribution network including clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device includes a logic circuit including registers each including a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register. The first active device is included in the first set of active devices of the first device tier and the second active device is included in the second set of active devices of the second device tier and connected to the clock distribution network to receive a clock signal.

The invention provides a thermal simulation method and device, equipment and a computer program. The method comprises the following steps: dividing each layer of chip based on material types, determining a plurality of material areas, and determining the average temperature of each material area; based on the average temperature of each material region in each layer of chip, determining the equivalent thermal conductivity of each layer of chip in the first direction; wherein the first direction is a chip stacking direction; and calculating the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chip in the first direction. According to the method and the device, the simulation precision of the heat distribution condition of the 3D integrated circuit chip under different power consumption can be improved, so that the calculation accuracy of parameters such as equivalent heat conductivity and equivalent heat resistance is improved.

A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.

A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.

The application discloses a monolithic 3D integrated circuit layout method, device, equipment and medium, and relates to the technical field of layout and wiring, to solve the problem of excessive total length of the connection line of the existing 3D integrated circuit layout. The method comprises the following steps: obtaining unit information of an integrated circuit to be laid out; determining a first root unit and a unit to be distributed; for any one unit in the unit to be distributed, determining the area of a current first circuit layer and a second circuit layer according to the unit width and the unit height, and determining the circuit layer with smaller area as a target circuit layer of the unit to be distributed; based on the connection information and the port coordinates, determining the position of the unit to be distributed in the target circuit layer as a target position when the total length of the connection line of the 3D integrated circuit is the shortest; and sequentially determining the target circuit layer and the target position of the remaining units, to complete the layout of the 3D integrated circuit. The monolithic 3D integrated circuit layout method provided by the application is used for shortening the total length of the connection line of the 3D integrated circuit, and improving the performance of the 3D integrated circuit.

A seed layer for deep vias in glass and its preparation method are disclosed, belonging to the field of semiconductor packaging and 3D integrated circuit interconnect technology. The seed layer is a four-layer composite seed layer structure sequentially prepared on the wall of the deep via in a glass substrate and the substrate surface, consisting of a PVD-Ti adhesion layer, a chemically plated Ni transition buffer layer, a chemically plated Cu conformal conductive layer, and a PVD surface Cu reinforcing layer. This invention solves problems such as shadowing effect, weak interface bonding, high residual stress, and seed layer disconnection in high aspect ratio TGV deep vias by designing a composite seed layer, achieving void-free metallization of glass vias with an aspect ratio ≥15:1, improving the structural stability and conductivity of the seed layer, and adapting it to the 3D high-density interconnect manufacturing of next-generation glass interposers. Simultaneously, by controlling key PVD parameters, the PVD sputtering effect is significantly improved, allowing the sputtered portion to penetrate deeper into the hole structure, thereby effectively improving the film coverage uniformity and adhesion performance.

Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device layer comprising a first set of active devices; a second semiconductor device layer comprising a second set of active devices; a clock circuit comprising a first active device, the first active device being comprised in the first set of active devices of the first semiconductor device layer; and a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on a side of the first semiconductor device layer facing the second semiconductor device layer, and a set of active clock devices formed by second active devices, the second active devices being comprised in the second set of active devices of the second semiconductor device layer; wherein the clock circuit is connected to the clock distribution network to receive a clock signal.

A semiconductor package including a redistribution structure, a first capacitor die on the redistribution structure, a 3D integrated circuit structure on the redistribution structure, and next to the first capacitor die, a logic die on the first capacitor die, and on the 3D integrated circuit structure;, and a memory stack on the 3D integrated circuit structure. The 3D integrated circuit structure including a second capacitor die and a buffer die on the second capacitor die.

An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.

This invention relates to a method and system for acquiring layout images of three-dimensional integrated circuit structures. The method includes: acquiring the three-dimensional structural information of the three-dimensional integrated circuit structure based on the architecture of the hardware units within the structure; establishing a coordinate system and acquiring the coordinate information of each hardware unit in the coordinate system, determining the effective layout image range of each hardware unit; acquiring the layout image of each hardware unit based on the determined effective layout image range; stitching the layout images of each hardware unit together based on the coordinate information of each hardware unit to obtain a stitched graphic; and obtaining the layout image of the three-dimensional integrated circuit structure based on the stitched graphic. This method solves the problems of wasting time on high-precision imaging in areas without layout information and increasing the difficulty of stitching and alignment in layout images in areas without layout information, making the acquisition of layout images of three-dimensional integrated circuit structures more efficient and accurate, and improving the efficiency of chip layout image acquisition.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device layer comprising a first set of active devices; a second semiconductor device layer comprising a second set of active devices; a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on a side of the first semiconductor device layer facing the second semiconductor device layer; and a logic circuit comprising a plurality of registers, each register comprising a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register, wherein the first active device is comprised in the first set of active devices of the first semiconductor device layer, and wherein the second active device is comprised in the second set of active devices of the second semiconductor device layer and connected to the clock distribution network to receive a clock signal.

Some embodiments relate to a method of forming a redistribution layer (RDL) stack of a 3D integrated circuit stack. The method comprises removing a substrate form the first side of a first die to expose a first dielectric layer. A spiral trench is formed in the first dielectric layer with one end of the spiral trench directly over a through silicon via (TSV) beneath the first dielectric layer. A first barrier layer is formed along sidewalls of the spiral trench, the first barrier layer being thermally coupled to the TSV. A first conductive wire is formed within the spiral trench, separated from the first dielectric layer by the barrier layer.

In one aspect, a 3D IC device is provided, comprising: a package routing plane comprising a global VDD voltage node and a global VSS voltage node; a die stack disposed on the package wiring plane and including a plurality of stacked dies stacked on each other; a metal interconnect layer disposed atop a top stacked die in the die stack; and a through interconnect extending vertically through each stacked die in the stack of dies and connecting the metal interconnect layer to a global VDD voltage node; wherein each stacked die in the die stack has a bottom surface and a top surface, a local VDD voltage contact on the top surface thereof, and a local VSS voltage contact on the bottom surface thereof, and wherein the stacked dies in the die stack are voltage stacked between a global VDD voltage node and a global VSS voltage node.

The invention discloses a three-dimensional integrated circuit material information management method and system and a storage medium, and the method comprises the steps: taking a core particle as a unit, constructing and managing a core particle material information base, and enabling the core particle material information base to support level calling; constructing and managing a hierarchical material distribution library by taking the core particles as units, calling a core particle material information library when the hierarchical material distribution library is managed, and establishing associated material attribute data of hierarchies and material attributes; thermodynamic performance analysis simulation is started, and a simulation engine calls the associated material attribute data from the hierarchical material distribution library for simulation analysis. Based on the core particle material information library and the hierarchical material distribution library, centralized management, distribution and editing of 3DIC chip material information are realized, material association and distribution according to hierarchy are realized, the maintenance process of the material library is simplified, and the efficiency of thermal simulation and electromagnetic simulation is improved.

The invention provides an F2F three-dimensional integrated circuit layout optimization method based on improved simulated annealing. The F2F three-dimensional integrated circuit layout optimization method comprises the following steps: constructing an initial three-dimensional layout; configuring simulated annealing algorithm parameters, and initializing a multi-target layout cost evaluation model containing cross-layer network interconnection cost; circularly executing the following operations until a termination condition is met: applying controllable random disturbance to the current layout to generate a new layout candidate scheme, wherein the disturbance at least comprises module cross-layer migration meeting F2F bonding interlayer spacing constraint; identifying a network and a layout area affected by disturbance, only calculating representative network cost change of an affected network group through network topology feature grouping, and deducing overall cost variation; according to the current temperature and the overall cost variation, whether a new layout is accepted or not is determined according to the Metropolis criterion; if accepting, updating the current layout and the cost value, and if rejecting, discarding the new layout and not executing state rollback; and adjusting the current temperature through a self-adaptive temperature scheduling strategy, and outputting an optimal layout scheme after iteration is ended.