6 results about "3d integrated circuit" patented technology

A device includes a first device tier including a first set of active devices and a second device tier including a second set of active devices. The device also includes a clocked circuit including first active devices of the first set of active devices, and a clock distribution network including a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device also includes a set of active clock devices formed by second active devices of the second set of active devices. The clocked circuit is connected to the clock distribution network to receive a clock signal.

A 3D IC device includes a first device tier including a first set of active devices, a second device tier including a second set of active devices, and a clock distribution network including clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device includes a logic circuit including registers each including a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register. The first active device is included in the first set of active devices of the first device tier and the second active device is included in the second set of active devices of the second device tier and connected to the clock distribution network to receive a clock signal.

A seed layer for deep vias in glass and its preparation method are disclosed, belonging to the field of semiconductor packaging and 3D integrated circuit interconnect technology. The seed layer is a four-layer composite seed layer structure sequentially prepared on the wall of the deep via in a glass substrate and the substrate surface, consisting of a PVD-Ti adhesion layer, a chemically plated Ni transition buffer layer, a chemically plated Cu conformal conductive layer, and a PVD surface Cu reinforcing layer. This invention solves problems such as shadowing effect, weak interface bonding, high residual stress, and seed layer disconnection in high aspect ratio TGV deep vias by designing a composite seed layer, achieving void-free metallization of glass vias with an aspect ratio ≥15:1, improving the structural stability and conductivity of the seed layer, and adapting it to the 3D high-density interconnect manufacturing of next-generation glass interposers. Simultaneously, by controlling key PVD parameters, the PVD sputtering effect is significantly improved, allowing the sputtered portion to penetrate deeper into the hole structure, thereby effectively improving the film coverage uniformity and adhesion performance.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device layer comprising a first set of active devices; a second semiconductor device layer comprising a second set of active devices; a clock circuit comprising a first active device, the first active device being comprised in the first set of active devices of the first semiconductor device layer; and a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on a side of the first semiconductor device layer facing the second semiconductor device layer, and a set of active clock devices formed by second active devices, the second active devices being comprised in the second set of active devices of the second semiconductor device layer; wherein the clock circuit is connected to the clock distribution network to receive a clock signal.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device layer comprising a first set of active devices; a second semiconductor device layer comprising a second set of active devices; a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on a side of the first semiconductor device layer facing the second semiconductor device layer; and a logic circuit comprising a plurality of registers, each register comprising a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register, wherein the first active device is comprised in the first set of active devices of the first semiconductor device layer, and wherein the second active device is comprised in the second set of active devices of the second semiconductor device layer and connected to the clock distribution network to receive a clock signal.

The present application relates to the technical field of integrated circuits, and discloses a method and device for 3D integrated circuit thermal simulation and a storage medium. The existing method based on machine learning ignores the shared structure of heat conduction and diffusion type partial differential equations, resulting in the problem of needing to train from zero, relying on massive data and poor generalization ability. The method comprises the following steps: obtaining a pre-trained basic model on a diversified data set containing diffusion type partial differential equations; fine-tuning the pre-trained model to adapt to the 3D integrated circuit thermal simulation task, reinitializing the embedding layer and the recovery layer to process specific input and output features, and keeping the backbone network pre-training weight; applying different learning rates to different layers in fine-tuning, using a lower learning rate for the backbone network and a higher learning rate for the embedding layer and the recovery layer; using a combined loss function for optimization, including a global fidelity loss and a hotspot area loss emphasizing the prediction accuracy of high temperature areas; and using the fine-tuned model to predict the steady-state temperature field distribution of the 3D integrated circuit.