48 results about "3d integrated circuit" patented technology

A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

A vertically stacked 3D integrated circuit structure includes at least two chiplets: a first chiplet formed from a non-diamond semiconductor material, a second chiplet formed from diamond. The diamond chiplet is positioned vertically relative to the first chiplet and is electrically coupled thereto. Thermal vias are formed through one or more of the non-diamond chiplets and include material to form heat extraction pathways. These thermal vias are thermally coupled to a heat-spreading structure, which may include the diamond chiplet, a diamond interposer, or an encapsulating diamond-based packaging layer.

The invention relates to the technical field of 3D integrated circuit thermal simulation, and particularly discloses a vertical interconnection layer equivalent thermal conductivity mapping method and a storage medium. According to the method, two-dimensional thermal simulation simplification of a complex three-dimensional structure is realized by establishing equivalent thermal conductivity calculation models of different interconnection structures. For a structure comprising a redistribution layer (RDL), a bilinear interpolation model is adopted to calculate equivalent thermal conductivity based on wiring spacing, line width and silicon dioxide thermal conductivity parameters. The method specifically comprises the following steps: obtaining a weight coefficient corresponding to a wiring parameter through a predefined two-dimensional lookup table, calculating a volume ratio by combining the thermal conductivity of metal and silicon dioxide, obtaining an initial value of equivalent thermal conductivity by using a linear mixing rule, and finally obtaining uniform equivalent thermal conductivity through bilinear interpolation correction. According to the method, the problem of complex multi-scale structure modeling in traditional thermal simulation is effectively solved, the thermal analysis efficiency of the 3D integrated circuit is remarkably improved, and meanwhile, the calculation precision is ensured.

An integrated circuit package is provided in which a hybrid-bonded stack of memory dies couples through a plurality of through-mold vias to a redistribution layer. A logic die couples to the redistribution layer through a plurality of interconnects.

The invention belongs to the technical field of integrated circuit design and test, and discloses a built-in self-test circuit and method for ILV fault positioning optimization in a 3D IC, and the circuit comprises a BIST mode generation module, a signal transmission module, a fault capturing module, and a fault positioning module. The ILV fault can be efficiently detected and positioned by generating test modes for different fault types, controlling one-way propagation of signals and scanning and capturing fault signals. The method is suitable for high-density irregular ILV layout, extra test ports are not needed, compared with a traditional test method, the method is short in test time and high in fault positioning precision, meanwhile, consumption of hardware resources is reduced, and the reliability and production efficiency of a 3D integrated circuit are further improved.

The invention relates to the field of integrated circuit design, and provides a temperature-adaptive TSV layer equivalent thermal conductivity dynamic calculation method. The invention aims to solve the problem of insufficient precision caused by nonlinear change of thermal conductivity of a silicon material along with temperature in equivalent thermal conductivity calculation of a TSV layer of a 3D integrated circuit, and obtains initial structure parameters of the TSV layer, including TSV array density and radius; based on the density and radius of the TSV array, determining a mixing coefficient of copper and silicon through a pre-constructed mixing coefficient lookup table, querying real-time heat conductivity of silicon and copper according to current temperature field data, calculating equivalent heat conductivity, and substituting the equivalent heat conductivity into a heat conduction equation for temperature field simulation to obtain updated temperature distribution data; and updating the heat conductivity of copper and silicon according to the simulation temperature, carrying out iteration until the relative variation of the equivalent heat conductivity is smaller than a preset threshold value, and outputting the converged equivalent heat conductivity.

Methods of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors is on top of the first level; providing placement data of the second level; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; performing a routing of the first level using a router {part of the CAD tool or another CAD tool) executed by a computer, where at least one metal routing layer is disposed in-between the first transistors and the second transistors, and the second level includes repeating structures.

An integrated circuit package is provided in which a hybrid-bonded stack of memory dies couples through a plurality of through-mold vias to a redistribution layer. A logic die couples to the redistribution layer through a plurality of interconnects.

In an aspect there is provided a 3D IC device comprising: a package wiring plane comprising a global VDD voltage node and a global VSS voltage node; a die stack arranged over the package wiring plane and comprising a number of stacked dies stacked on top of each other; a metal interconnect layer arranged on top of a top stacked die of the die stack; and a pass-through interconnect extending vertically through each stacked die of the die stack and connecting the metal interconnect layer to the global VDD voltage node; wherein each stacked die of the die stack has a bottom side and a top side, a local VDD voltage contact on its top side and a local VSS voltage contact on its bottom side.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die transmits a test pattern to the second circuit die via the interconnect layer. Then, the second circuit die determines that a first interconnect has failed based on the test pattern and generates a signature. Finally, the second circuit die uses signatures to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

An apparatus of a ferromagnetic transformer in a 3D integrated circuit is described, which comprises a plurality of semiconductor chips stacked within the 3D integrated circuit. An individual semiconductor chip of the plurality of semiconductor chips comprises a substrate, a plurality of dielectric layers, and a plurality of metal layers in the plurality of dielectric layers. In at least one example, the apparatus comprises one or more ferromagnetic through silicon vias vertically positioned through the individual semiconductor chip.

The invention belongs to the technical field of integrated circuit packaging, and provides a packaging structure and packaging method of a 3D integrated circuit, and the packaging structure comprises a multi-layer chip stacking body, an inter-chip interconnection layer, a power distribution network, a heat dissipation module, and a packaging substrate. The multi-layer chip stacking body comprises integrated circuit chips, the integrated circuit chips are arranged in a three-dimensional stacking mode, and the integrated circuit chips are electrically connected through vertical interconnection structures; the inter-chip interconnection layer is configured between adjacent integrated circuit chips, comprises multiple layers of metal interconnection circuits, is made of a high-density and low-resistance metal material, and is integrated with a signal isolation structure; the power distribution network is configured to be integrated in the packaging substrate, and the power supply voltage of the integrated circuit chip is adjusted through the programmable switch matrix; the heat dissipation module is connected with the multi-layer chip stacking body; the package substrate is disposed at the bottom of the multi-layer chip stack for supporting the entire package structure. According to the invention, miniaturization and lightweight application of an integrated circuit is facilitated.

The present invention belongs to the technical field of integrated circuit design and testing, and discloses a built-in self-test circuit and method for optimizing ILV fault location in 3D IC. The circuit includes a BIST mode generation module, a signal transmission module, a fault capture module, and a fault location module. By generating test patterns for different fault types, controlling the unidirectional propagation of signals, and capturing and locating fault signals through scan chains, it can efficiently detect and locate ILV faults. The present invention is applicable to high-density and irregular ILV layouts, without the need for additional test ports. Compared with traditional test methods, the present invention has a short test time, high fault location accuracy, reduces the consumption of hardware resources, and further improves the reliability and production efficiency of 3D integrated circuits.

A package substrate according to the present disclosure includes a package substrate, an interposer disposed over the package substrate, a photonic die disposed over the interposer, a memory structure disposed over the interposer and including a controller die, a system die disposed over the interposer and partially overlapping with the photonic die and the controller die, and a lid covering the system die, the memory structure, and photonic die. The system die includes micro bumps extending from a bottom surface of the system die to a top surface of the controller die.

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

A device includes a first device tier including a first set of active devices and a second device tier including a second set of active devices. The device also includes a clocked circuit including first active devices of the first set of active devices, and a clock distribution network including a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device also includes a set of active clock devices formed by second active devices of the second set of active devices. The clocked circuit is connected to the clock distribution network to receive a clock signal.

Interconnect repair systems and methods for integrated circuits (e.g., 3D integrated circuits, 2.5 D integrated circuits, etc.). An example integrated circuit includes a first circuit die, a second circuit die, and an interconnect layer. The first circuit die emits a test pattern to the second circuit die via the interconnect layer. The second circuit die then determines, based on the test pattern, that a first interconnect has failed and generates a signature. Finally, the second circuit die uses a signature to cause deactivation of the first interconnect and activation of a second interconnect on both the first circuit die and the second circuit die. The disclosed interconnect repair systems and methods can be used to provide various advantages.

The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

A 3D integrated circuit includes a first integrated circuit including a first substrate. A second integrated circuit is stacked on the first integrated circuit. A through via extends through the first substrate and electrically connects the first integrated circuit and the second integrated circuit to one another. A plurality of protection circuits is disposed at opposite sides of the through via in a keep-out zone surrounding the through via and is electrically connected to the through via.

1. Name of the Design Product: Electronic Device with a Graphical User Interface for 3D Integrated Circuit Design Control 2. Use of the Design Product: An electronic device 3. Design Key Points of the Design Product: Lies in the graphical user interface 4. Picture or Photograph that Best Illustrates the Design Key Points: The front view of Design 1 5. The electronic device is a prior design, and the rear view, left view, right view, top view, and bottom view of Designs 1 - 5 are omitted 6. Design 1 is designated as the basic design 7. Use of the Graphical User Interface: Used for the display and editing of the physical structure during the stacking of multiple chips in 3D integrated circuit design and the display and verification of simulation data, improving the design efficiency of 3D integrated circuits 8. Human - Machine Interaction Method of the Graphical User Interface: In the front view of Design 1, operations such as zooming in, zooming out, dragging, and rotating the 3D integrated circuit model can be performed through mouse operations. At the same time, physical devices in the 3D integrated circuit can be selected through the mouse, and editing operations such as moving, dragging, and deleting the selected devices can be performed. On the right side of the interface, corresponding buttons can be selected to check or uncheck to control the visibility and selectability of the metal layers in each chip; in the front view of Design 2, operations such as zooming in, zooming out, dragging, and rotating the 3D integrated circuit model can be performed through mouse operations. At the same time, physical devices in the 3D integrated circuit can be selected through the mouse, and editing operations such as moving, dragging, and deleting the selected devices can be performed. On the right side of the interface, corresponding buttons can be selected to check or uncheck to control the visibility and selectability of different types of devices in each chip; the interaction method of Design 3 is the same as that of Design 2; in the front view of Design 4, operations such as zooming in, zooming out, dragging, and rotating the 3D integrated circuit model can be performed through mouse operations. At the same time, physical devices in the 3D integrated circuit can be selected through the mouse, and editing operations such as moving, dragging, and deleting the selected devices can be performed. On the right side of the interface, corresponding buttons can be selected to check or uncheck to control the visibility and selectability of devices with different uses in each chip; in the front view of Design 5, operations such as zooming in, zooming out, dragging, and rotating the 3D integrated circuit model can be performed through mouse operations. At the same time, physical devices in the 3D integrated circuit can be selected through the mouse, and editing operations such as moving, dragging, and deleting the selected devices can be performed. On the right side of the interface, various display control data can be input to perform more detailed control on the front view 9. Other Situations Requiring Explanation: Other Explanation: The single gray color block in the interface represents the content screen

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure, a first interposer, a second interposer, a first semiconductor die, and a second semiconductor die. The substrate structure has a first surface and a second surface opposite to the first surface. The first interposer is disposed over the first surface of the substrate structure. The second interposer is disposed over the first interposer. The first and the second semiconductor dies are disposed over the first surface of the substrate structure, and the first and the second semiconductor dies are bonded to two opposite sides of the second interposer, respectively. The substrate structure includes a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure.

A 3D IC device includes a first device tier including a first set of active devices, a second device tier including a second set of active devices, and a clock distribution network including clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device includes a logic circuit including registers each including a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register. The first active device is included in the first set of active devices of the first device tier and the second active device is included in the second set of active devices of the second device tier and connected to the clock distribution network to receive a clock signal.

The invention provides a thermal simulation method and device, equipment and a computer program. The method comprises the following steps: dividing each layer of chip based on material types, determining a plurality of material areas, and determining the average temperature of each material area; based on the average temperature of each material region in each layer of chip, determining the equivalent thermal conductivity of each layer of chip in the first direction; wherein the first direction is a chip stacking direction; and calculating the equivalent thermal conductivity of the chip stacking structure based on the equivalent thermal conductivity of each layer of chip in the first direction. According to the method and the device, the simulation precision of the heat distribution condition of the 3D integrated circuit chip under different power consumption can be improved, so that the calculation accuracy of parameters such as equivalent heat conductivity and equivalent heat resistance is improved.

A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.

The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.

A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.

The present invention belongs to the field of integrated circuit packaging technology and provides a packaging structure and packaging method for a 3D integrated circuit. The packaging structure includes: a multi-layer chip stack, an inter-chip interconnect layer, a power distribution network, a heat dissipation module, and a packaging substrate. The multi-layer chip stack includes integrated circuit chips arranged in a three-dimensional stack, and the integrated circuit chips are electrically connected via a vertical interconnect structure. The inter-chip interconnect layer is arranged between adjacent integrated circuit chips and includes multiple layers of metal interconnect lines made of high-density, low-resistance metal materials and integrated with a signal isolation structure. The power distribution network is configured to be integrated into the packaging substrate, and the supply voltage of the integrated circuit chips is adjusted via a programmable switch matrix. The heat dissipation module is connected to the multi-layer chip stack. The packaging substrate is arranged at the bottom of the multi-layer chip stack to support the entire packaging structure. The present invention facilitates the miniaturization and lightweight application of integrated circuits.

Achieving homogeneous and heterogeneous integration for 2.5D and 3D integrated circuit, chip-to-wafer, chip-to-substrate, or wafer-to-wafer bonding is an essential technology. The landing wafer or substrate is bonded with a carrier by using a temporary bonding material before thinning the landing wafer to the desired thickness. Upon completion of redistribution layer formation, Cu pad formation, or other backside processing, dies or wafers with through-silicon vias are stacked onto the landing substrate before molding and singulation. As the landing wafer usually has interconnection metals in the bond line, and those interconnection metals are typically made from lead-free solder alloys, deformation of those solder alloys during thermocompression bonding becomes an issue for manufacturers. To address this issue, a polymeric material with desired strengths is coated on the device wafer to form a conformal protective layer on top of solder alloys, thus enabling temporary bonding and debonding processes.