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SOI three-dimensional CMOS integrated component and preparation method thereof

A technology for integrating devices and manufacturing methods, which is applied in the manufacturing of semiconductor/solid-state devices, electric solid-state devices, semiconductor devices, etc., can solve the problems of low speed of three-dimensional integrated circuits, and can ensure AC and DC electrical performance, improve device performance, and improve performance. Effect

Inactive Publication Date: 2009-04-15
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0012] One of the objects of the present invention is to provide a structure of an SOI three-dimensional CMOS integrated device, and the second object is to provide a method for making an SOI three-dimensional CMOS integrated device, so as to solve the problem of low speed of the existing three-dimensional integrated circuits

Method used

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  • SOI three-dimensional CMOS integrated component and preparation method thereof
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Embodiment 1

[0039] Embodiment 1: The steps of making a SOI three-dimensional CMOS integrated device with a conductive channel of 65nm are as follows:

[0040] (1) Select SSOI substrates with stress > 1Gpa;

[0041] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposit polysilicon-photolithography polysilicon and diffusion layer contact hole-deposition polysilicon-photolithography polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 - Lithographic wiring holes - polysilicon wiring - low temperature deposition of SiO 2 For the dielectric layer, make a strained Si nMOSFET device structure and interconnections with a conductive channel of 65nm, and complete the lower active layer structure;

[0042] (3) Deposit SiO on the surface of the above active layer 2 medium layer;

[0043] (4) Carry out surface oxidation to the cleaned n-type Si sheet, as the upper substrate material;

[0044] (5) Using an ion implantati...

Embodiment 2

[0051] Embodiment 2: The steps of making a SOI three-dimensional CMOS integrated device with a conductive channel of 90nm are as follows:

[0052] (1) Select SSOI substrates with stress > 1Gpa;

[0053] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposit polysilicon-photolithography polysilicon and diffusion layer contact hole-deposition polysilicon-photolithography polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 - Lithographic wiring holes - polysilicon wiring - low temperature deposition of SiO 2 For the dielectric layer, make a strained Si nMOSFET device structure and interconnection with a conductive channel of 90nm, and complete the lower active layer structure;

[0054] (3) Deposit SiO on the surface of the above active layer 2 medium layer;

[0055] (4) Carry out surface oxidation to the cleaned n-type Si sheet, as the upper substrate material;

[0056] (5) Using an ion implantatio...

Embodiment 3

[0063] Embodiment 3: The steps of making an SOI three-dimensional CMOS integrated device with a conductive channel of 130nm are as follows:

[0064] (1) Select SSOI substrates with stress > 1Gpa;

[0065] (2) On the SSOI substrate, use oxidation-photolithography source, drain, gate region-gate oxidation-deposit polysilicon-photolithography polysilicon and diffusion layer contact hole-deposition polysilicon-photolithography polysilicon-phosphorus implantation-low temperature deposition Product SiO 2 - Lithographic wiring holes - polysilicon wiring - low temperature deposition of SiO 2 For the dielectric layer, make a strained Si nMOSFET device structure and interconnections with a conductive channel of 130nm, and complete the lower active layer structure;

[0066] (3) Deposit SiO on the surface of the above active layer 2 medium layer;

[0067] (4) Carry out surface oxidation to the cleaned n-type Si sheet, as the upper substrate material;

[0068] (5) Using an ion implant...

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Abstract

The invention discloses a 3D SOI CMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SSGOI substrate are employed to construct two active layers of a new 3D CMOS integrated device; wherein, the lower active layer is the SSOI substrate and is made into a strained Si nMOSFET device by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is the SSGOI substrate and is made into a strained SiGe surface channel pMOSFET device by utilizing the characteristic of high hole mobility of the strained Si material in the SSGOI substrate; the upper active layer and the lower active layer form a 3D active layer structure by a bonding process, and are connected by an interconnection line to form the 3D CMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D SOI CMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a silicon-on-insulator SOI three-dimensional CMOS integrated device and a manufacturing method thereof. Background technique [0002] Integrated circuits follow Moore's law, and the feature size continues to decrease, and the integration and performance of chips continue to improve. Entering the deep submicron era, the interconnection of devices inside the chip becomes more and more complex. Therefore, the influence of the delay time caused by the parasitic resistance and parasitic capacitance of the interconnection on the performance of the circuit becomes more and more prominent. Studies have shown that after the feature size of the device is less than 250nm, the R-C delay caused by conventional metal wiring will dominate the delay of the entire circuit, which restricts the continuous improvement of the integration and performance of VLSI. The use of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 张鹤鸣胡辉勇戴显英宣荣喜舒斌宋建军王冠宇
Owner XIDIAN UNIV
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