91 results about "Soi cmos" patented technology

Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

A hybrid laser for generating radiation includes an optical passive material and an optical active material. The laser includes a first optical waveguide and optical laser components with reflectors in the optical passive material. The first optical waveguide is adapted for coupling out radiation from the hybrid laser. The laser also includes a second optical waveguide defined in the optical active material. The optical laser components include reflectors defining a cavity and furthermore are adapted for providing laser cavity confinement in the first optical waveguide and the second optical waveguide. The second optical waveguide thereby is positioned at least partly over the first optical waveguide so that an evanescent coupling interface is defined between the second optical waveguide and the first optical waveguide and the evanescent coupling interface is positioned within the laser cavity.

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

A structure and process for making a semiconductor device with SOI body contacts under the gate conductor. The gate conductor is partitioned into segments and provides a body contact under each gate conductor segment over the width of the device. A plurality of body contacts may be distributed across the length of the gate conductor. This results in a relatively short path for holes leaving the body to traverse and allows accumulated charge to be removed from the body region under the gate. The structure provides for stable and efficient body-contact operation for SOI MOSFETS of any width operating at high speeds.

The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.

CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) diffusion source within the insulation layer underlying the gate regions of the SOI wafer substantially between the source and drain. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the p- and n-wells, thereby forming asymmetric retrograde dopant profiles in the channel under the gate. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.

The invention discloses a control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches. The control circuit comprises a band-gap reference circuit, a low-dropout linear voltage regulator, an annular oscillator, voltage inverters, a non-overlapping clock circuit, a charge pump and a level switching circuit. A core unit of the control circuit is a charge pump circuit capable of generating negative voltages. The band-gap reference circuit is connected with the low-dropout linear voltage regulator, an output end of the low-dropout linear voltage regulator is connected with the charge pump, an output end of the annular oscillator is connected with an input end of the inverter I2 by the inverter I1, an output end of the inverter I1 and an output end of the inverter I2 are connected with an input end of the non-overlapping clock generating circuit, four output ends of the non-overlapping clock generating circuit is connected with an input end of the charge pump, and the SOI CMOS radiofrequency switches can be controlled by an output end OUTPUT of the charge pump via the level switching circuit. The control circuit has the advantages that the charge pump capable of generating the negative voltages can be quickly started and has low steady-state currents, accordingly, radiofrequency switch tubes can be assuredly in excellent closed states under the conditions of high radiofrequency signals, and the linearity and the isolation of the radiofrequency switches can be improved.

A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

In a protection NMOS transistor serving as an ESD input/output protection element formed on a semiconductor support substrate, a drain region of the N-type protection transistor is formed so as to surround the source region, and a minimum distance between the source and the drain is kept constant, which makes it possible to ensure a sufficient ESD breakdown strength and to realize a structure capable of protecting input/output terminal, particularly an output terminal, of the fully depleted SOI CMOS device vulnerable to ESD noise.

Provided is a structure in which a gate electrode of an MMOS transistor of a fully depleted SOT CMOS circuit formed on a semiconductor thin film has an N-type conductivity, while a gate electrode of an protection NMOS transistor as an ESD input/output protection element formed on a semiconductor support substrate has a P-type conductivity, making it possible to protect input/output terminals, especially, an output terminal of a fully depleted SOI CMOS device, which is weak against ESD noise, while ensuring a sufficient ESD breakdown strength.

An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other devices to reduce leakage. Devices with high threshold have a thicker gate oxide or a high k dielectric gate oxide that is selected based on threshold voltage (VT) variations with gate oxide dielectric type or gate oxide thickness for the particular technology, e.g., PD SOI CMOS. High threshold devices may be used in non-critical path margin identified. A thicker device threshold is selected for non-critical path FETs based on the non-critical path margin. Non-critical path delays are re-checked. FETs are formed with the selected thicker gate oxide for any non-critical paths passing the re-check and in array FETs with non-selected FETs being formed with normal gate oxide thickness.