Ultra-thin soi CMOS with raised epitaxial source and drain and embedded sige pfet extension

Abstract

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source / drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source / drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source / drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

Description

FIELD OF THE INVENTION [0001]The present invention related generally to the fabrication of complementary metal oxide semiconductor (CMOS) field effect transistors (FET), and more particularly, to a method for forming ultra-thin SOI (UTSOI) field effect transistors with stressed channel regions which provide increased carrier mobility among other benefits.BACKGROUND OF THE INVENTION [0002]CMOS FETs are employed in almost every electronic circuit application such as signal processing, computing, and wireless communications. It has been demonstrated that ultra-thin SOI (UTSOI) FETs have a very good short channel control due to extremely thin channel region. Thin body devices however, lead to high series resistance Rext, which can be mitigated by forming raised source / drain (RSD) regions. It has also been demonstrated however, that thick channel SOI FETs exhibit improved FET performance such as switching speed and drive current, by applying stress in the channel. The improvement stems f...

AI Technical Summary

Benefits of technology

[0009]The present invention provides a novel semiconductor device structure that includes integrating embedded PFET devices with a SiGe extension with raised CMOS source drain regions. Particularly, according to the invention, epitaxially grown raised source and drain structures are formed to reduce contact and source / drain resistance. Additionally, implemented are the embedded SiGe extensions to improve the PFET device extension and channel region conductivity.

[0010]The present invention provides a methodology that includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source / drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source / drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

[0016]wherein said epitaxially grown embedded semiconductor PFET extensions create compressive stress in the UTSOI layer thereby enhancing PFET device performance.

[0027]wherein said epitaxially grown embedded semiconductor extensions create compressive stress in the thin SOI layer thereby enhancing device performance.

Problems solved by technology

Incorporating stress into UTSOI FETs is a challenge because of the thin channel region.

None of this prior art however, addresses the integration of an embedded pFET SiGe extension with raised source / drain regions.

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