421 results about "Buried oxide" patented technology

The invention discloses an MEMS device architecture, which comprises a cap layer, a device layer and a substrate layer, the cap layer is bonded with the device layer, the bonded whole is bonded with the substrate layer, the cap layer is manufactured based on a first silicon substrate, the bottom of the cap layer is provided with a cavity structure, and the cap layer is internally provided with a high-deep groove structure. A silicon dioxide film is arranged on the groove wall of the high-deep groove structure, polycrystalline silicon is deposited and filled in the high-deep groove structure, and a silicon dioxide layer is arranged on the upper surface of the first silicon substrate; the device layer is manufactured based on an SOI wafer and comprises a first silicon structure layer composed of top layer silicon, a buried oxide layer and a second silicon structure layer composed of back substrate silicon. The substrate layer comprises a second silicon substrate, a bottom layer cavity is formed in the top face of the second silicon substrate, and exhaust holes are formed in the bottom face of the second silicon substrate. According to the method, deep groove etching, polycrystalline silicon groove filling and bonding technologies are combined, advanced materials such as the SOI wafer and the polyimide layer are utilized, and excellent signal isolation and flexibility of various MEMS IMU applications are achieved.

The invention discloses a semiconductor structure, a preparation method thereof and a semiconductor device, and belongs to the technical field of semiconductors. The semiconductor structure comprises a substrate which comprises a first surface and a second surface which are oppositely arranged; the groove is recessed from the first surface to the interior of the substrate, and the interface of the groove and the substrate is in a step shape; the buried oxide structure comprises a first buried oxide region and a plurality of second buried oxide regions, the first buried oxide region extends into the substrate from the bottom of the groove, and the second buried oxide regions extend into the substrate from part of the side wall of the groove; the epitaxial layer is arranged in the groove in the buried oxide structure; and the cavity is arranged in the substrate among the epitaxial layer, the first buried oxide region and the second buried oxide region, the depth of the cavity is equal to that of the second buried oxide region, and the atmosphere in the cavity is the same as the atmosphere when the epitaxial layer is formed. According to the semiconductor structure, the preparation method thereof and the semiconductor device provided by the invention, the preparation cost of the semiconductor device can be reduced, and the performance of the device is improved.

The invention discloses a lithium niobate film rapid heat insulation 3dB power beam splitter, and relates to the technical field of integrated photons. Comprising an upper cladding layer, an x-cut lithium niobate film layer, a buried oxide layer and a silicon substrate layer which are sequentially stacked from top to bottom, the x-cut lithium niobate layer contains a lithium niobate film ridge waveguide formed by an etching technology; the lithium niobate film waveguide comprises an input end conical waveguide, an input end S-bent waveguide, a rapid adiabatic mode evolution waveguide and an output end S-bent waveguide which are connected in sequence; on the basis of a traditional linear adiabatic cone, nonlinear change is achieved in combination with adiabatic parameters so as to accelerate the adiabatic process, and the excellent characteristics of broadband and robustness of the adiabatic power beam splitter are reserved while the length of the adiabatic power beam splitter is reduced.

A method of fabricating an IR transparent window wafer with integrated AR grating structures includes providing a handle wafer having a first surface and a second surface opposite the first surface, providing a device wafer including a single crystal silicon layer disposed on an oxide layer, the single crystal silicon layer having a planar side and the oxide layer having a bonding side that is opposite the planar side, forming AR grating structures in a first portion of the first surface of the handle wafer, bonding the bonding side of the oxide layer to the first surface of the handle wafer, and etching a recess in the planar side of the single crystal silicon layer to: remove the buried oxide layer, form a plurality of recess walls, and expose the AR grating structures in the first portion of the first surface of the handle wafer.

The invention provides a wavelength division multiplexing / demultiplexing system based on micro-ring structure and phase change material modulation and a preparation method thereof, and belongs to the field of optical coupling devices. The wavelength division multiplexing / demultiplexing system comprises a substrate and a buried oxide layer which are stacked, and n (n is a positive integer greater than or equal to 2) micro-ring units and an upper cladding which are positioned on the upper surface of the buried oxide layer. And the upper cladding covers the n micro-ring units and is in contact with the buried oxide layer. Each micro-ring unit comprises a straight-through waveguide and at least one micro-ring waveguide. And the n micro-ring units are connected into a whole through the straight waveguide. The micro-ring waveguide includes a first ring waveguide and a second ring waveguide over the first ring waveguide. The second annular waveguide is made of a phase change material, and a fourth distance exists between the second annular waveguide and the first annular waveguide. The micro-ring waveguides are arranged at intervals along the extension direction of the straight waveguide. A first distance exists between the straight-through waveguide and the micro-ring waveguide. The wavelength division multiplexing / demultiplexing system has the properties of low energy consumption, low loss, non-volatility and the like.

The invention discloses a semiconductor structure forming method and a semiconductor structure. The method comprises the steps of providing a substrate; forming a shallow trench isolation structure connected with the buried oxide layer in the top layer silicon, wherein the shallow trench isolation structure is provided with a capacitor region; forming a first interlayer dielectric layer on the substrate; at least two adjacent and mutually independent capacitor openings and a plurality of first conductive openings are formed, the projection of each capacitor opening on the surface of the shallow trench isolation structure is located in the capacitor area, and the projection of each first conductive opening on the surface of the shallow trench isolation structure is located outside the capacitor area; the capacitor opening and the first conductive opening penetrate through the first interlayer dielectric layer, the shallow trench isolation structure and the buried oxide layer; a capacitor conductive structure is formed in each capacitor opening, a first conductive structure is formed in the first conductive opening, and the capacitor conductive structures form MOM capacitors with adjacent positive and negative plates. According to the invention, high integration level is considered while large capacitance is provided.

The invention belongs to the field of MEMS sensors, and discloses a high-temperature-resistant MEMS pressure sensor chip and a packaging structure thereof. The chip is provided with an SOI substrate, an AlN layer and a SiO2 layer from bottom to top, a plurality of P-type piezoresistors are arranged on the uppermost layer of the SOI substrate and are symmetrically distributed at the stress concentration position of the edge of the elastic diaphragm; a channel which continuously penetrates through the AlN layer and the SiO2 layer is arranged above the P-type piezoresistor; a metal Pad is arranged in the channel; the upper end of the metal Pad is located on the uppermost layer of the high-temperature-resistant MEMS pressure sensor chip, and the lower end of the metal Pad is in contact with the P-type piezoresistor. According to the invention, the relatively thick buried oxide layer can resist a high-temperature severe environment, and an AlN heat dissipation material with a high heat conductivity coefficient is deposited, so that rapid heat dissipation at a high temperature is ensured; and meanwhile, the stability and the reliability of the sensor are improved by adopting leadless packaging, and the packaging density is further optimized.

The invention provides an electro-optical modulator and a modulation method thereof, the electro-optical modulator comprises a substrate, a buried oxide layer and a lithium niobate waveguide layer are sequentially stacked on the substrate, and the lithium niobate waveguide layer comprises a first optical waveguide and a second optical waveguide; the electrode layer comprises a composite traveling wave electrode and a direct-current electrode, and the direct-current electrode is arranged on one side, in the signal transmission direction, of the composite traveling wave electrode; wherein the composite traveling wave electrode comprises a metal electrode and a polymer electrode, the metal electrode is embedded into the buried oxide layer, the polymer electrode is arranged on the surface of the buried oxide layer, and the composite traveling wave electrode is arranged between the first optical waveguide and the second optical waveguide and arranged on the side faces of the first optical waveguide and the second optical waveguide respectively; wherein the direct current electrode is arranged between the first optical waveguide and the second optical waveguide. The electro-optical modulator is high in electro-optical conversion efficiency, the plasma effect caused by light field coupling is effectively avoided, and the light loss of the device is remarkably reduced.

The invention provides a junction-free transistor, which comprises a substrate, and a buried oxide layer, a core layer and a shell layer which are sequentially stacked on the substrate, the doping concentration of the shell layer is smaller than that of the core layer, the shell layer is provided with a grid electrode, and the size of the shell layer in a first direction along the surface of the substrate is larger than that of the grid electrode in the first direction, that is, the size of the shell layer in the first direction is smaller than that of the grid electrode. Compared with the condition that the size of the shell layer in the first direction is equal to the size of the grid electrode in the first direction, the size of the shell layer in the first direction is increased in the scheme, so that carriers in a channel are less acted by a source leakage field and are almost only controlled by a grid electrode electric field, and when the device starts, due to the fact that the doping concentration of the shell layer is low or the shell layer is not doped, the performance of the device is improved. Therefore, the carrier mobility is high, the device can have lower off-state current and higher on-state current, and the performance of the device is improved.

A method for producing a substrate comprising a buried oxide layer (1, 10, 20) or a buried nitride layer for the production of electronic components, comprising at least one step for depositing an oxide layer (1, 10, 20) or a nitride layer on a donor substrate (2, 11, 21) and / or an acceptor substrate, and a step for establishing contact between the donor substrate and the acceptor substrate (9, 14, 22), further comprising at least: a first heat treatment of the oxide layer (1, 10, 20) or the nitride layer deposited on the donor substrate (2, 11, 21) and / or the acceptor substrate (9, 14, 22) before connecting the donor substrate (2, 11, 21) with the Acceptor substrate (9, 14, 22) and a second heat treatment of the substrate, which consists of the acceptor substrate (9, 14, 22), the oxide layer (1, 10, 20) or the nitride layer and the entire donor substrate (2, 11, 21) or a part thereof, at a temperature,which is the same as or higher than the temperature applied in the first heat treatment, wherein the second heat treatment is a compression heat treatment, wherein the first heat treatment consists of applying a temperature of 600 to 1000 °C for a period of a few minutes to a few hours in a non-oxidizing inert gas or a mixture of inert gases.

The invention provides a radio frequency switch and a forming method, and the method comprises the steps: providing an SOI which comprises a switch region and a control region which are adjacent to each other; forming a plurality of first shallow trench isolation structures which are arranged at intervals in the top layer silicon of the switch region and the control region; the first shallow trench isolation structure, the buried oxide layer and partial thickness of the bottom layer silicon of the switch region are etched to form second shallow trenches which are arranged at intervals, and the width, located on the bottom layer silicon, of each second shallow trench is larger than the width, located on the buried oxide layer, of each second shallow trench; the second shallow trench is filled with oxide to form a second shallow trench isolation structure, and the thickness of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure; gate structures of the MOS transistor are formed on the surface of the top layer silicon of the switch region and the control region, a source end and a drain end of the MOS transistor are formed in the top layer silicon on the two sides of each gate structure respectively, and the second shallow trench isolation structure is partially located below the source end and the drain end of the switch region.

A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.

The invention discloses a micro MEMS piezoresistive pressure sensor and a preparation method thereof, and belongs to the technical field of piezoresistive pressure sensors. Comprising a base layer, a substrate layer, a bottom silicon layer, a buried oxide layer, a device layer and a metal layer which are stacked from bottom to top, the bottom silicon layer, the buried oxide layer and the device layer form a peninsula-rod beam reinforced pressure sensing diaphragm; the peninsula-rod beam reinforced pressure sensing diaphragm comprises a peninsula, a connecting beam, a stepped rib plate and a central diaphragm; the peninsula is arranged on the upper surface of the central diaphragm, the stepped rib plate is located on the lower surface of the central diaphragm, the rod beam is arranged along the diagonal line of the central diaphragm, and the square island is arranged at the central position of the central diaphragm; and the stepped rib plates are positioned on four sides of the central diaphragm. The peninsula-rod beam reinforced pressure sensing diaphragm is adopted, the peninsula improves the output voltage of the sensor, the rod beam relieves the phenomenon that the displacement of the pressure sensing diaphragm is excessively increased under high stress, the step-shaped rib plate enables a piezoresistor area to generate stress concentration, and the sensitivity and stability of the piezoresistive pressure sensor are improved.

The invention discloses a common-film differential high-static-pressure resonant differential pressure sensor based on hot resistance driving, and relates to a pressure sensor. The invention provides a novel sensor structure based on a thermal piezoresistive effect. The sensor adopts a thermal piezoresistive effect for driving and piezoresistive detection, and comprises a low-voltage side pressure sensing film, a bonding oxide layer, a structural layer, a buried oxide layer, a high-voltage side pressure film and a substrate layer, the low-voltage side pressure sensing film is made of a silicon material, the structural layer and the high-voltage side pressure film are made of SOI sheets, and the substrate layer is made of BF33 glass; the high-pressure side pressure film and the low-pressure side pressure film respectively sense high pressure and low pressure and sense a difference value between the high pressure and the low pressure through deformation of the pressure films, deflection deformation of the films generates tensile stress in a central area and pressure stress in an edge area, the double resonators sense opposite stress and generate opposite frequency deviation, and the difference between the two is used for representing a differential pressure value. The glass substrate is mainly used for isolating thermal stress of the packaging stainless steel base.

The present application provides a junctionless transistor, comprising a substrate (100), and a buried oxide layer (110), a core layer (150), and a shell layer (160) sequentially stacked on the substrate (100). The doping concentration of the shell layer (160) is less than the doping concentration of the core layer (150), a gate (170) is provided on the shell layer (160), and the dimension of the shell layer (160) in a first direction parallel to the surface of the substrate (100) is greater than the dimension of the gate (170) in the first direction. Compared with a scenario where the dimension of the shell layer (160) in the first direction is equal to the dimension of the gate (170) in the first direction, in the present application, the dimension of the shell layer (160) in the first direction is increased, so that charge carriers in a channel are less influenced by source-drain electric fields and are controlled almost exclusively by a gate electric field. During device operation, due to the low doping concentration or absence of doping in the shell layer (160), the charge carrier mobility is high, and therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance.

The invention relates to a lithium niobate electro-optical modulator and a preparation method and application thereof. The lithium niobate electro-optical modulator sequentially comprises a ground electrode, a substrate layer, a buried oxide layer, a lithium niobate waveguide and a high-dielectric-constant cladding from bottom to top. Optical isolation grooves which are symmetrically distributed are formed in two sides of the lithium niobate waveguide; the high-dielectric-constant wrapping layer comprises a first wrapping layer and a second wrapping layer from inside to outside, and the dielectric constant of the first wrapping layer is smaller than that of the second wrapping layer; the number of the high-dielectric-constant claddings is greater than or equal to 2; the lithium niobate electro-optical modulator further comprises a signal electrode, and the signal electrode is embedded in the high-dielectric-constant cladding and located above the optical isolation groove. Due to the synergistic effect of the optical isolation groove and the high-dielectric-constant cladding, the lithium niobate electro-optical modulator not only has high modulation efficiency, but also has high bandwidth. In addition, the lithium niobate electro-optical modulator disclosed by the invention has excellent power tolerance.

A three-dimensional integrated circuit includes a first integrated circuit having a first transistor and a first buried oxide layer; a second integrated circuit having a second transistor and a second buried oxide layer; a bond interface between an upper surface of the first integrated circuit and an upper surface of the second integrated circuit; a passivation layer coupled to the first buried oxide layer; and a mold wafer coupled to the second buried oxide layer.

The invention relates to the technical field of pressure sensors, in particular to a high-temperature-resistant piezoresistive pressure sensor chip and a processing method.The high-temperature-resistant piezoresistive pressure sensor chip comprises a device layer, a buried oxide layer, a supporting layer and a sealing substrate layer, and the buried oxide layer and the device layer are sequentially arranged on the supporting layer; wherein the device layer comprises a piezoresistor and a wire, the piezoresistor and the wire are arranged on the buried oxide layer, and a metal bonding pad is arranged on the wire; the piezoresistor and the wire are made of a P-type silicon material or an N-type silicon material of which the doping concentration is greater than 1014 cm <-3 >; wherein the sealing substrate layer is connected with the device layer and a reference pressure cavity is formed between the sealing substrate layer and the device layer, or the sealing substrate layer is connected with one side, deviating from the device layer, of the supporting layer and a reference pressure cavity is formed between the sealing substrate layer and the supporting layer. According to the invention, the processing efficiency of the high-temperature-resistant piezoresistive pressure sensor chip is improved, and the electrical stability of the chip in a high-temperature environment is improved at the same time.

The invention discloses a grating antenna based on height gradient multi-waveguide radiation blocks, which comprises a substrate layer, a dielectric buried oxide layer, a device layer and an upper cladding, and is characterized in that the device layer is arranged in the upper cladding and comprises a strip-shaped waveguide and a plurality of radiation block arrays, the strip-shaped waveguide is provided with a plurality of Bragg grating units, and the Bragg grating units are arranged in the upper cladding. The radiation block array is arranged on the two sides of the strip-shaped waveguide, the radiation block array comprises a plurality of radiation blocks with different heights, the axis of each radiation block is parallel to the axis of the strip-shaped waveguide, and the heights of the plurality of radiation blocks are gradually increased from the side close to the strip-shaped waveguide to the side far away from the strip-shaped waveguide. According to the invention, the radiation block array is arranged, and the plurality of height gradient radiation blocks in the radiation block array are of an asymmetric structure in the vertical direction, so that compared with a traditional rectangular radiation block, the antenna better conforms to periodic medium disturbance of an optical mode in the upward propagation direction, the directivity of the antenna can be more effectively improved, the radiation at the bottom is inhibited, and the upward radiation efficiency is improved.

A micro-electromechanical system (MEMS) electric field sensor using a resonant torsional shutter and a method of manufacturing the MEMS electric field sensor are described. A method of manufacturing a micro-electromechanical system (MEMS) electric field sensor according an embodiment includes: forming a metal layer on a wafer having a handle layer, a buried oxide layer arranged on the handle layer, and a device layer arranged on the buried oxide layer; patterning the metal layer to form a plurality of electrical pads thereon, forming a comb drive actuator on the device layer, the comb drive actuator including a sensing electrode and a torsional shutter configured to be resonant torsionally driven; forming a driving space of the torsional shutter in the handle layer; and etching and releasing the buried oxide layer.

A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

The invention relates to a 3 [mu] m SOI-based polarization insensitive waveguide grating antenna for optical sensing. The waveguide grating antenna provides a substrate and a ridge waveguide located above the substrate; grating teeth are formed on the upper surface of the ridge waveguide through shallow etching; slab areas on the two sides of the ridge waveguide are provided with deep etching which is etched to the buried oxide layer. The OPA transmit-receive system introduced in the invention has high diffraction efficiency (gt; 70%), which is far greater than 50% emission efficiency of a conventional fishbone-shaped antenna; polarization is insensitive, and inherent loss of a polarization controller in the system can be eliminated; and the beam divergence is small (less than 0.01 degree), and the method has a good application prospect.

The invention discloses a calculation spectrometer based on a random multimode waveguide grating and a spectrum reconstruction method. Comprising a silicon substrate layer, a silicon dioxide buried oxide layer, a lithium niobate waveguide layer, a silicon dioxide coating layer and an interdigital electrode which are sequentially stacked from bottom to top, a mode multiplexer, a multi-mode waveguide spiral line and multi-mode waveguide gratings are formed on the lithium niobate waveguide layer, the mode multiplexer is communicated with the multi-mode waveguide spiral line, the multi-mode waveguide spiral line at least comprises a section of multi-mode straight waveguide, a plurality of non-periodically distributed multi-mode waveguide gratings are arranged on the multi-mode straight waveguide, and the multi-mode waveguide gratings are arranged on the multi-mode straight waveguide. And each multimode waveguide grating unit adopts a Bragg grating structure and comprises two groups of grating tooth structures which are respectively positioned on two sides of the multimode straight waveguide. According to the invention, the electrical control logic can be simplified, the disordered resonance of different modes in the spiral line can provide high spectral reconstruction resolution, and meanwhile, the lithium niobate electro-optical modulation can realize rapid and low-power consumption measurement channel scanning.

The invention relates to the technical field of Hall sensors, and provides a Hall element with a triple isolation structure and a preparation method thereof.The Hall element comprises two pairs of Hall contact areas participating in electrical connection and oxide isolation structures located on the two sides of the Hall contact areas and having a certain gap distance. The oxide buried layer completely isolates the Hall plate area in the vertical direction, the Hall plate is completely isolated from the outside through the isolation structure and the oxide buried layer, external direct current interference is reduced to the maximum extent, meanwhile, the thickness and the current path of the Hall plate are controlled, and the effect of reducing noise interference while the sensitivity is improved is achieved. A three-circle surrounding structure is formed by utilizing a P well in contact with the side face of a Hall plate, a PBL in contact with the vertical bottom of an oxide buried layer and connected with the P well on the side face of the Hall plate, an NBL tightly attached to the lower surface of the PBL, an N well connected with the NBL and surrounding the Hall plate and the P well, and a P well connected with a substrate and surrounding the outermost layer, and Hall voltage changes caused by substrate noise and EMI electromagnetic interference are prevented.

The invention relates to the technical field of semiconductor structures, and discloses a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a first substrate slice and a second substrate slice; depositing polycrystalline silicon on the surface of one side of the second substrate slice to form a polycrystalline silicon layer; growing or depositing an oxide on the surface of one side, far away from the second substrate slice, of the polycrystalline silicon layer to form a first buried oxide layer; forming a graphic structure layer on the surface of one side, far away from the polycrystalline silicon layer, of the first buried oxide layer, wherein the graphic structure layer comprises a plurality of conductive structures and a plurality of insulator structures; based on a thermal oxidation process, growing an oxide on the surface of one side of the first substrate slice to form a second buried oxide layer; and carrying out bonding processing on the surface of one side, far away from the first buried oxide layer, of the graphic structure layer and the surface, subjected to ion implantation processing, of the second buried oxide layer so as to obtain the semiconductor structure. The threshold voltage of the semiconductor device can be adjusted, and the electrical performance of the semiconductor device can be flexibly optimized.

The invention provides a double-sided polishing device and a double-sided polishing method.The double-sided polishing method comprises the steps that firstly, a mechanical grinding process is executed, so that the face, away from a buried oxide layer, of a device wafer is thinned to the preset thickness, and the edge thickness difference of the device wafer meets the first preset threshold value; then executing a double-sided chemical mechanical polishing process to enable the edge thickness difference of the bonded wafer to meet a second preset threshold value; the carrier for executing the double-sided chemical mechanical polishing process comprises a lining and a substrate, the thickness difference between the lining and the substrate is 5-10 [mu] m, and the thickness of the lining is 770-780 [mu] m. By controlling the thickness of the lining and the thickness difference between the lining and the substrate of the carrier for the double-sided chemical mechanical polishing process, the edge thickness difference of the SOI wafer after the double-sided chemical mechanical polishing process meets the second preset threshold value, the edge thickness difference range of top silicon of the SOI wafer is improved, and the edge thickness uniformity of the SOI wafer is improved.

The embodiment of the invention discloses a semiconductor device, a semiconductor wafer, a preparation method and a storage system, the semiconductor wafer comprises a first semiconductor base material, a second semiconductor base material and a high-K dielectric layer, and the second semiconductor base material and the first semiconductor base material are oppositely arranged; the high-K dielectric layer is disposed between the first semiconductor substrate and the second semiconductor substrate. According to the semiconductor wafer provided by the embodiment of the invention, the first semiconductor substrate and the second semiconductor substrate are used as the intermediate bonding layer through the high-K dielectric layer, and the high-K dielectric layer has a higher physical thickness than a buried oxide layer under the condition of the same equivalent oxygen thickness, so that the bonding process is easier to control, and therefore, the reliability of the semiconductor wafer is improved. After the feature size of the semiconductor wafer is miniaturized, the requirement for improving the performance of the device can be met, and meanwhile the requirement for the bonding technology can also be met.

The invention provides a compact low-loss grating coupler with a bottom reflector, which sequentially comprises a silicon substrate layer, a distributed Bragg reflector, a buried oxide layer, a top silicon layer and a top cladding from bottom to top, and is characterized in that the distributed Bragg reflector is formed by laminating silicon and silicon dioxide; the top silicon layer is composed of a focusing type grating waveguide structure and a strip-shaped waveguide structure connected with the focusing type grating waveguide structure, the focusing type grating waveguide structure is composed of a shallow etching area and a full-height waveguide, optimization design is conducted by evaluating the influence rule of physical parameters, and finally efficient transmission of optical signals in an integrated photoelectric system can be achieved. According to the invention, the substrate loss is reduced, and the efficiency of the grating coupler is improved.

The application discloses a preparation method of FE-DSOI wafers and FE-DSOI devices, and the method comprises the following steps: providing a plurality of original wafers; preparing a bottom wafer by using the original wafers; depositing ferroelectric material on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; performing thermal oxidation treatment on the original wafers to obtain a top wafer; and performing bonding and layer transfer treatment on the top wafer and the bottom wafer containing ferroelectric material, so as to obtain FE-DSOI wafers containing ferroelectric material and double buried oxide silicon. By using the application, the technical problems that the conventional DSOI does not have back gate regulation capability and cannot inhibit threshold voltage drift when no back gate voltage is continuously applied in the prior art can be solved.

Some embodiments of the disclosure provide an apparatus comprising a memory cell array region, and a peripheral region including a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor. The SOI CMOS transistor pair includes a buried oxide (BOX) layer in a semiconductor substrate, and an SOI layer on the BOX layer. The SOI layer has a thickness such that a depletion layer when formed in the SOI layer fills the SOI layer between a gate and the BOX layer and between source / drain regions.