131 results about "Buried oxide" patented technology

A method for producing a substrate comprising a buried oxide layer (1, 10, 20) or a buried nitride layer for the production of electronic components, comprising at least one step for depositing an oxide layer (1, 10, 20) or a nitride layer on a donor substrate (2, 11, 21) and / or an acceptor substrate, and a step for establishing contact between the donor substrate and the acceptor substrate (9, 14, 22), further comprising at least: a first heat treatment of the oxide layer (1, 10, 20) or the nitride layer deposited on the donor substrate (2, 11, 21) and / or the acceptor substrate (9, 14, 22) before connecting the donor substrate (2, 11, 21) with the Acceptor substrate (9, 14, 22) and a second heat treatment of the substrate, which consists of the acceptor substrate (9, 14, 22), the oxide layer (1, 10, 20) or the nitride layer and the entire donor substrate (2, 11, 21) or a part thereof, at a temperature,which is the same as or higher than the temperature applied in the first heat treatment, wherein the second heat treatment is a compression heat treatment, wherein the first heat treatment consists of applying a temperature of 600 to 1000 °C for a period of a few minutes to a few hours in a non-oxidizing inert gas or a mixture of inert gases.

The invention relates to the technical field of Hall sensors, and provides a Hall element with a triple isolation structure and a preparation method thereof.The Hall element comprises two pairs of Hall contact areas participating in electrical connection and oxide isolation structures located on the two sides of the Hall contact areas and having a certain gap distance. The oxide buried layer completely isolates the Hall plate area in the vertical direction, the Hall plate is completely isolated from the outside through the isolation structure and the oxide buried layer, external direct current interference is reduced to the maximum extent, meanwhile, the thickness and the current path of the Hall plate are controlled, and the effect of reducing noise interference while the sensitivity is improved is achieved. A three-circle surrounding structure is formed by utilizing a P well in contact with the side face of a Hall plate, a PBL in contact with the vertical bottom of an oxide buried layer and connected with the P well on the side face of the Hall plate, an NBL tightly attached to the lower surface of the PBL, an N well connected with the NBL and surrounding the Hall plate and the P well, and a P well connected with a substrate and surrounding the outermost layer, and Hall voltage changes caused by substrate noise and EMI electromagnetic interference are prevented.

The application discloses a preparation method of FE-DSOI wafers and FE-DSOI devices, and the method comprises the following steps: providing a plurality of original wafers; preparing a bottom wafer by using the original wafers; depositing ferroelectric material on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; performing thermal oxidation treatment on the original wafers to obtain a top wafer; and performing bonding and layer transfer treatment on the top wafer and the bottom wafer containing ferroelectric material, so as to obtain FE-DSOI wafers containing ferroelectric material and double buried oxide silicon. By using the application, the technical problems that the conventional DSOI does not have back gate regulation capability and cannot inhibit threshold voltage drift when no back gate voltage is continuously applied in the prior art can be solved.

Some embodiments of the disclosure provide an apparatus comprising a memory cell array region, and a peripheral region including a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor. The SOI CMOS transistor pair includes a buried oxide (BOX) layer in a semiconductor substrate, and an SOI layer on the BOX layer. The SOI layer has a thickness such that a depletion layer when formed in the SOI layer fills the SOI layer between a gate and the BOX layer and between source / drain regions.

The invention provides an MEMS suspended heating bearing structure for characterization of a projection electron microscope (TEM) and a preparation method of the MEMS suspended heating bearing structure. An SOI silicon wafer comprises device layer silicon, a buried oxide layer and substrate layer silicon. A first silicon oxide layer is arranged on the surface of the device layer, and a heating electrode is arranged on the first silicon oxide layer; the surface of the substrate layer is provided with a second silicon dioxide layer used for back patterning and etching control. The device layer silicon is provided with a first cavity to form a suspended supporting structure, and comprises a central bearing region, a transmission window region and a plurality of supporting beams connected with the central bearing region; the substrate layer silicon is etched from the back surface to form a second cavity, and the second cavity covers the bearing area, the transmission window and the projection range of the supporting beam in the thickness direction. And the second cavity is communicated with the first cavity, so that a through type cavity heat insulation structure is formed. According to the invention, while the permeability of the electron beam transmission window is maintained, stable bearing and controllable heating of the to-be-tested sample are realized, and the requirements of structural reliability, low power consumption and electrical parasitic suppression are considered.

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: providing a substrate structure which comprises a back substrate, a buffer layer and a top silicon layer, a second groove is formed in the base structure, and the buffer layer is removed through etching of the second groove so that a cavity can be formed between the back substrate and the top silicon layer; according to the method, the top silicon layer is provided with a cavity, the cavity is filled with a buried oxide layer to form the SOI substrate, so that the thickness of the top silicon layer and the thickness of the buried oxide layer can be controlled to obtain the SOI substrate with the ideal thickness, the SOI substrate is prevented from being formed through an ion implantation process, correspondingly, ion implantation damage is avoided, and the quality and reliability of the formed SOI substrate are improved.

A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

This invention relates to an end-face coupling structure for a low-loss silicon photonic chip, comprising a silicon substrate, a laser mounting region on the silicon substrate, a buried oxide layer on one side of the laser mounting region and on the silicon substrate, a shallow etched region on the buried oxide layer, and a beveled end face etched on the cross section formed by the buried oxide layer and the shallow etched region. The beveled end face is used to reduce reflection loss. A ridge waveguide facing the laser mounting region is disposed on the shallow etched region, and the incident end of the ridge waveguide is located at the beveled end face. This invention can achieve high coupling efficiency and alignment tolerance.

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.

The invention provides a silicon-on-insulator and a manufacturing method thereof, and the manufacturing method of the silicon-on-insulator comprises the steps: providing a device substrate, and forming a buried oxide layer on the device substrate; executing multiple ion implantation processes to form an embrittlement layer at the target stripping depth; the ion implantation process is a single hydrogen ion implantation process, and the implantation energy in the multiple ion implantation processes is sequentially increased. According to the multi-time ion implantation technology, the technology is optimized through a step-by-step and low-dosage strategy, the precision is remarkably improved, for example, ion implantation is conducted in three times, the total dosage is not changed, the implantation dosage is low each time, and lattice damage accumulation of single-time ion implantation is reduced. The continuity of the buried oxide layer is improved, and the thickness deviation is controllable. The distribution of oxygen ions can be accurately controlled by combining multiple times of ion implantation with gradient implantation energy adjustment: overlapped oxygen concentration peaks are formed in the longitudinal direction by adjusting each time of implantation energy, and a uniform buried oxide layer is fused after annealing.

The invention relates to a heating type gas sensor and a preparation method thereof.The heating type gas sensor comprises a silicon-on-insulator wafer, and the silicon-on-insulator wafer comprises a silicon-based substrate, a buried oxide layer and a semiconductor layer which are stacked from bottom to top, the semiconductor layer is etched to form a plurality of silicon nanowire channels which are spaced from one another and grooves located between the adjacent silicon nanowire channels. The upper surface of the buried oxide layer is etched to form a cavity located below the silicon nanowire channel, and the cavity is communicated with the groove. A plurality of heating elements which are arranged at intervals are arranged in the cavity, and the heating elements are positioned between the silicon nanowire channel and the buried oxide layer. The heating uniformity of the heating type gas sensor can be improved, and the heating power consumption can be reduced.

A semiconductor device and a method of manufacturing the same are disclosed. According to embodiments, a semiconductor device can include a substrate, a buried oxide layer, a channel portion, a source / drain portion, and a gate stack. The channel portion includes a plurality of semiconductor layers stacked above the buried oxide layer spaced apart from each other, each of the plurality of semiconductor layers including a shell portion and a core portion. The shell portion is a doped region in the semiconductor layer, the shell portion having a doping type opposite to a doping type of the source / drain portion, and the shell portion is disposed between the core portion and the gate stack, and / or the shell portion encloses the core portion.

This invention relates to a lithium niobate electro-optic modulator, its fabrication method, and its application. The lithium niobate electro-optic modulator, from bottom to top, comprises a ground electrode, a substrate layer, a buried oxide layer, a lithium niobate waveguide, and a high-dielectric-constant cladding. Symmetrically distributed optical isolation trenches are arranged on both sides of the lithium niobate waveguide. The high-dielectric-constant cladding includes a first cladding and a second cladding from the inside out, wherein the dielectric constant of the first cladding is less than that of the second cladding. The number of high-dielectric-constant cladding layers is ≥2. The lithium niobate electro-optic modulator also includes a signal electrode embedded within the high-dielectric-constant cladding and located above the optical isolation trenches. The synergistic effect of the optical isolation trenches and the high-dielectric-constant cladding in this invention enables the lithium niobate electro-optic modulator to possess not only high modulation efficiency but also high bandwidth. Furthermore, the lithium niobate electro-optic modulator of this invention exhibits excellent power tolerance.

The invention relates to a silicon-on-insulator semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; the buried oxide layer is arranged on the substrate; the first device region and the second device region are arranged on the buried oxide layer; a trench disposed between the first device region and the second device region; the device diaphragm fills the groove and insulates the first device region and the second device region, the side wall of the groove is determined by the first trap of the first device region, the bottom surface of the groove is determined by the buried oxide layer, and the bottom surface of the groove is determined by the second trap of the second device region. A portion of the first well in contact with the buried oxide layer includes a recessed portion recessed toward the sidewall of the trench.

A photodiode includes an SOI substrate, a rib waveguide structure, a Ge+-implanted region, and first and second LTO layers. The SOI substrate includes a buried oxide layer and a silicon layer. The rib waveguide structure is formed in the silicon layer. The Ge+-implanted region is formed within the rib waveguide by ion implantation at a dose of 5×1012 to 3×1015 cm-2 to enable all-silicon sub-bandgap linear photodetection at the telecommunications O-and C-bands. The LTO layers define an implantation window aligned with the Ge+-implanted region.

The invention provides a double-layer uniform emission grating antenna structure for an optical phased array. Comprising a substrate, a waveguide layer and a cladding, the SOI substrate comprises a substrate layer and a buried oxide layer, the waveguide layer comprises a lower-layer silicon waveguide and an upper-layer silicon nitride waveguide, the upper-layer silicon nitride waveguide is provided with a grating structure formed by etching in the light propagation direction, and the grating structure is formed by modulating the transverse width of an etching area and the grating duty ratio. And near-field uniform radiation of light energy in the waveguide is realized, so that a fishbone-like grating antenna is formed. According to the double-layer grating structure provided by the invention, the characteristics of strong light limitation of the silicon waveguide and weak disturbance of full etching of the silicon nitride waveguide are utilized, the etching difficulty is reduced, the effective length of the grating is effectively prolonged, so that the far-field emission angle of a light beam is reduced, the wavelength tuning efficiency and the upward diffraction efficiency are relatively high, the structure is simple, and the manufacturing difficulty is relatively low.

According to the bonding wafer and the forming method thereof provided by the invention, in the forming method of the bonding wafer, when an ion implantation process is executed, a set temperature difference exists between the temperature of the marginal region of the device substrate and the temperature of the central region, so that ion implantation damage of the marginal region of the device substrate can be self-repaired; the ion implantation damage density of the edge region is reduced; bonding the supporting substrate and the device substrate, wherein the buried oxide layer is located between the device substrate and the supporting substrate; a lift-off transfer process is performed to lift off a portion of the thickness of the device substrate along the ion implanted layer. Since the ion implantation damage density of the edge region is reduced, the propagation direction of the conduction wave of the stripping interface during layer transfer can be optimized when the stripping transfer process is executed, the edge region is prevented from being transferred along the radial direction, the damage of the edge region is reduced or avoided, and the performance of the device is improved. And therefore, the problems of silicon island defects and film layer falling in the edge area can be avoided.

This application provides a gradient-doped ferroelectric thin film device and its fabrication method, relating to the field of optoelectronic device technology. The gradient-doped ferroelectric thin film device comprises, from bottom to top, a substrate, a buried oxide layer, a buffer layer, and a ferroelectric thin film material layer; the ferroelectric thin film material layer is doped with impurity ions, with the doping concentration of the impurity ions increasing sequentially from bottom to top. This application, by employing a bottom-up incremental gradient doping design, optimizes the interface defects and internal stress of the ferroelectric thin film, overcomes the problem of lattice mismatch between ordinary ferroelectric thin films and the substrate layer, achieves improved crystal quality and enhanced electro-optic coefficient, and effectively improves the electro-optic effect.

The application is a sensor based on a continuous domain bound state subwavelength grating racetrack resonator, and the device structure is sequentially from bottom to top: the first layer is intrinsic silicon substrate (1), the second layer is buried oxide layer (2), the third layer is silicon nitride film (3), and the fourth layer is racetrack resonator (4), which comprises racetrack micro-ring (4.1), bus waveguide (4.2) and grating coupler (4.3). The application realizes high-quality-factor light confinement propagation by designing subwavelength grating structure with a period less than the wavelength of light and parameters of the racetrack resonator on the waveguide supporting continuous domain bound mode, and is further applied as a sensor. The application has many advantages such as high throughput, high detection sensitivity, high quality factor, simple structure, easy manufacturing and the like, and application as a refractive index sensor or a biological sensor can provide a solution for fast, portable and cost-effective medical detection.

An edge coupler has a wide end, a narrow end, and a tapering thickness. The narrow end is coupled to a waveguide in a photonic integrated circuit (PIC). The wide end is coupled to an optical transmitter or receiver. The edge coupler thickens by tapering downward into the buried oxide layer of a BOX substrate. An upper surface of the edge coupler may be planar. A pedestal may be formed in the oxide layer so that a laser diode mounted on the pedestal will be vertically aligned to the edge coupler. Alternatively, the pedestal may be formed in a substrate under the oxide layer so that the core of an optical fiber mounted on the pedestal will be vertically aligned to the edge coupler. The pedestal may be in a cavity that facilitates horizontal alignment between the laser diode, optical fiber, or other such device and the edge coupler.

An integrated circuit (IC) is described. The IC includes a substrate supporting a buried oxide (BOX) layer. The IC also includes a first-type semiconductor layer on the BOX layer. The IC further includes an oxide layer on the first-type semiconductor layer. The IC also includes a second-type semiconductor layer on the oxide layer, in which a perforated portion of the first-type semiconductor layer is exposed through an opening in the second-type semiconductor layer and the oxide layer. The IC further includes a contact between the first-type semiconductor layer and the second-type semiconductor layer. The IC also includes the BOX layer defining a cavity and partially in the substrate.

The invention provides an FDSOI device integrated with a surrounding gate and a manufacturing method of the FDSOI device, which can be applied to the technical field of semiconductors. The semiconductor device comprises an on-insulator semiconductor substrate which comprises a buried oxide layer and a semiconductor layer which is arranged on the buried oxide layer and is adjacent to the buried oxide layer; a channel portion on the semiconductor-on-insulator substrate including a semiconductor layer; the side wall is arranged on the side wall of the grid electrode, the grid electrode comprises a work function metal layer and a grid conductor layer on the work function metal layer, and the work function metal layer extends from the top surface of the semiconductor layer to the opposite side wall of the semiconductor layer in the first direction along the first direction and further extends to the bottom surface of the semiconductor layer; the source / drain layers are located on the two opposite sides of the grid electrode in the second direction intersecting with the first direction, and the side walls are located between the source / drain layers and the grid electrode.

An optical device and a method for forming the optical device, the structure comprising: a substrate, the substrate comprising a first substrate, a buried oxide layer on the first substrate, and a second substrate on the buried oxide layer; a first waveguide in the second substrate and first grooves on both sides of the first waveguide; a second waveguide in the second substrate and second grooves on both sides of the second waveguide, the second grooves having a depth greater than that of the first grooves; a third waveguide in the second substrate and third grooves on both sides of the third waveguide, the third grooves exposing a surface of the buried oxide layer, the third waveguide comprising a third starting region, a projection of the third starting region on a surface of the substrate being a triangle. The structure can effectively reduce return loss.

This invention provides a double-sided deep silicon etching method and a MEMS device. The double-sided deep silicon etching method includes: providing an SOI substrate, on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed; performing a first deep silicon etching on the top silicon layer to form multiple blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, the protective layer being deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the protective layer deposition, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer. The double-sided deep silicon etching method provided by this invention can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

This invention discloses a single-pole double-throw switch circuit based on an enhancement-mode GaN HEMT integrated device, belonging to the field of radio frequency integrated circuits. It includes first and second switching units integrated on a high-resistivity SOI substrate. Each unit is composed of series and parallel connection of enhancement-mode GaN HEMTs. The device employs a finned active region combined with a gate-around structure, and a p-type doped layer is provided under the gate to achieve normally-off characteristics. A deep trench isolation structure penetrating to the buried oxide layer and having a recessed bottom is provided between adjacent devices. The circuit also includes an auxiliary RC linearization branch. This invention can enhance channel control and reduce on-resistance by using a gate-around structure, and significantly improve high-frequency isolation by utilizing deep trench isolation and cutting off parasitic paths with the SOI substrate. Simultaneously, the RC branch improves linearity under high power, achieving single positive power supply logic control, thus improving the integration and communication reliability of the RF front-end.

The invention relates to an SOI-LIGBT device integrated with a double-clamping MOSFET, and belongs to the technical field of semiconductor devices. The device comprises a cathode P + region, a cathode P-well region, a cathode N + region, a drift region, an anode N-buffer region, an anode P + region, an anode N + region, a clamping N + 1 region, a clamping N + 2 region, a forward clamping gate oxide layer, a reverse conducting gate oxide layer, a main gate oxide layer, a silicon dioxide buried oxide layer and a substrate. Double NMOS (N-channel metal oxide semiconductor) are integrated at an anode of the device and share a clamping N + 1 region and a clamping N + 2 region, one NMOS is used for clamping the anode N + region and the anode N-buffer region when the device is in forward conduction, so that a parasitic PNP triode of the IGBT device can be normally conducted, the problem of reliability of voltage turn-back caused by a traditional anode short circuit LIGBT is solved, the other NMOS plays a role in reverse conduction, and the reliability of the device is improved. And the two NMOSs can be completed by the same process step in the process, so that the process cost is not increased too much.

A semiconductor structure includes a SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer. A circuit element is disposed on the device layer and surrounded by a trench isolation region in the SOI substrate. A buried power rail is embedded in the trench isolation region and the buried oxide layer. The buried power rail is isolated from the device layer by the buried oxide layer and a trench-filling oxide in the trench isolation region.

Photonic Integrated Circuit comprising a stacking of layers comprising: a substrate defining a plane and a stacking direction perpendicular to said plane, a buried oxide layer provided on top of said substrate, a patterned layer of electro-optic material comprising at least one optical waveguide of said electro-optic material, provided on top of said buried oxide layer, a first patterned metal layer comprising a first group of metallic structures, provided on top of said electro-optic material and / or said buried oxide layer, a dielectric cladding volume, provided on top of said buried oxide layer, said patterned layer of electro-optic material and said first patterned metal layer, a second patterned metal layer comprising a second group of metallic structures embedded in said dielectric cladding volume, wherein there is at least one electrical connection between at least two metallic structures from said first and second groups through at least one via, characterized in that said second patterned metal layer is provided at a distance along the stacking direction between 1 and 2.5 micrometres from said at least one optical waveguide.