95 results about "Impurity diffusion" patented technology

The present invention is applicable to the technical field of solar cells, and provides a solar cell, a passivated contact structure thereof, a battery module and a photovoltaic system. The passivated contact structure of the solar cell includes a first passivation layer, a first doped polysilicon layer, a first barrier layer, and a second doped polysilicon layer that are sequentially stacked on the surface of a silicon substrate. The doping polarity of the first doped polysilicon layer is the same as that of the second doped polysilicon layer. Among them, the thickness of the first passivation layer is greater than the thickness of the first barrier layer. The passivated contact structure of the solar cell provided by the present invention adds a first barrier layer and a second doped polysilicon layer, and uses the first passivation layer and the first barrier layer to jointly block the diffusion of impurities into the interior of the silicon substrate, reducing the inward diffusion of impurities into the silicon substrate, which can significantly improve the passivation effect of the solar cell, thereby improving the battery efficiency.

A manufacturing method of a semiconductor device includes a step of preparing a semiconductor substrate having a first main surface and a second main surface, a step of forming a recess in the first main surface and embedding an insulating film in the recess, a step of forming a polysilicon film on the insulating film, a step of forming an interlayer insulating film on the first main surface so as to cover the insulating film and the polysilicon film, and a step of forming a first contact hole and a second contact hole. The semiconductor substrate has a first impurity diffusion region formed in the first main surface, and a second impurity diffusion region in contact with a portion of the first impurity diffusion region, the portion being closer to the second main surface.

The present invention relates to the technical field of semiconductors, and provides a CS-JL device and a manufacturing method therefor, and an electronic device. In the manufacturing method for the CS-JL device, a Core layer is prepared first; then a dummy gate structure, a sidewall structure, a source, and a drain are prepared; then a Shell layer is prepared by removing the dummy gate structure; and finally a gate structure is formed. This method effectively avoids the impact of high temperatures required during the preparation of the sidewall structure, the source, the drain, etc. on impurity diffusion in a channel region, facilitates accurate control of the doping concentrations and thicknesses of the Core layer and the Shell layer, reduces an off-state leakage current of the CS-JL device, and improves the device performance thereof.

The application relates to a calculation method of a high-temperature alloy impurity diffusion coefficient and an atomic mobility parameter based on a molecular dynamics simulation, which comprises the following steps: parameter setting; model establishment; setting a potential function as a multicomponent EAM alloy potential; energy minimization and setting an initial atomic speed; calculating RDF values of a model system and drawing RDF curves; calculating MSD values of all atoms and respectively outputting MSD values of various atomic groups according to various different metal atom types; defining thermodynamic physical quantity output and commanding each step to output and save; giving a random initial speed to the system, and running under each system in three stages: a temperature rising stage, a temperature keeping stage and continuous temperature keeping and relaxation, and outputting MSD values; calculating the impurity diffusion coefficient of the system based on the MDS values; and taking the measured impurity diffusion coefficient as an input value, and obtaining the atomic mobility parameter through DICTRA software. Compared with the prior art, the application has the advantages of simple method, accurate numerical value and the like.

Embodiments of the present disclosure relate to a semiconductor device. The semiconductor device has a split-gate type MONOS structure using a FinFET, and includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel formation layer formed under a control gate and formed of a semiconductor layer doped with a p-type impurity, and a second channel formation layer formed under a memory gate and formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer formed under the second channel formation layer and having a higher impurity concentration than an impurity concentration of a semiconductor substrate.

A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

1. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and / or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

The invention provides a silicon ultraviolet light photodiode and a manufacturing method thereof. The silicon ultraviolet light photodiode comprises an N-type region which is formed below the upper surface of a silicon substrate and is in contact with the upper surface of the silicon substrate; the P + region is formed below the N-type region and is in contact with the N-type region; the deep N-type well region is formed below the P + region and is in contact with the P + region; the N-type conductive channel is connected to the deep N-type well region and is used for enabling non-ultraviolet current caused by electron-hole pairs formed in the deep N-type well region to flow out; according to the heat treatment process step, the P-type doped impurities in the P + injection region are diffused and compensated for the N-type doped impurities in the N-type injection region, so that the depth of the N-type region is controlled to be the preset depth, and the ultraviolet light sensitivity is enhanced.

The invention relates to an extended wavelength InGaAs detector structure and a preparation method thereof. The detector comprises a substrate, an epitaxial structure grown on the substrate and a metal electrode connected with the epitaxial structure, the epitaxial structure comprises an N-type lattice matching buffer layer, an N-type component gradient buffer layer, an intrinsic absorption layer, an i-type tunneling passivation layer and a P-type contact layer which are sequentially grown on the substrate and are in lattice matching with the substrate; the i-type tunneling passivation layer covers the intrinsic absorption layer, and the P-type contact layer is located in a partial region of the upper surface of the i-type tunneling passivation layer. The planar InGaAs detector structure can be obtained without an impurity diffusion method, and the passivation contact layer is formed by the i-type tunneling passivation layer and the P-type contact layer which are sequentially epitaxially grown, so that the interface passivation effect is enhanced.

The invention provides a semiconductor light-receiving element and a method for manufacturing the semiconductor light-receiving element. The semiconductor light-receiving element has both capacitance and dark current values and has a large breakdown voltage. A semiconductor light receiving element according to the present invention includes an n-type InP substrate, a buffer layer on the n-type InP substrate, an n-type InGaAs light absorbing layer on the buffer layer, and an InP window layer on the n-type InGaAs light absorbing layer, and is characterized in that a p-type impurity diffusion region reaching an upper portion of the n-type InGaAs light absorbing layer is formed in the InP window layer, and an average n-type impurity concentration of the n-type InGaAs light absorbing layer is 2.5 * 1014 / cm3 or more and 1.0 * 1015 / cm3 or less.

The application relates to a process for improving the uniformity of a selective window diffusion of a wafer, comprising the following steps: depositing a diffusion mask on the surface of the wafer; photoetching to form a diffusion window and a diffusion ring surrounding the diffusion window on the surface of the diffusion mask; and diffusing impurities in the diffusion window and the diffusion ring to form a diffusion region. By adding the diffusion ring around the diffusion window, the diffusion ring plays an auxiliary diffusion role, the position and size of the auxiliary diffusion ring of different regions of the pixel are adjusted, the diffusion depth of different regions of the wafer is corrected and compensated, the impurity diffusion depths of different regions of the wafer are close to uniform, and the consistency of each unit in the wafer of a prepared single-tube device is improved or the consistency of the performance of each pixel of an array chip is improved.

The present disclosure discloses a gate-all-around field effect transistor which not only can suppress the occurrence of punch through in the substrates and direct leakage of current from the source region / drain region into the part under the channels, but also can facilitate heat release of the substrate, and minimizes the occurrence of device defects due to misalignment between the trench inner spacers and the device by forming trench inner spacers (TISs) and thus preventing source region / drain region impurities from diffusing into the substrate, and a method for manufacturing the same.

A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first impurity region, a gate insulating pattern, a second conductive pattern, and a second impurity region. Each semiconductor structure includes a first semiconductor pattern having a linear shape extending along a first direction and a second semiconductor pattern protruding from the upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other along a first direction perpendicular to a second direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities.

This invention provides a boron nitride crucible and a method for real-time monitoring of impurity release, relating to the field of boron nitride crucible technology. The boron nitride crucible of this invention includes a crucible substrate, the inner surface of which is covered with a barrier layer. An impurity trap region is formed inside the crucible substrate by doping with an impurity-capturing material. This impurity trap region is used to capture impurities diffusing from the crucible substrate. The boron nitride crucible of this invention aims to solve the problem of continuous release of inherent trace impurities during long-term use of boron nitride crucibles in molecular beam epitaxy (MBE) processes, leading to a decrease in epitaxial film purity and affecting device performance and yield. It can effectively suppress impurity diffusion, thereby improving crucible purity and epitaxial film quality.

The present disclosure is applicable to the technical field of solar cells, and provides a solar cell, a solar cell passivation contact structure, a cell assembly, and a photovoltaic system. The solar cell passivation contact structure comprises a first passivation layer, a first doped polysilicon layer, a first barrier layer, and a second doped polysilicon layer that are sequentially stacked on the surface of a silicon substrate; the doping polarity of the first doped polysilicon layer is the same as the doping polarity of the second doped polysilicon layer; and the thickness of the first passivation layer is greater than the thickness of the first barrier layer. The solar cell passivation contact structure provided by the present disclosure is additionally provided with a first barrier layer and a second doped polysilicon layer, and a first passivation layer and the first barrier layer are used to jointly prevent impurities from diffusing into a silicon substrate, so that the inward diffusion of the impurities into the silicon substrate is reduced, and thus the passivation effect of the solar cell can be significantly improved, thereby improving the cell efficiency.

The application discloses a device and method for detecting hydrogen impurity content in a pipeline, and relates to the technical field of hydrogen detection.The application uses a time-domain dynamic characteristic analysis algorithm, utilizes the difference between fluid pressure disturbance and impurity diffusion adsorption in the time response scale, accurately separates the high-frequency transient fluctuation characteristics caused by piston mechanical vibration from the original signal, and effectively filters out the interference caused by flow rate and pressure pulsation.Meanwhile, an adaptive model containing mechanical friction hysteresis logic is constructed, which can not only lock and inhibit the false drift of the dead zone state of the piston caused by static friction force, but also can smooth and repair the elastic overshoot generated in the moment when the piston breaks the static friction force, and deeply compensate for the hardware physical defects, so that the device can still output the detection results with high signal-to-noise ratio and truly reflecting the impurity concentration without pursuing extremely high mechanical processing precision.

A semiconductor device includes one or more LDMOS transistors and a semiconductor substrate having an upper surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed in the semiconductor substrate at the upper surface; a plurality of drain layers formed in the semiconductor substrate at the upper surface; and a plurality of insulating films formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extend along a first direction in plan view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in plan view while interposing a gap between two adjacent impurity diffusion layers among the plurality of impurity diffusion layers.

The invention discloses an all-around gate field effect transistor and a method for manufacturing the all-around gate field effect transistor. According to the invention, the TIS is formed to prevent source / drain impurities from diffusing into the substrate, so that punch-through at the bottom of the substrate and direct electric leakage of the source / drain at the bottom of the channel are inhibited, heat dissipation is facilitated, and device defects caused by misalignment between the TIS and the device are minimized.

It is prevented that charge carriers flow from a diode region into an IGBT region during diode recovery, concentrate in a boundary portion, and thereby cause device breakage. In a semiconductor device having an IGBT region 4, a diode region 5, and a wiring region 6 on the same chip, the wiring region 6 has a gate runner 7 for supplying a gate potential to a trench gate electrode 20, a well layer 28 having a greater impurity diffusion depth than a trench 19, and a plurality of first contact regions 33 electrically connecting the well layer 28 and an emitter electrode 21, and an area of the first contact region 33 in a boundary region vicinity 10 near a boundary portion 9 between the IGBT region 4 and the diode region 5 is larger than an area of the first contact region 33 at a location remote from the boundary region vicinity 10. Position.

Provided is a highly efficient crystalline silicon solar cell having a high open circuit voltage (Voc) and a fill factor (FF). A solar cell according to the present invention comprises: a crystalline silicon substrate (1) including an impurity diffusion layer; a passivation film (2) disposed on at least a portion of the impurity diffusion layer of the substrate (1); the solar cell includes a substrate (1), a passivation film (2) including silver (Ag), and an electrode (20) including silver (Ag) and disposed on at least a portion of the passivation film (2), the solar cell further includes at least one AgSi region (30) disposed on at least a portion between the electrode (20) and the substrate (1), and the AgSi region (30) includes at least one AgSi region (30) having a depth of 100 nm or more. In a scanning electron microscope photograph of a 5.7 [mu] m * 3.9 [mu] m cross section including the AgSi region (30) of the solar cell, the remaining rate of the passivation film (2), which is the ratio of the remaining length of the passivation film (2), is 10-90%.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a pad barrier layer caps a pad of a piezoelectric device. The pad barrier layer is configured to block hydrogen ions and / or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and / or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.

The present invention discloses a micro-LED and a preparation method thereof, which is applied to red light micro-LED and relates to the field of diode technology. The micro-LED includes a substrate; a red light epitaxial preparation layer, an N-type Indium substrate are sequentially provided on the substrate. b Ga 1‑b N / GaN layer, light-emitting layer, electron blocking layer, P-type In f Ga 1‑f N layer and contact layer; a waveguide layer is provided between the light-emitting layer and the electron blocking layer, and the waveguide layer is In e Ga 1‑e The present invention can solve the technical problem in the prior art that impurities in the epitaxial layer diffuse into the light-emitting layer, resulting in low luminous efficiency.

Provided is a semiconductor device in which, even if the silicon-based semiconductor material is different, the on-off loss can be made the same if the on voltage is the same. The present invention also relates to a manufacturing method of a semiconductor device. The semiconductor device according to the present invention includes: a semiconductor substrate having a first main surface and a second main surface; a drift layer of a first conductivity type formed on the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the first main surface side of the drift layer; and a buffer layer of the first conductivity type formed on the second main surface side of the drift layer, the peak impurity concentration of which is higher than that of the drift layer, the drift layer having: a first well whose energy level is lower than that of the conduction band bottom by 0.246 eV; a second well whose energy level is lower than that of the conduction band bottom by 0.349 eV; and a third well whose energy level is lower than that of the conduction band bottom by 0.470 eV, the well density of the second well being greater than or equal to 2.0 x 1014 cm-2. 11 ‑3 ​​

Apparatus and associated methods relate to a thermoelectric device having a superconducting generator ring. In an illustrative example, a thermoelectric device may include a differential generator supply and a thermoelectric generator ring. The thermoelectric generator ring, for example, may be configured to generate an electric current based on a differential temperature received from the differential temperature supply. For example, the thermoelectric generator ring may include a number of thermoelectric coupons forming a ring on a horizontal plane. Each of the thermoelectric coupons may include an n-type impurity diffused silicon semiconductor (IDSS) and an p-type IDSS. For example, the impurities may be distributed in the IDSS at a predetermined concentration distribution, at which a forward bias voltage of the IDSS is below a predetermined target voltage (e.g., 20 mV) Various embodiments may advantageously generate a low-voltage loss high electric current based on an applied temperature differential at the thermoelectric coupons.

The application discloses a semiconductor device and a manufacturing method thereof. The doping concentration of a P column of an epitaxial layer of the semiconductor device near a substrate part is greater than the doping concentration of an N column. Thus, under high-temperature processes such as annealing and oxidation, part of impurities in the substrate diffuse to the P column at the bottom of the N column region epitaxial layer, and the doping concentration of the P column is equivalent to the doping concentration of the N column, so that the positive carriers and the negative carriers of the P column and the N column are as possible as possible to be exhausted to each other at the bottom of the epitaxial layer, and the performance of the semiconductor device is further improved.

The application provides an antimony impurity doped wafer and a preparation method thereof. A double-temperature-zone method is used to control a temperature field of a source region and a diffusion temperature of a wafer region respectively. The accurate control of the temperature of the source region can ensure the volatilization steam concentration of antimony oxide, and the accurate control of the temperature of the wafer region can ensure the longitudinal depth of impurity diffusion while ensuring the wafer surface quality. Compared with the prior art, the application can significantly improve the impurity doping concentration and diffusion depth of the wafer surface, and has obvious effects on reducing the series resistance of the collector of an NPN transistor. Meanwhile, the high-precision doping of the antimony impurity can be realized through one process step, 200 wafers can be processed per furnace, the production efficiency is greatly improved, and the production and processing cost is reduced.

The utility model discloses a stirring device and a crystallization purification system, and solves the technical problems of insufficient impurity diffusion and low segregation purification efficiency in the purification process of a crystallization method in the prior art. A stirring device comprises a support, two lifting mechanisms, a stirring mechanism, a water bath mechanism and a driving mechanism, and the stirring mechanism comprises a stirring column and a spiral piece arranged on the stirring column; the water bath mechanism is correspondingly communicated with the water bath inlet and the water bath outlet; the driving end of the driving mechanism is connected with the stirring column to drive the stirring column to rotate; under the condition that the lifting mechanism drives the stirring mechanism to ascend, the driving mechanism drives the stirring mechanism to rotate in a first direction; and under the condition that the lifting mechanism drives the stirring mechanism to descend, the driving mechanism drives the stirring mechanism to rotate in a second direction opposite to the first direction. According to the stirring column, under the combined action of the lifting mechanism and the driving mechanism, the vertical stirring speed and the rotating speed of the stirring column are controlled, and the stirring efficiency and the segregation effect are improved.

The invention relates to the technical field of non-ferrous metallurgy, and discloses a vertical gradient solidification segregation purification method for 5N ultra-high-purity aluminum, which comprises the following steps: executing an asymmetric thermal field oscillation growth process in a longitudinal thermal gradient field, and controlling a solid-liquid interface to advance upwards at an instantaneous rate in a growth stage, the theoretical thickness of a solute diffusion boundary layer is determined according to the target impurity diffusion coefficient and the instantaneous rate; in the re-melting stage, a directional heat pulse is applied to drive an interface to perform downward re-melting, and the physical re-melting depth is locked in an interval of 1.2-2.0 times of the theoretical thickness. By constructing a dynamic anchoring mechanism of the re-melting depth and the thickness of a diffusion boundary layer, the re-melting depth is forced to physically penetrate through an impurity enrichment layer and communicate with an impurity-poor main melt; deterministic full-layer stripping of interface front-edge impurities is achieved under the variable-rate growth working condition, cleaning failure or excessive ablation caused by scale mismatch is avoided, and the purification efficiency and process stability of ultra-high-purity aluminum are improved.

Provided in the present application is a preparation method for a junction-less transistor. The method comprises: providing a substrate, wherein a buried oxide layer and a semiconductor layer are formed on the substrate; doping the semiconductor layer to obtain a core layer; forming a semiconductor material on the core layer to serve as a shell layer, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer; and forming a source electrode, a drain electrode and a gate electrode on the shell layer. In this way, the core layer can be doped before the shell layer is formed, and when there is a huge concentration gradient between the core layer and the shell layer, accurate doping can be realized, thereby facilitating control over the doping depth and the doping thickness of the core layer in a core-shell structure, reducing negative effects such as impurity diffusion and lattice damage, and thus improving the performance and stability of a device.

A semiconductor device (1) according to one embodiment of the present disclosure comprises: a semiconductor substrate (11) having a first surface (11S1) and a second surface (11S2) facing each other; one or more first impurity diffusion layers (15) that are provided on a first surface (11S1) of the semiconductor substrate (11) and contain diffused impurities of 1E17 / cm < 3 > or more and 1E19 / cm < 3 > or less; one or more second impurity diffusion layers (14) provided on a second surface (11S2) of the semiconductor substrate (11); a metal film (23) provided on the first surface (11S1) side of the semiconductor substrate (11) and electrically connected to the first impurity diffusion layer (15); and a contact layer (22) that is provided between the first surface (11S1) of the semiconductor substrate (11) and the metal film (23), contains an oxide semiconductor having a band gap of 2-6 eV, and is in contact with the first impurity diffusion layer (15).