51 results about "Impurity diffusion" patented technology

The present invention relates to the technical field of semiconductors, and provides a CS-JL device and a manufacturing method therefor, and an electronic device. In the manufacturing method for the CS-JL device, a Core layer is prepared first; then a dummy gate structure, a sidewall structure, a source, and a drain are prepared; then a Shell layer is prepared by removing the dummy gate structure; and finally a gate structure is formed. This method effectively avoids the impact of high temperatures required during the preparation of the sidewall structure, the source, the drain, etc. on impurity diffusion in a channel region, facilitates accurate control of the doping concentrations and thicknesses of the Core layer and the Shell layer, reduces an off-state leakage current of the CS-JL device, and improves the device performance thereof.

The application relates to a calculation method of a high-temperature alloy impurity diffusion coefficient and an atomic mobility parameter based on a molecular dynamics simulation, which comprises the following steps: parameter setting; model establishment; setting a potential function as a multicomponent EAM alloy potential; energy minimization and setting an initial atomic speed; calculating RDF values of a model system and drawing RDF curves; calculating MSD values of all atoms and respectively outputting MSD values of various atomic groups according to various different metal atom types; defining thermodynamic physical quantity output and commanding each step to output and save; giving a random initial speed to the system, and running under each system in three stages: a temperature rising stage, a temperature keeping stage and continuous temperature keeping and relaxation, and outputting MSD values; calculating the impurity diffusion coefficient of the system based on the MDS values; and taking the measured impurity diffusion coefficient as an input value, and obtaining the atomic mobility parameter through DICTRA software. Compared with the prior art, the application has the advantages of simple method, accurate numerical value and the like.

Embodiments of the present disclosure relate to a semiconductor device. The semiconductor device has a split-gate type MONOS structure using a FinFET, and includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel formation layer formed under a control gate and formed of a semiconductor layer doped with a p-type impurity, and a second channel formation layer formed under a memory gate and formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer formed under the second channel formation layer and having a higher impurity concentration than an impurity concentration of a semiconductor substrate.

The invention provides a semiconductor light-receiving element and a method for manufacturing the semiconductor light-receiving element. The semiconductor light-receiving element has both capacitance and dark current values and has a large breakdown voltage. A semiconductor light receiving element according to the present invention includes an n-type InP substrate, a buffer layer on the n-type InP substrate, an n-type InGaAs light absorbing layer on the buffer layer, and an InP window layer on the n-type InGaAs light absorbing layer, and is characterized in that a p-type impurity diffusion region reaching an upper portion of the n-type InGaAs light absorbing layer is formed in the InP window layer, and an average n-type impurity concentration of the n-type InGaAs light absorbing layer is 2.5 * 1014 / cm3 or more and 1.0 * 1015 / cm3 or less.

The application relates to a process for improving the uniformity of a selective window diffusion of a wafer, comprising the following steps: depositing a diffusion mask on the surface of the wafer; photoetching to form a diffusion window and a diffusion ring surrounding the diffusion window on the surface of the diffusion mask; and diffusing impurities in the diffusion window and the diffusion ring to form a diffusion region. By adding the diffusion ring around the diffusion window, the diffusion ring plays an auxiliary diffusion role, the position and size of the auxiliary diffusion ring of different regions of the pixel are adjusted, the diffusion depth of different regions of the wafer is corrected and compensated, the impurity diffusion depths of different regions of the wafer are close to uniform, and the consistency of each unit in the wafer of a prepared single-tube device is improved or the consistency of the performance of each pixel of an array chip is improved.

The present disclosure discloses a gate-all-around field effect transistor which not only can suppress the occurrence of punch through in the substrates and direct leakage of current from the source region / drain region into the part under the channels, but also can facilitate heat release of the substrate, and minimizes the occurrence of device defects due to misalignment between the trench inner spacers and the device by forming trench inner spacers (TISs) and thus preventing source region / drain region impurities from diffusing into the substrate, and a method for manufacturing the same.

A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first impurity region, a gate insulating pattern, a second conductive pattern, and a second impurity region. Each semiconductor structure includes a first semiconductor pattern having a linear shape extending along a first direction and a second semiconductor pattern protruding from the upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other along a first direction perpendicular to a second direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities.

This invention provides a boron nitride crucible and a method for real-time monitoring of impurity release, relating to the field of boron nitride crucible technology. The boron nitride crucible of this invention includes a crucible substrate, the inner surface of which is covered with a barrier layer. An impurity trap region is formed inside the crucible substrate by doping with an impurity-capturing material. This impurity trap region is used to capture impurities diffusing from the crucible substrate. The boron nitride crucible of this invention aims to solve the problem of continuous release of inherent trace impurities during long-term use of boron nitride crucibles in molecular beam epitaxy (MBE) processes, leading to a decrease in epitaxial film purity and affecting device performance and yield. It can effectively suppress impurity diffusion, thereby improving crucible purity and epitaxial film quality.

The present disclosure is applicable to the technical field of solar cells, and provides a solar cell, a solar cell passivation contact structure, a cell assembly, and a photovoltaic system. The solar cell passivation contact structure comprises a first passivation layer, a first doped polysilicon layer, a first barrier layer, and a second doped polysilicon layer that are sequentially stacked on the surface of a silicon substrate; the doping polarity of the first doped polysilicon layer is the same as the doping polarity of the second doped polysilicon layer; and the thickness of the first passivation layer is greater than the thickness of the first barrier layer. The solar cell passivation contact structure provided by the present disclosure is additionally provided with a first barrier layer and a second doped polysilicon layer, and a first passivation layer and the first barrier layer are used to jointly prevent impurities from diffusing into a silicon substrate, so that the inward diffusion of the impurities into the silicon substrate is reduced, and thus the passivation effect of the solar cell can be significantly improved, thereby improving the cell efficiency.

The application discloses a device and method for detecting hydrogen impurity content in a pipeline, and relates to the technical field of hydrogen detection.The application uses a time-domain dynamic characteristic analysis algorithm, utilizes the difference between fluid pressure disturbance and impurity diffusion adsorption in the time response scale, accurately separates the high-frequency transient fluctuation characteristics caused by piston mechanical vibration from the original signal, and effectively filters out the interference caused by flow rate and pressure pulsation.Meanwhile, an adaptive model containing mechanical friction hysteresis logic is constructed, which can not only lock and inhibit the false drift of the dead zone state of the piston caused by static friction force, but also can smooth and repair the elastic overshoot generated in the moment when the piston breaks the static friction force, and deeply compensate for the hardware physical defects, so that the device can still output the detection results with high signal-to-noise ratio and truly reflecting the impurity concentration without pursuing extremely high mechanical processing precision.

A semiconductor device includes one or more LDMOS transistors and a semiconductor substrate having an upper surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed in the semiconductor substrate at the upper surface; a plurality of drain layers formed in the semiconductor substrate at the upper surface; and a plurality of insulating films formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extend along a first direction in plan view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in plan view while interposing a gap between two adjacent impurity diffusion layers among the plurality of impurity diffusion layers.

Provided is a semiconductor device in which, even if the silicon-based semiconductor material is different, the on-off loss can be made the same if the on voltage is the same. The present invention also relates to a manufacturing method of a semiconductor device. The semiconductor device according to the present invention includes: a semiconductor substrate having a first main surface and a second main surface; a drift layer of a first conductivity type formed on the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the first main surface side of the drift layer; and a buffer layer of the first conductivity type formed on the second main surface side of the drift layer, the peak impurity concentration of which is higher than that of the drift layer, the drift layer having: a first well whose energy level is lower than that of the conduction band bottom by 0.246 eV; a second well whose energy level is lower than that of the conduction band bottom by 0.349 eV; and a third well whose energy level is lower than that of the conduction band bottom by 0.470 eV, the well density of the second well being greater than or equal to 2.0 x 1014 cm-2. 11 ‑3 ​​

Apparatus and associated methods relate to a thermoelectric device having a superconducting generator ring. In an illustrative example, a thermoelectric device may include a differential generator supply and a thermoelectric generator ring. The thermoelectric generator ring, for example, may be configured to generate an electric current based on a differential temperature received from the differential temperature supply. For example, the thermoelectric generator ring may include a number of thermoelectric coupons forming a ring on a horizontal plane. Each of the thermoelectric coupons may include an n-type impurity diffused silicon semiconductor (IDSS) and an p-type IDSS. For example, the impurities may be distributed in the IDSS at a predetermined concentration distribution, at which a forward bias voltage of the IDSS is below a predetermined target voltage (e.g., 20 mV) Various embodiments may advantageously generate a low-voltage loss high electric current based on an applied temperature differential at the thermoelectric coupons.

The application discloses a semiconductor device and a manufacturing method thereof. The doping concentration of a P column of an epitaxial layer of the semiconductor device near a substrate part is greater than the doping concentration of an N column. Thus, under high-temperature processes such as annealing and oxidation, part of impurities in the substrate diffuse to the P column at the bottom of the N column region epitaxial layer, and the doping concentration of the P column is equivalent to the doping concentration of the N column, so that the positive carriers and the negative carriers of the P column and the N column are as possible as possible to be exhausted to each other at the bottom of the epitaxial layer, and the performance of the semiconductor device is further improved.

The utility model discloses a stirring device and a crystallization purification system, and solves the technical problems of insufficient impurity diffusion and low segregation purification efficiency in the purification process of a crystallization method in the prior art. A stirring device comprises a support, two lifting mechanisms, a stirring mechanism, a water bath mechanism and a driving mechanism, and the stirring mechanism comprises a stirring column and a spiral piece arranged on the stirring column; the water bath mechanism is correspondingly communicated with the water bath inlet and the water bath outlet; the driving end of the driving mechanism is connected with the stirring column to drive the stirring column to rotate; under the condition that the lifting mechanism drives the stirring mechanism to ascend, the driving mechanism drives the stirring mechanism to rotate in a first direction; and under the condition that the lifting mechanism drives the stirring mechanism to descend, the driving mechanism drives the stirring mechanism to rotate in a second direction opposite to the first direction. According to the stirring column, under the combined action of the lifting mechanism and the driving mechanism, the vertical stirring speed and the rotating speed of the stirring column are controlled, and the stirring efficiency and the segregation effect are improved.

The invention relates to the technical field of non-ferrous metallurgy, and discloses a vertical gradient solidification segregation purification method for 5N ultra-high-purity aluminum, which comprises the following steps: executing an asymmetric thermal field oscillation growth process in a longitudinal thermal gradient field, and controlling a solid-liquid interface to advance upwards at an instantaneous rate in a growth stage, the theoretical thickness of a solute diffusion boundary layer is determined according to the target impurity diffusion coefficient and the instantaneous rate; in the re-melting stage, a directional heat pulse is applied to drive an interface to perform downward re-melting, and the physical re-melting depth is locked in an interval of 1.2-2.0 times of the theoretical thickness. By constructing a dynamic anchoring mechanism of the re-melting depth and the thickness of a diffusion boundary layer, the re-melting depth is forced to physically penetrate through an impurity enrichment layer and communicate with an impurity-poor main melt; deterministic full-layer stripping of interface front-edge impurities is achieved under the variable-rate growth working condition, cleaning failure or excessive ablation caused by scale mismatch is avoided, and the purification efficiency and process stability of ultra-high-purity aluminum are improved.

Provided in the present application is a preparation method for a junction-less transistor. The method comprises: providing a substrate, wherein a buried oxide layer and a semiconductor layer are formed on the substrate; doping the semiconductor layer to obtain a core layer; forming a semiconductor material on the core layer to serve as a shell layer, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer; and forming a source electrode, a drain electrode and a gate electrode on the shell layer. In this way, the core layer can be doped before the shell layer is formed, and when there is a huge concentration gradient between the core layer and the shell layer, accurate doping can be realized, thereby facilitating control over the doping depth and the doping thickness of the core layer in a core-shell structure, reducing negative effects such as impurity diffusion and lattice damage, and thus improving the performance and stability of a device.

This invention provides a suspended crucible-type anti-pollution pharmaceutical testing device for ignition residue, belonging to the technical field of pharmaceutical testing devices. It includes a shell with a holding groove at its center, into which a graphite crucible is inserted; a heating mechanism including a heating block; a triggering mechanism including a pressure switch; and a pressure-holding mechanism including an air inlet with an exhaust fan inside. The device collects waste gas and replenishes inert gas in real time by controlling the pressure changes inside the testing chamber, ensuring that the internal pressure is always higher than the external pressure. This effectively prevents secondary pollution caused by backflow of external air. Simultaneously, the device constructs a unidirectional inert gas circulation system, combined with a multi-layer filtration structure to trap impurities in the waste gas generated during ignition, thus avoiding pollution of the testing environment by impurity diffusion and achieving the recycling of inert gas.

The invention discloses an extremely-low-vibration low-temperature strong-magnetic-field thermostat with a pulse tube refrigerator as a cold source, which comprises a vibration reduction supporting assembly, a vacuum cavity, a sample cavity assembly, a refrigerator assembly and a circulating system assembly, the sample cavity assembly, the refrigerator assembly and the circulating system assembly are connected in the vacuum cavity through a pipeline, a sample table is arranged at the bottom of the sample cavity assembly, and a superconducting magnet surrounds the sample table. According to the device, the separated pulse tube refrigerator is combined with a vibration reduction structure, vibration of the position of the sample table is reduced, an inner cavity and an outer cavity of a sample can be independently detached, an internal circuit penetrates through the outer cavity, heat leakage is avoided, the temperature of the sample table is reduced, and the service life of the sample table is prolonged. The valve block combination is used for effectively reducing sealing surfaces and pipelines and reducing the risk that impurities diffuse to the system, the electromagnetic valve is adopted for achieving automatic cooling, and manual operation of a mechanical valve is not needed.

The present invention provides a semiconductor device that can linearly change the electrical characteristics of an LDMOS transistor with respect to the number of fingers. [Solution] The semiconductor device (DEV1, DEV2, DEV3) comprises at least one LDMOS transistor (Tr) and a semiconductor substrate (SUB) having a top surface (F1). Each of the at least one LDMOS transistor has a plurality of impurity diffusion layers (ILD) formed inside and on the top surface of the semiconductor substrate, a plurality of drain layers (DRA) formed inside and on the top surface of the semiconductor substrate, and a plurality of insulating films (IF) formed on the top surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction (DR1) in a plan view. The plurality of impurity diffusion layers are arranged with a gap between two adjacent impurity diffusion layers along a second direction (DR2) perpendicular to the first direction in a plan view.

The invention provides a CS-JL device, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The preparation method of the CS-JL device comprises the following steps: firstly preparing a Core layer, then preparing a false gate structure, a side wall structure, a source electrode and a drain electrode, then preparing a Shell layer by removing the false gate structure, and finally forming a gate structure. The influence of high temperature required in the preparation process of the side wall structure, the source electrode, the drain electrode and the like on impurity diffusion in the channel region is effectively avoided, the doping concentration and thickness of the Core layer and the Shell layer can be accurately controlled, the off-state leakage current of the CS-JL device is reduced, and the performance of the device is improved.

The present invention suppresses an increase in dark current caused by a defect at an interface of an element isolation layer embedded in a semiconductor layer into which light is incident. The light detection device includes: a first conductivity type impurity diffusion layer provided at an incident position of light; a second conductivity type impurity diffusion layer bonded to the first conductivity type impurity diffusion layer; an element isolation layer embedded in the first conductivity type impurity diffusion layer to isolate the second conductivity type impurity diffusion layer; and a pinning layer disposed at an interface between the first conductivity type impurity diffusion layer and the element isolation layer, the pinning layer being spaced apart from the second conductivity type impurity diffusion layer. The element isolation layer may be continuously disposed around a periphery of the second conductivity type impurity diffusion layer.

In a semiconductor device having a lower electrode on the underside of a semiconductor substrate, the contact between the lower electrode and the semiconductor substrate is improved. [Solution] The method for manufacturing a semiconductor device includes the steps of forming a diffusion source on the lower surface of a semiconductor substrate for diffusing conductive impurities into the semiconductor substrate, and irradiating the lower surface of the semiconductor substrate with laser light via the diffusion source.

The application discloses a heat treatment preparation and plasticity improvement process of a copper rod, relates to the technical field of copper and copper alloy copper material heat treatment, and realizes targeted removal of harmful impurities at the grain boundary by constructing impurity diffusion channels through large processing rate plastic deformation and combining three-section continuous controllable atmosphere heat treatment, so that the impurity removal rate is more than 60%, the problem of intergranular brittle fracture and deep drawing cracking caused by the grain boundary impurity aggregation is solved, the copper rod grain boundary bonding strength is improved by more than 50%, and the multi-pass deep drawing forming yield is improved from about 70% to more than 99%. Meanwhile, the application does not need alloying modification in the smelting stage, avoids the problem of significant decrease in conductivity caused by the introduction of alloy elements, controls the copper rod conductivity loss to be less than or equal to 0.2% IACS through precise control of the micro-oxidation degree and the weak reduction process, and meets the dual requirements of high conductivity and high plasticity.

The invention provides a boron nitride crucible and an impurity release real-time monitoring method, and relates to the technical field of boron nitride crucibles. The boron nitride crucible comprises a crucible base body, the inner surface of the crucible base body is covered with a blocking layer, an impurity trapping area is formed in the crucible base body by doping an impurity trapping material, and the impurity trapping area is used for trapping impurities diffused from the crucible base body. The boron nitride crucible aims at solving the problems that in the long-term use process of the boron nitride crucible in the molecular beam epitaxy technology, inherent trace impurities in the boron nitride crucible are continuously released, consequently, the purity of an epitaxial film is reduced, and the performance and the yield of a device are affected, impurity diffusion can be effectively inhibited, and the effect of improving the purity of the crucible and the quality of the epitaxial film is achieved.

The invention discloses a heat treatment preparation and plasticity improvement process of a copper rod, and relates to the technical field of heat treatment of copper and copper alloy copper materials, an impurity diffusion channel is constructed through large-machining-rate plastic deformation, and targeted removal of grain boundary harmful impurities is realized in combination with three-section continuous controllable atmosphere heat treatment, the impurity removal rate reaches 60% or above, and the plasticity of the copper rod is improved. The problems of intergranular brittle failure and deep drawing cracking caused by grain boundary impurity segregation are solved, the grain boundary bonding strength of the copper rod is improved by 50% or above, the multi-pass deep drawing forming yield is improved to 99% or above from about 70%, meanwhile, alloying modification in the smelting stage is not needed, the problem that the electric conductivity is remarkably reduced due to introduction of alloy elements is avoided, and the method is suitable for industrial production. By accurately controlling the micro-oxidation degree and the weak reduction process, the conductivity loss of the copper rod is controlled to be smaller than or equal to 0.2% IACS, and the double requirements of high conductivity and high plasticity are met.

A semiconductor device comprises one or more LDMOS transistors and a semiconductor substrate with a top surface. Each of the one or more LDMOS transistors comprises: a plurality of impurity diffusion layers formed in the semiconductor substrate at the top surface; a plurality of drain layers formed in the semiconductor substrate at the top surface; and a plurality of insulating films formed on the top surface. Each plurality of impurity diffusion layers, each plurality of drain layers, and each plurality of insulating films extends along a first direction in the top view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in the top view, with a gap inserted between two adjacent impurity diffusion layers beneath the plurality of impurity diffusion layers.

The application provides an N-type monocrystalline silicon wafer and a diffusion gettering treatment method thereof, and belongs to the technical field of solar cells, and comprises the following steps: performing texturing cleaning on the N-type monocrystalline silicon wafer, performing passivation on the N-type monocrystalline silicon wafer after the texturing cleaning, and performing diffusion gettering on the N-type monocrystalline silicon wafer after the passivation. The application can accurately control a thermal field and an air field in a crystal growth process, reduces defects caused by in-situ growth by adopting a passivation technology, realizes high-quality N-type monocrystalline silicon growth, simultaneously develops an N-type monocrystalline silicon wafer diffusion gettering post-treatment technology, optimizes an impurity diffusion heat process, and eliminates problems such as local impurity defects in in-situ growth, impurity pollution and stress defects in a cutting process and the like.

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a silicon substrate, a nitride buffer composite layer, an active layer and a silicon barrier composite layer. The nitride buffer composite layer is arranged above the silicon substrate, the active layer is arranged above the nitride buffer composite layer, and the silicon blocking composite layer is clamped in the nitride buffer composite layer and substantially blocks diffusion of a silicon impurity from the silicon substrate so as to reduce leakage current.