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METHOD OF MANUFACTURING ZnO SEMICONDUCTOR LAYER FOR ELECTRONIC DEVICE AND THIN FILM TRANSISTOR INCLUDING THE ZnO SEMICONDUCTOR LAYER

Provided are a method of manufacturing a ZnO semiconductor layer for an electronic device, which can control the size of crystals of the ZnO semiconductor layer and the number of carriers using a surface chemical reaction between precursors, and a thin film transistor (TFT) including the ZnO semiconductor layer. The method includes: (a) loading a substrate into a chamber; (b) injecting a Zn precursor into the chamber to adsorb the Zn precursor on the substrate; (c) injecting an inert gas or N2 gas into the chamber to remove the remaining Zn precursor; (d) injecting an oxygen precursor into the chamber to cause a reaction between the oxygen precursor and the Zn precursor adsorbed on the substrate to form the ZnO semiconductor layer; (e) injecting the N2 gas or inert gas into the chamber to remove the remaining oxygen precursor; (f) repeating steps (a) through (e); (g) repeatedly processing the surface treatment of the ZnO semiconductor layer using O2 plasma or O3; (h) injecting the N2 gas or inert gas into the chamber to remove the remaining oxygen and Zn precursors; and (i) repeating steps (a) through (h) to control the thickness of the ZnO semiconductor layer. In this method, a transparent TFT is formed using a transparent substrate to enable manufacture of a transparent display device, and a flexible display device can be manufactured using a flexible substrate. Also, the crystallinity of the ZnO semiconductor layer can be increased to improve the mobility of a TFT, and the number of carriers can be controlled to reduce a leakage current. Therefore, a ZnO semiconductor having excellent characteristics can be manufactured.
Owner:ELECTRONICS & TELECOMM RES INST

Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories

A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.
Owner:PROMOS TECH INC
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