15results about How to "High carrier mobility" patented technology

The invention provides a perovskite laminated cell and a preparation method thereof. The perovskite laminated cell comprises a bottom cell, a tunneling composite layer and a perovskite top cell which are sequentially laminated, the tunneling composite layer comprises a first TCO layer and a second TCO layer which are stacked in sequence; the first TCO layer contains a hydrogen element; the surface of the second TCO layer is provided with hydroxyl groups; the perovskite top cell comprises a first charge transport layer, a perovskite light absorption layer, a second charge transport layer and an electrode which are stacked. The first charge transport layer is connected with the second TCO layer, the first charge transport layer is provided with a passivation group, and the passivation group and a hydroxyl group on the surface of the second TCO layer form a covalent bond. According to the invention, under the synergistic effect of the first TCO layer and the second TCO layer, efficient tunneling recombination can be realized, and the stability and efficiency of a cell device are greatly improved.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor columns; forming first word lines, each first semiconductor column being connected with a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor columns, the first semiconductor columns and the second semiconductor columns corresponding to each other; and forming second word lines and second bit lines, each second semiconductor column being connected with a corresponding second word line and a second bit line, so as to form a 2T0C semiconductor structure, and the capacitor process in the manufacturing process of the semiconductor structure can be simplified.

The application discloses a kind of transparent conductive heating material and preparation method thereof, belong to conductive heating material technical field, can solve the problems of high surface resistance, low light transmittance, poor temperature uniformity and short service life of existing conductive heating material.The preparation method comprises the following steps: S1, pretreatment is carried out to the substrate to obtain the treated substrate;S2, depositing buffer target material on the treated substrate to form a stress buffer layer;S3, depositing conductive heating target material on the stress buffer layer to form a conductive heating layer; the conductive heating target material is zirconium-doped indium oxide;S4, preparing an electrode layer on the conductive heating layer.The application is used for the preparation of transparent semiconductor heating material.

This invention discloses a class of porphyrin-based A-D-A type polymer photovoltaic materials, their preparation methods, and applications. The invention utilizes a porphyrin-DPP system constructed through Sonogashira coupling, placing the donor unit at the center of the A-D-A structure. This A-D-A structure more effectively enhances the intramolecular push-pull electronic effect, promoting intramolecular charge transfer and thus significantly broadening and redshifting the light absorption range of the polymer. Furthermore, the A-D-A structure facilitates more ordered and compact intermolecular stacking, promoting the expansion of π-π conjugation and potentially increasing the carrier mobility of the material. This lays the material foundation for obtaining higher short-circuit current densities and fill factors in devices.

The application belongs to the field of organic-inorganic heterostructure thin films, and relates to a polymer / inorganic heterostructure composite thin film and a preparation method and application thereof. The composite thin film is formed by compounding PEDOT:PSS and ITO nanocrystals, PEDOT:PSS forms a flexible network skeleton, the growth orientation of ITO nanocrystals is a (222) crystal face, a (400) crystal face or a (211) crystal face, and the ITO nanocrystals are uniformly dispersed and bonded in the PEDOT:PSS network. The flexible organic polymer PEDOT:PSS and the brittle ceramic material ITO are compounded, the surface state and the work function of the two-phase materials are regulated, the heterostructure composite thin film with a molecular-level interface combination is constructed, and the critical mechanical properties, the interface toughness and the electron mobility of the thin film are simultaneously improved, so that the demand of the flexible electronic device for the high-performance and high-reliability thin film material is met.

This invention discloses a perovskite solar cell and its fabrication method. The method includes: spin-coating a mixed solution of lead iodide and HIAM-4024 or HIAM-4025 onto the surface of an electron transport layer, followed by annealing to obtain a lead iodide layer; and spin-coating an organic halide solution onto the surface of the lead iodide layer, followed by annealing to obtain a perovskite layer. This invention introduces HIAM-4024 or HIAM-4025 into the lead iodide layer, allowing high-energy photons to be filtered through HIAM-4024 or HIAM-4025. Through down-conversion, it emits photons in the visible light range, which are further utilized by the underlying perovskite absorber, thereby improving the light energy utilization of the perovskite solar cell. Furthermore, both HIAM-4024 and HIAM-4025 can effectively filter ultraviolet radiation that could damage the device, further enhancing the light energy utilization of the perovskite device.

The application provides a transistor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to improve the on performance of a transistor. The transistor structure comprises a substrate and a shallow trench isolation structure. The substrate comprises a containing groove, a first active region and a second active region. The containing groove is located on opposite sides of the first active region and the second active region. The opposite sides of the first active region comprise a step structure. The shallow trench isolation structure is at least partially arranged in the containing groove and is at least located on the opposite sides of the first active region and the opposite sides of the second active region. One side of the shallow trench isolation structure close to the first active region has a recess, and the recess exposes the step structure of the first active region. One side of the shallow trench isolation structure close to the second active region has a protrusion. The transistor structure is applied to a chip.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; a first oxide semiconductor layer perpendicular to a surface of the substrate, comprising a first channel region and first source-drain doped regions located on opposite sides of the first channel region along an extension direction of the first oxide semiconductor layer; first gates located on at least opposite sides of the first oxide semiconductor layer along any direction parallel to the surface of the substrate, the first gates located on opposite sides of the first oxide semiconductor layer being gate regions, and the first gates further comprising a connecting region connecting the gate regions; and first source-drain electrodes comprising first source electrodes and first drain electrodes located on opposite sides of the first oxide semiconductor layer, the first source-drain electrodes being in contact with the first source-drain doped regions; wherein the first oxide semiconductor layer, the first gates and the first source-drain electrodes constitute a first transistor. At least the performance of the semiconductor structure can be improved while reducing the size of the semiconductor structure.

The application relates to a linear negative temperature coefficient thermistor material. The material takes graphene oxide and a manganese-cobalt-nickel system transition metal oxide as a base material, is doped with urea, melamine, dicyandiamide, thiourea, boric acid or sodium borohydride, and is obtained by hydrothermal synthesis to have the linear negative temperature coefficient thermistor material. The material has obvious NTC performance, and the resistance value thereof changes with temperature in a linear manner. The preparation steps are simple, the process is safe, the cost is low, the performance is stable, and the material is easy to popularize in the industrial field. The material overcomes the process of realizing the compensation of electrical parameters from nonlinearity to linearity by complicated design of a circuit part in the application process of an existing nonlinear thermistor device, and has a larger TCR value compared to a linear negative temperature coefficient thermistor material obtained by only doping modification, and has a good application prospect in the temperature sensing field.

This invention discloses a method for manufacturing a semiconductor device, relating to the field of semiconductor technology, for simultaneously improving the carrier mobility of NMOS and PMOS transistors, both of which have a gate-around-the-loop (GOP) transistor structure. The manufacturing method includes: forming a first GOP transistor on a first well region of a substrate, and forming a second GOP transistor on a second well region of the substrate. The crystal orientation of a first channel region of the first GOP transistor is perpendicular to the crystal orientation of a second channel region of the second GOP transistor. Forming the first GOP transistor on the first well region includes: forming a first stacked structure on the first well region. The first stacked structure includes a pre-formed layer and alternating first and second material layers formed on the pre-formed layer. The second material layer is the topmost layer in the first stacked structure. Each first material layer is laterally thinned so that the width of the remaining portion of each first material layer is equal to the width of the first channel region.

This application discloses a thin film, its preparation method, and an optoelectronic device. The thin film is made of noble metal particles and transition metal oxide nanomaterials. The thin film has pores, and the noble metal particles are at least partially located in the pores. The thin film of this application exhibits high carrier mobility.

The invention provides a growth method of a metal halide single crystal film, which comprises the following steps of: firstly, depositing a layer of blended polymer film with an orthogonal dissolution characteristic on the surface of a metal halide single crystal substrate as a sacrificial layer, and performing solvent treatment to form a self-patterning soft template; and then coating the polymer layer with a precursor solution of a target epitaxy, carrying out nucleation, transverse growth and grain combination to form a uniform and compact single crystal thin film, and completing mechanical stripping and transfer of the epitaxial thin film through a thermal stripping adhesive tape. The growth method provided by the invention has excellent universality, can grow various metal halide single crystal films including lead-based, non-lead-based, alloy and superlattice structures, and has wide adjustability in size and thickness; in addition, the prepared thin film shows high carrier mobility and low trap density which are equivalent to those of blocky single crystals.

Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a source doped region, a drain doped region, and a lightly doped region and an intrinsic region that are arranged adjacent to each other and located between the source doped region and the drain doped region. The lightly doped region is adjacent to the source doped region, and the intrinsic region is adjacent to the drain doped region. A doping concentration of the source doped region and the drain doped region is greater than a doping concentration of the lightly doped region.

This invention discloses an IBC / HBC battery based on a high hole mobility material and its fabrication method. The IBC / HBC battery includes: a crystalline silicon substrate having a front and a back side; a first passivation layer on the front side of the crystalline silicon substrate; an antireflection layer on the surface of the first passivation layer away from the crystalline silicon substrate; a second passivation layer on the back side of the crystalline silicon substrate; a hole transport layer including multiple sub-hole transport layers; and an electron transport layer including multiple sub-electron transport layers, the sub-hole transport layers being spaced apart on the surface of the second passivation layer away from the crystalline silicon substrate. The hole transport layer is made of a polymer material. This invention improves the crystallinity of each sub-hole transport layer, thereby significantly improving the carrier mobility and conductivity of each sub-hole transport layer.