1544results about How to "High carrier mobility" patented technology

Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel layer contacting the source and the drain is crystallized. In the method of manufacturing the TFT, the channel layer is formed of an oxide semiconductor, and a metal component is injected into the channel layer so as to crystallize at least a portion of the channel layer contacting the source and the drain. The metal component can be injected into the channel layer by depositing and heat-treating a metal layer or by ion-implantation.

A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Interfaces that are portions of semiconductor structures used in integrated circuits and optoelectronic devices are described. In one instance, the semiconductor structure has an interface including a semiconductor surface, an interfacial layer including sulfur, and an electrically active layer (e.g., a dielectric or a metal). Such an interface can inhibit oxidation and improve the carrier mobility of the semiconductor structures in which such an interface is incorporated. The interfacial layer can be created by exposure of the semiconductor surface to sulfur donating compounds (e.g., H₂S or SF₆) and, optionally, heating.

A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized by that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.

An electrical switching device includes a semiconductor having a channel therein which is proximate to at least on channel tap in an extension region and also to a gate. A conductor (e.g., a metal) is disposed proximate to the extension region but is electrically isolated from both the extension region and the gate (e.g., through the use of one or more insulators). The conductor has a workfunction outside of the bandgap of a semiconductor in the extension region and therefore includes a layer of charge in the extension region. The magnitude and polarity of this layer of charge is controlled through selection of the metal, the semiconductor, and the insulator.

Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the memory cells, and a second substrate including a sense amplifier. Each of the memory cells includes a first transistor, and the sense amplifier includes a second transistor. The second substrate is stacked with the first substrate such that the sense amplifier amplifies data transferred through the bit line from a selected one of the memory cells. The first transistor is lower in carrier mobility than the second transistor.

An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized by that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.

The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, sandwiching the channel region; and a pocket region 40 formed between the source/drain region and the channel region. The well 58 has a first peak of an impurity concentration at a depth deeper than the pocket region 40 and shallower than the bottom of the source/drain regions 60, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions 60.

A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.

Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.

A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

A method for fabricating a thin film field effect transistor is described in this invention. The active layer of the thin film transistor (TFT) is formed by a low cost chemical bath deposition method. The fabrication procedure includes deposition of a metal layer on an insulating substrate, patterning of the metal layer to form a metal gate, formation of the di-electric layer, deposition of the active layer and formation of source and drain contacts.

The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.