108 results about "Charge layer" patented technology

The invention discloses a stress balance InP-InGaAs avalanche photodetector and a preparation method thereof. An n-type InP buffer layer, an unintentionally doped In < 0.53 > Ga < 0.47 > As bottom absorption layer, a plurality of groups of unintentionally doped stress matching InGaAs absorption layers, an unintentionally doped In < 0.53 > Ga < 0.47 > As top absorption layer, an n-type InP charge layer and an unintentionally doped InP cover layer are sequentially grown on an n-type InP substrate; the optimal photosensitive wavelength of the avalanche photodetector is 2.0 microns, and the device can stably work at room temperature at low dark current.

The invention provides an array type composite emitter ionic liquid electrospray thruster containing a far-end electrode, and relates to the technical field of spaceflight thrusters, an insulating material is adopted to process a composite emitter assembly, so that a double charge layer is generated at an ionic liquid electrode component, electrochemical reaction cannot be generated at an inner flow channel of a composite emitter, and the composite emitter assembly is made to be uniform. The problem that an electrochemical reaction product is directly generated in the composite emitter to block an internal flow channel of the emitter is avoided, and through the arrangement of a transverse flow channel, a vertical flow channel and a liquid collecting tank, a zigzag liquid flow channel is formed, so that the electrochemical reaction product generated at the electrode component is more uniform and uniform. When the ionic liquid flows, the ionic liquid is limited at the position of the electrode component by the flow channel wall surface and cannot enter the inlet of the base flow channel of the composite emitter assembly along with the ionic liquid, so that the influence of electrochemical reaction on the work of the composite emitter is prevented.

The invention relates to the field of fiber manufacturing, in particular to a magnetic far-infrared dual-response fiber and a preparation method thereof.The magnetic far-infrared dual-response fiber comprises a polymer matrix and a magnetic far-infrared composite material evenly distributed in the polymer matrix; the magnetic far-infrared composite material comprises a nano ferroferric oxide core body and a zirconium carbide coating layer coating the core body, the interior of the nano ferroferric oxide core is doped with transition metal elements, so that the Curie point temperature of the nano ferroferric oxide core is 40-50 DEG C, and the surface of the nano ferroferric oxide core is modified by a cationic surface active agent to form a positive charge layer; hydroxyl is grafted on the surface of the zirconium carbide material. The Curie temperature of ferroferric oxide is precisely regulated and controlled to range from 40 DEG C to 50 DEG C through transition metal doping, a magnetic-far infrared synergistic energy transfer channel is designed and constructed in combination with a core-shell structure, intelligent response with the far infrared emissivity larger than or equal to 0.90 is achieved under body temperature triggering, and the functional strength and large-scale production feasibility are both achieved.

The disclosure relates to a method of manufacturing an avalanche photodetector (APD) (100). The method comprises: providing a silicon-on-insulator substrate comprising an oxide layer (101) and a silicon layer (102) disposed on the oxide layer, the silicon-on-insulator substrate comprising a central region (110) in which an n+ doped layer (103) is embedded in the silicon layer, an embedded intrinsic layer (104) is overlaying the n+ doped layer and an intrinsic multiplication layer (105) is overlaying the embedded intrinsic layer and the n+ doped layer; forming in the silicon layer on the central region, by a thermal drive-in process, a p+ doped charge layer (106) above the intrinsic multiplication layer, wherein the p+ doped charge layer forms with the embedded intrinsic layer, the intrinsic multiplication layer and the n+ doped layer a PIN junction of the APD which is configured to cause a photoelectric effect to convert light energy to electrical energy; and depositing on the central region a germanium absorption layer (107) overlaying the p+ doped charge layer, the germanium absorption layer being configured to function as a light absorption layer to absorb light.

The invention relates to the technical field of unmanned ship charging devices, in particular to an autonomous charging dock for linkage patrol unmanned ships and a charging method. The charging dock comprises a floating bank layer, a bottom plate layer and a charging layer, the floating bank layer is provided with a floating plate, the floating plate floats on the water surface, a charging notch is formed in one side of the floating plate, lifting mechanisms are arranged on the floating plate on the two sides of the charging notch, and a fixing frame is arranged on the floating plate at the inner end of the charging notch; the bottom plate layer comprises a lifting plate, the lifting plate is located at the charging notch of the floating plate, and the lifting mechanism is in driving connection with the lifting plate; the charging layer comprises a floating electromagnet and a fixed magnetic attraction charging head, the floating electromagnet is installed on the fixing frame in a sliding mode in the vertical direction, and the fixed magnetic attraction charging head is fixed to the end of the fixing frame. The problems that in the prior art, a dock is complex in structure, poor in anti-interference performance, insufficient in charging stability and the like are solved.

A photonic device includes a substrate, a P-type doped component disposed over the substrate, an N-type doped component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. The optical absorption layer is disposed between the P-type doped component and the N-type doped component. The optical absorption layer and the substrate have different material compositions. A charging layer is disposed between the P-type doped component and the N-type doped component. The charging layer has a first side surface that is substantially linear. The first side surface is in direct contact with the optical absorption layer.

To provide, in a device that performs display by applying an electric field to charged material, a structure for reducing after-images and a manufacturing method therefor.SOLUTION: A display device comprises a plurality of pixel electrodes and a charged layer (layer including a charged substance) provided on the pixel electrodes. In end parts of the adjacent two pixel electrodes of the plurality of pixel electrodes, one end has a concave part in an end face direction and the other end has a convex part in the end face direction, and the concave part and convex part form a pair to form a gap between the two pixel electrodes.SELECTED DRAWING: Figure 1

This invention discloses a superlattice multiplication layer avalanche diode and its fabrication method. The single-photon avalanche diode includes a graphene transparent electrode and, from bottom to top, an InP substrate, an n-type buffer layer, a superlattice absorption region, a p-type charge layer, a superlattice gradient region, a superlattice multiplication region, a p-type contact layer with a p-type contact window, and a passivation layer. The graphene transparent electrode is grown on the passivation layer and the p-type contact window, forming an ohmic contact with the p-type contact region. Magnetic metal nanoparticles that generate a local magnetic field are embedded in the superlattice multiplication region. The magnetic metal nanoparticles are uniformly distributed in-plane within a depth range of 5-400 nm from the interface in the light-gathering direction of the superlattice multiplication region. This invention combines the internal bandgap optimization of the superlattice with the external limiting pump capability of graphene to produce a synergistic effect, providing a single-photon avalanche diode with low dark count rate, weak afterpulse effect, high detection efficiency, and the ability to operate at relatively high temperatures.

A semiconductor device includes a substrate, a gate stack structure, and a channel structure. The gate stack structure includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate. The channel structure at least partially penetrates the gate stack structure and extends in one direction. The channel structure includes: a channel layer coupled to the substrate; a ferroelectric layer at least partially surrounding the channel layer and including a ferroelectric material; and a charge-bound layer at least partially surrounding the ferroelectric material and including an insulating material. At least one of a conduction band level or a valence band level of the insulating material is disposed between a conduction band level and a valence band level of the ferroelectric material.

The invention discloses a low-noise near-infrared single-photon avalanche detector and a preparation method thereof, the low-noise near-infrared single-photon avalanche detector comprises an n-type InP substrate, and an InP buffer layer, a GaAs < 0.51 > Sb < 0.49 > absorption layer, an In Ga < 1-a > As Sb < 1-b > energy band gradient layer, a composite charge layer containing an indium quantum dot array, an InP avalanche layer and an i-InP diffusion layer which grow on the front surface of the n-type InP substrate from bottom to top in sequence, the composite charge layer containing the indium quantum dot array comprises an InP gradient charge layer, an In quantum dot deposition layer and an InP constant charge thin layer which are sequentially grown from bottom to top. On the premise of keeping high photon detection efficiency of the detector, the dark counting rate and the post-pulse probability of the detector can be effectively reduced, and the performance and the reliability of the detector are remarkably improved.

The invention discloses a single-photon avalanche detector with high detection efficiency and a preparation method of the single-photon avalanche detector. The single-photon avalanche detector comprises a semi-insulating substrate, an n + InGaAs substrate epitaxial layer, an n + InAlAs substrate epitaxial layer, an i: InAlAs epitaxial multiplication layer, a p + InAlAs charge layer, an InAlAs / InAlGaAs superlattice gradient layer, an InAlGaAs / InGaAs superlattice absorption layer, a p +: InAlAs epitaxial layer and a p +: InP epitaxial layer which are sequentially arranged from bottom to top, the InAlAs / InAlGaAs superlattice gradient layer is arranged in a periodic cycle mode, and the InAlGaAs / InGaAs superlattice absorption layer is arranged in a periodic cycle mode. Compared with the prior art, the quantum efficiency of the device can be improved, the width of a depletion region can be increased, the electric field of the absorption layer is reduced, and the carrier collection efficiency is improved.

The application belongs to the technical field of semiconductor process, and discloses an indium arsenide quantum dot single-photon avalanche diode and a manufacturing method thereof, which comprises a substrate layer, a buffer layer, an N-type indium phosphide doped layer, an intrinsic indium gallium arsenide absorption layer, an N-type indium gallium arsenide phosphorus light-doped gradient layer, an N-type indium phosphide light-doped charge layer, an intrinsic indium arsenide quantum dot avalanche layer and a P-type indium phosphide light-doped contact layer which are sequentially stacked; the quantum dot size of the intrinsic indium arsenide quantum dot avalanche layer ranges from 2 nm to 10 nm. The application can reduce excessive noise, improve the bandwidth of a device and improve the response speed of a diode.

The application relates to the technical field of photoelectric detection, and provides an avalanche multiplication photoelectric detector and a preparation method, the detector comprising a super surface structure, a second doped layer, a first doped layer, a multiplication layer, a charge layer, an absorption layer and a dielectric super surface layer which are arranged in sequence, the super surface structure is arranged on the dielectric super surface layer or arranged on the side surface of the dielectric super surface layer and the absorption layer close to the dielectric super surface layer, and the super surface structure penetrates along the thickness direction of the dielectric super surface layer; the second doped layer is formed in the absorption layer and located on the side of the absorption layer close to the super surface structure. The avalanche multiplication photoelectric detector provided by the application realizes the regulation and control of the phase, amplitude and polarization of the incident light field by integrating the super surface structure on the incident side of the absorption layer, so that the absorption rate of the detector is improved without increasing the thickness of the absorption layer, and the gain of the detector is improved, the device bandwidth is effectively expanded, the time jitter is reduced, and the noise is suppressed.

The invention relates to the technical field of photodiodes, and relates to a photodiode and a preparation method thereof, an active region structure and electronic equipment, so as to obtain a high-quality InyGa1-yAs absorption layer. The photodiode comprises an N-type contact layer, an active region structure and a P-type contact layer which are sequentially stacked, the active region structure comprises a multiplication structure layer, a charge layer, a transition layer and an absorption layer which are sequentially stacked, the absorption layer is an InyGa1-yAs layer, the transition layer comprises N InxGa1-xAs buffer layers, N is a positive integer larger than 1, x is larger than 0 and smaller than 1, and x is larger than 0 and smaller than 1 in the direction from the charge layer to the absorption layer. The content of the In component in the N-layer InxGa1-xAs buffer layer is gradually increased, and the absolute value of the difference between the surface, facing the absorption layer, of the transition layer and the content of the In component in the absorption layer is smaller than or equal to 0.2, so that the InyGa1-yAs absorption layer with higher quality can be obtained, and effective absorption of long-wavelength light is realized.

The invention discloses a self-driven composite marine antifouling coating and a preparation method thereof. The self-driven composite marine antifouling coating comprises a base material, a copper electrode plate and an antifouling coating from bottom to top in sequence, the base material and the copper electrode plate form a friction nano generator; the base material is a glass base material. The preparation method comprises the following steps: respectively preparing the antifouling coating, the glass substrate and the copper electrode plate, and then sequentially adhering together; the invention has the advantages of good dispersibility and better heat-conducting property. According to the invention, the friction nano-generator is formed by the glass substrate and the copper electrode plate, the anti-fouling coating prepared in a matched manner is combined, wave energy near a waterline is collected through the friction nano-generator, and a stable double-charge layer at a contact interface of the coating and water is interfered by a variable electric field formed around the underwater electrode wire; therefore, the formation of a biological membrane in an initial stage is inhibited, and the purpose of effectively hindering the formation of biological pollution is achieved; the antifouling paint has the advantages of being good in antifouling performance and free of environmental pollution.

The application belongs to the technical field of lithium ion battery electrode materials, and discloses a method for in-situ coating of magnesium borate on a lithium ion battery positive electrode material. By adjusting the feeding ratio of a magnesium source and a boron source, and by using the positive charge layer on the surface of the lithium ion battery positive electrode material, the borohydride groups with negative charges dispersed in the solution, and the magnesium ion groups with positive charges, a positive-negative-positive charge distribution layer is constructed. Then, through a hydrolysis reaction, a uniform and complete amorphous magnesium borate coating is in-situ coated on the surface of the positive electrode material, a series of in-situ coating of magnesium borate (Mg2B2O5, Mg3B2O6, MgB4O7) is realized, and a lithium ion battery positive electrode material with good interface stability in air and electrolyte is prepared. The method provided by the application has remarkable effects, simple and efficient steps, low cost, and is easy to realize industrialized preparation.

The invention belongs to the technical field of semiconductors, and particularly relates to an APD chip with an isolation groove and a preparation method of the APD chip. The APD chip provided by the invention comprises a first insulating layer arranged on the upper surface of a cap layer except a photosensitive region; the isolation groove at least simultaneously penetrates through the first insulating layer, the non-photosensitive area of the cap layer, the charge layer and the absorption layer, and the isolation groove surrounds the periphery of the photosensitive area. The isolation groove is arranged around the periphery of the photosensitive area, and the depth of the isolation groove is controlled, so that when light irradiates the passivation area, the APD chip of the detector does not generate a signal or the signal is very small due to the isolation effect of the isolation groove, and laser radar pulse broadening can be effectively inhibited. Therefore, the cost is reduced, and the problem of pulse broadening of the laser radar is solved.

The utility model discloses a semiconductor device. The semiconductor device comprises a substrate; the semiconductor epitaxial layer is positioned on one side of the substrate; wherein the semiconductor epitaxial layer is internally provided with a heterojunction of two-dimensional electron gas; the semiconductor epitaxial layer comprises a gate region and drift regions located on two opposite sides of the gate region; the gate structure is positioned on one side, far away from the substrate, of the semiconductor epitaxial layer and is positioned in the gate region of the semiconductor epitaxial layer; the strain layer is positioned in the drift region of the semiconductor epitaxial layer and the side wall of the gate structure; wherein at least one of the surface, close to one side of the substrate, of the strain layer, the interior of the strain layer and the surface, away from one side of the substrate, of the strain layer comprises a parasitic negative charge layer; the parasitic negative charge layer is used for supplementing electrons to the two-dimensional electron gas. According to the technical scheme provided by the utility model, the dynamic resistance value of the device is reduced, and the working efficiency of the device is improved.

A method of manufacturing a semiconductor device is provided, comprising the steps of: forming a first trapped charge layer on a first oxide layer of a first wafer in a batch of wafers by a deposition process; obtaining a first uniformity profile of the first charge trapping layer; determining first feed-forward compensation information of the first wafer according to one of the first uniformity profile and a target uniformity profile; selecting a first process formula from a plurality of process parameter formulas based on the first feed-forward compensation information; and forming a second oxide layer through a first oxidation process that consumes a portion of the first charge trapping layer according to the first process recipe. According to the method, the manufacturing tools of the current batch are optimized by actively utilizing the data of the previous steps, waste is avoided, and the efficiency is improved.

The invention relates to a high-dispersity irradiation shielding filler, a preparation method thereof and an irradiation shielding composite material. The preparation method comprises the following steps: carrying out oxidation-hydroxylation pretreatment on a composite filler containing a high-atomic-number gamma-ray shielding filler and a neutron absorption filler in an alkaline hydrogen peroxide aqueous solution; mixing and reacting the composite filler with an anionic polyelectrolyte solution to form a first charge layer; reacting the composite filler with a mixed solution of an amino-containing silane coupling agent and polyether amine to form a second charge layer with opposite polarity; and carrying out surface microgelation on the filler by using a multifunctional epoxy cross-linking agent to obtain the high-dispersity irradiation shielding filler. Compared with the prior art, the high-dispersity irradiation shielding filler with the Zeta potential absolute value not smaller than 30 mV is successfully prepared, and the high-dispersity irradiation shielding filler can be further used for preparing an irradiation shielding composite material.

The present application relates to a kind of diamond-based gallium oxide heterojunction avalanche photodetector and its preparation method, adopt p + Diamond substrate, sequentially epitaxial p ‑ Diamond multiplication layer, n ‑ Ga2O3 charge layer, i-Ga2O3 absorption layer and n + Ga2O3 contact layer, form separate absorption multiplication II-type heterojunction mesa structure;Through ICP etching exposure substrate, and utilize BOE wet etching and nitrogen annealing repair side wall damage;Finally, ohmic contact electrode is formed at top and bottom respectively.Under reverse bias, heterojunction built-in electric field and mesa edge local electric field cooperate, realize carrier avalanche multiplication, can realize single-photon level detection to ≤280nm solar blind waveband.Diamond substrate high thermal conductivity significantly inhibits Ga2O3 thermal accumulation, improves device stability and life.Process is fully compatible with MPCVD / MOCVD and standard semiconductor process, applicable to deep ultraviolet weak light imaging and other fields.

This application discloses a lithium cobalt oxide cathode material, its preparation method, and a solid-state battery. The lithium cobalt oxide cathode material includes a lithium cobalt oxide core and a rock salt phase layer and a fast ion conductor layer sequentially coated on the surface of the lithium cobalt oxide core. The rock salt phase layer is made of cobalt oxide, and the fast ion conductor layer is made of Li. x M y O z Wherein, M includes at least one of Sm, Gd, La, Nd, Zr, Nb, and W, and x, y, and z are all greater than 0. This application, by forming a rock salt phase layer and a fast ion conductor layer on the surface of the lithium cobalt oxide core, can weaken the side reactions between the layered lithium cobalt oxide core and the sulfide electrolyte, reduce the impedance introduced by the space charge layer, and improve the interfacial diffusion capability of lithium ions, thereby achieving the effect of reducing interfacial impedance and improving the cycle performance and rate performance of solid-state batteries.

This invention discloses a cerium-doped InP-based single-photon avalanche detector for space communication and its fabrication method. The detector's epitaxial structure, from bottom to top, includes a substrate, an N-type buffer layer, an absorption layer, a band transition layer, an N-type charge layer, an intrinsic multiplication layer, an intrinsic InP layer, and a cerium-doped P-type contact layer. The core innovation lies in the dual radiation-resistant design of the Ce-doped P-type contact layer and the Ce-doped modified stacked passivation film. The fabrication method involves MOCVD epitaxial growth, spin-coating source diffusion to prepare the P-type contact layer, ICP etching and wet repair, magnetron sputtering doping, and electrode fabrication. This invention utilizes Ce's unique electronic structure to suppress radiation-induced defects and combines this with an SACM structure to optimize the electric field distribution, achieving low dark count rate, high detection sensitivity, and excellent neutron radiation resistance. The process is compatible with existing semiconductor production lines and is suitable for wafer-level mass production, meeting the high-reliability single-photon detection requirements of aerospace missions such as space laser communication and quantum key distribution.

Avalanche photodiode designs having separate absorption and multiplication regions are disclosed. The avalanche photodiode designs include a charge layer tailored to allow charge carrier transport from the absorption layer to the multiplication layer and reduce the dark current when the avalanche photodiode is reverse biased.

The invention discloses a flexible InP-based semiconductor film structure and a preparation method thereof, and the structure comprises an InP-based epitaxial wafer and a flexible substrate. The InP-based epitaxial wafer comprises a single-sided polished GaAs substrate, and an AlAs stripping layer, a GaAs buffer layer, a periodic Inx (Al1-yGay) 1-xAs / Al1-zInzAs strain buffer superlattice multiplication layer, an InP charge layer, an (InaGa1-a) (AsbP1-b) energy band transition layer, a GaInAs absorption layer and an AlInAs cap layer which sequentially grow on the front surface of the single-sided polished GaAs substrate from bottom to top, and the flexible substrate is arranged on the front surface of the AlInAs cap layer, so that the GaAs substrate of the InP-based epitaxial wafer is stripped. And further growing a GaAs diffusion layer. By adopting an epitaxial layer stripping (ELO) technology, the hard and brittle SPAD material is changed into a flexible form, and meanwhile, the excellent electrical and optical properties of the SPAD material are still kept.

The present invention provides a gate-all-around transistor device and a method for manufacturing the same. The device comprises: a substrate layer, an insulating layer, a top semiconductor layer, a first gate, a second gate, a source electrode, and a drain electrode. A groove is provided between the insulating layer and the top semiconductor layer, the first gate is provided within the groove, a pre-charge layer is provided on the first surface of the insulating layer where the first gate is not provided, and / or a pre-charge layer is provided on the surface of the semiconductor boss in contact with the insulating layer. By providing a pre-charge layer around the first gate between the top semiconductor layer and the insulating layer, the present invention enables the channel switching of the gate-all-around transistor to be primarily controlled by a gate-all-around, thereby fully leveraging the performance advantages of the gate-all-around transistor. Simultaneously, nanocrystals are formed by sequential ion implantation to further reduce the control of the π-type channel on the device. Furthermore, by cleaning the top semiconductor layer above the groove, the influence of the pre-charge layer on the channel threshold voltage of the gate-all-around is reduced.

The invention provides a negative pole piece and a preparation method thereof and a battery, the negative pole piece comprises a current collector, and a first coating, a second coating and a third coating which are sequentially laminated on at least one side surface of the current collector, a first conductive agent in the first coating comprises SP and / or CNT, and the content of the first conductive agent is less than or equal to 20wt%; the second coating is a silicon-based layer and the third coating is a first graphite layer, or the second coating is a second graphite layer and the third coating is a third graphite layer; an active substance in the silicon-based layer comprises a silicon-based material and a first graphite material, and an active substance in the first graphite layer comprises a second graphite material; the active substance in the second graphite layer comprises a third graphite material, and the active substance in the third graphite layer comprises a fourth graphite material. By adopting the first coating with high cohesiveness and conductivity, the second coating with high energy density and the quick charge layer as the third coating, lithium precipitation and material falling of the negative electrode during quick charge can be reduced, and meanwhile, the capacity is improved.

The invention discloses an InGaAsP SPAD dead pixel suppression structure based on a deep isolation groove tungsten plug. The InGaAsP SPAD dead pixel suppression structure comprises a heteroepitaxial material which sequentially grows on an n + type InP substrate in an epitaxial mode, wherein the heteroepitaxial material comprises an n + type InGaAs etching cut-off layer, an n + type InP contact layer, an i type InGaAsP absorption layer, an n + type InGaAsP electric field modification layer, an n + type InP charge layer, an i type InP multiplication layer and an n type InGaAsP contact layer and is provided with an absorption multiplication separation structure; a Geiger avalanche diode pixel with a Zn doped region is formed on a heteroepitaxial material, a deep isolation groove is prepared around the pixel, a tungsten plug is prepared in the deep isolation groove for filling, an N electrode is prepared on the surface of a tungsten plug filling region, a P electrode is prepared on the surface of the Zn doped region, and the P electrode and the N electrode are coplanarly led to a readout circuit. Electrical isolation is carried out through a switch channel of the reading circuit, and dead pixel suppression is realized. According to the invention, the independent turn-off of the pixels is realized through the switch, and the inhibition effect on very few dead pixels is effectively enhanced.

The application discloses a silicon-based germanium SPAD with compensation doping below a shielding ring and a preparation method, and relates to the technical field of semiconductor optoelectronic devices. The silicon-based germanium SPAD with compensation doping below the shielding ring comprises an N-type silicon substrate, an intrinsic silicon multiplication layer, a P-type silicon charge layer, an intrinsic germanium absorption layer and a P-type germanium anode contact layer from bottom to top, and has a single mesa structure. A P-type shielding ring is arranged on the periphery of the charge layer, and the doping concentration of the shielding ring is higher than that of the charge layer. An N-type compensation doping area is arranged in the silicon substrate directly below the shielding ring, and the doping concentration of the compensation doping area is lower than that of the substrate. The application effectively reduces the dark current through the shielding ring, balances the electric field concentration caused by the shielding ring through the compensation doping area, suppresses the early breakdown, restores the avalanche gain and widens the linear working area, and realizes the balance between low dark current and high gain.