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150 results about "Avalanche multiplication" patented technology

Avalanche multiplication: A current-multiplying phenomenon that occurs in a semiconductor photodiode that is reverse-biased just below its breakdown voltage.

Integrated optoelectronic device with an avalanche photodetector and method of making the same using commercial CMOS processes

An integrated optoelectronic circuit chip for optical data communication systems includes a silicon substrate, at least one MOS field effect transistor (MOSFET) formed on a portion of the silicon substrate, and an avalanche photodetector operatively responsive to an incident optical signal and formed on another portion of the substrate. The avalanche photodetector includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is ionizable by the incident optical signal to form freed charge carriers in the light absorbing region. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth of less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type. The light absorbing region and the light responsive region form a P-N junction at the interface therebetween such that when the light absorbing and light responsive regions are appropriately reverse biased, the freed charge carriers in the light absorbing region are amplified by avalanche multiplication.
Owner:LUCENT TECH INC

Methods and structures for highly efficient hot carrier injection programming for non-volatile memories

A metal oxide semiconductor field effect transistor (MOSFET) in a non-volatile memory cell has a source, a drain and a channel region between the source and the drain, all formed in a substrate of opposite conductivity type to the conductivity type of the source and drain. The MOSFET is programmed by connecting the drain electrode to the supply source of the main voltage, Vcc, provided to said non-volatile memory cell and supplying selected voltages to the source and substrate so as to invert a portion of the channel region extending from the source toward the drain. The inverted portion of the channel region ends at a pinch-off point before reaching the drain. By controlling the reverse bias across the PN junction between the source and the substrate, the pinch-off point of the inversion region is pulled back toward the source thereby to increase the programming efficiency of the MOSFET.
Methods and structures for highly efficient Hot Carrier Injection (HCI) programming for Non-Volatile Memories (NVM) apply the main positive supply voltage Vcc to, the drain electrode of the NVM cell from the chip main voltage supply in contrast to the conventional method using a higher voltage than Vcc. The source electrode and substrate are reverse biased with a differential voltage relative to the drain, while a voltage pulse is applied to the control gate of the NVM cell to turn on the NVM cell for programming. To optimize the programming condition, the source voltage and the substrate voltage are then adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i.e. using a gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage). The substrate voltage to the drain voltage can not exceed the avalanche multiplication junction breakdown for a small programming current during the bias voltage adjustment.
Owner:PEGASUS SEMICON SHANGHAI CO LTD

SPAD with high detection efficiency and low dark count based on standard CMOS process

The invention discloses an SPAD with high detection efficiency and low dark count based on a standard CMOS process. The SPAD is prepared on a P substrate that is provided based on the CMOS process; anN-buried layer is arranged on the P substrate to play an isolation role, the buried N-type injection has the characteristic of inverted doping distribution, the doping concentration increases with the increase of depth, and a virtual protection ring is formed; an N-well region, a P-well region and a heavily doped P+ region are respectively arranged in a diffusion doping region of the N-buried layer, and the N-well region is taken as a component part of a photosensitive PN junction; the P-well region serves as a protection ring; the heavily doped P+ region, a shallow P-well region and the N-type region jointly form a P+P-/N-well photosensitive PN junction, and the combination of two P-type injections with different concentrations form a gradient junction to reduce the dark count of devices; the depletion region of the PN junction is the main occurrence region of avalanche multiplication, and meanwhile, the heavily doped P+ region is also taken as an anode contact region of a photodetector; an N-well contact region is arranged in the N-well region at the edge, and the N-well contact region is a heavily doped N+ region and serves as a cathode contact region of the photodetector.
Owner:TIANJIN UNIV

InP base plane type back incident avalanche optoelectronic diode and manufacturing method thereof

InactiveCN101552304ASuppresses edge breakdownSimple processSemiconductor devicesControl layerProtection layer
The invention relates to an InP base plane type back incident avalanche optoelectronic diode which comprises a substrate, a buffer layer manufactured on the substrate, an absorption layer manufactured on the buffer layer, a transition layer manufactured on the absorption layer, an electric field control layer manufactured on the transition layer and an avalanche multiplication layer manufactured on the electric field control layer, wherein a concave part is disposed on a central area on the avalanche multiplication layer, and the edge of the concave part is of an inverse step-shaped structure; a floating protective ring is manufactured at the outside of the concave part on the avalanche multiplication layer; the concave part comprises a P-type doped layer disposed on the bottom surface of the concave part and a passivation protecting layer disposed on the surfaces of the P-type doped layer and the avalanche multiplication layer, wherein a contact through hole is disposed in the center of the passivation protecting layer, and a P electrode is manufactured at the bottom in the middle of the passivation protecting layer; and an n electrode is manufactured on the back of the substrate, and a light incident window is disposed in the middle of the n electrode.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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