The invention discloses a packaging structure corresponding to
wafer back power supply of a
chip of 2nm and below 2nm. According to the scheme, an adapter plate is arranged on a substrate, and a first
chip with the thickness of 2nm and below 2nm is inversely arranged on the basis of the adapter plate, so that smaller packaging height and smaller physical size are realized. Through the vertical
metal blocks and the transverse
metal blocks, the sectional area of current transmission is increased, the resistance is reduced, and the current transmission efficiency is improved. The vertical
metal blocks and the transverse metal blocks serve as conductive channels and also serve as heat conduction paths, the heat conduction and dissipation capacity is effectively improved, and stable operation of the
chip is guaranteed. Through the arrangement of the flip first chip,
wafer back power supply is realized, the power supply path is shortened, the IR
voltage drop is reduced, and the power supply efficiency is improved. And the vertical metal block is flush with the back surface of the first chip, so that the length of a current transmission path is reduced, the
energy loss and
electromagnetic interference are reduced, the
electrical performance is improved, the uniformity of
current distribution is ensured, and the resistance is further reduced.