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31results about How to "Avoid volume increase" patented technology

Silicon-on-insulator (SOI) structures with step-type buried oxide layers

The invention provides two types of silicon-on-insulator (SOI) structures with step-type buried oxide layers. The first type of SOI structure comprises a P-type semiconductor substrate, a gate insulation layer formed above a P-type channel, a grid electrode formed above the gate insulation layer and a side wall which covers the grid electrode and the side edge of the gate insulation layer, wherein an N-type source region, an N-type drain region, the step-type buried oxide layers positioned in the N-type source region and the N-type drain region and below the P-type channel are formed on the semiconductor substrate; the thicknesses of the buried oxide layers positioned in the N-type source region and the N-type drain region are respectively greater than that of the buried oxide layer positioned below the P-type channel; and a P-type element heavily doped region is arranged in the P-type semiconductor substrate below the corresponding thinner buried oxide layer below the side wall adjacent to one side of the N-type drain region. Different from the first type of SOI structure, the second type of SOI structure is characterized in that the top of the substrate is provided with the N-type doped region, and the source region and the drain region are P-type. By utilizing the technical scheme of the invention, the short channel effect of the existing SOI structures can be solved.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Manufacturing method for silicon-on-insulator (SOI) structure provided with stepped oxidization buried layer

The invention provides two methods for forming a silicon-on-insulator (SOI) structure provided with a stepped oxidization buried layer. The first method comprises the following steps of: providing a first region and a third region used for forming a source region and a drain region respectively, and a P-type semiconductor substrate of a second region on which a grid electrode, a grid electrode insulating layer and a hard mask layer are formed, wherein a BOX layer is arranged in the substrate, and a P-type element heavily-doped region corresponding the drain region is formed below the BOX layer; forming a side wall for covering the hard mask layer, the grid electrode and the grid electrode insulating layer; forming an N-type source region and an N-type drain region; performing oxygen ion implantation on the substrate positioned below the BOX layer corresponding to the source region and the drain region except the side wall; and performing high-temperature annealing to form an oxygen ion implantation region and the BOX layer into a stepped oxidization layer. The other method comprises the following steps of: forming an N-type doped region on the top layer of the substrate; and forming the source region and the drain layer in the doped region. Due to the adoption of the technical scheme provided by the invention, the short-channel effect of an existing SIO structure can be avoided.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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