11 results about "Joint Test Action Group" patented technology

The application provides a control board and a test system. The control board comprises a first debug access port (DAP) connector, a master control chip electrically connected with pins of the first DAP connector, wherein a target pin of the first DAP connector is electrically connected with a 10-pin DAP emulator through a first soldering mode of two resistors, and the target pin of the first DAP connector is electrically connected with a 20-pin joint test action group (JTAG) emulator through a second soldering mode of two resistors. The control board and the test system can realize compatible design of the DAP emulator and the JTAG emulator, meet the test requirements of project development, and solve the problem of adapting to different emulator interfaces.

The present invention relates to a device and a system for debugging a solid state disk device, the device comprising: a joint test action group add-on board; and a Raspberry Pi. The Raspberry Pi comprises a general purpose input output interface coupled to the joint test action group add-on board; and a processing unit coupled to the general purpose input output interface. The processing unit is configured to emulate a plurality of joint test action group commands to the solid state disk device through the general purpose input output interface to dump data generated by the solid state disk device during runtime of the solid state disk device. Using the device as described above can reduce the cost required to debug the solid state disk device.

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

The invention discloses an integrated circuit equipment debugging method and device, equipment and a storage medium, and relates to the technical field of integrated circuit debugging, and the method comprises the steps: monitoring a target joint test action group bus to obtain a target integrated circuit equipment debugging request; analyzing the target integrated circuit equipment debugging request to obtain a target equipment identifier, and performing preset validity verification operation on the target equipment identifier to obtain a verified equipment identifier; matching a target integrated circuit device address corresponding to the target integrated circuit device through a target mapping relation table based on the verified device identifier, and determining a target debugging link according to the target integrated circuit device address; the target debugging link is a link for linking the joint test action group debugging host and the target integrated circuit equipment; and obtaining a target debugging instruction of the target integrated circuit equipment through the target debugging link, and debugging the target integrated circuit equipment based on the target debugging instruction. Therefore, efficient and reliable automatic switching of the JTAG debugging link can be realized.

In an implementation, a method may include receiving an input clock at an input pin of a device, the device having a Joint Test Action Group (JTAG) test access port (TAP). The method may also include counting a first number of cycles of a reference clock using a first counter. The method may furthermore include simultaneously counting a second number of cycles of the input clock received at the input pin using a second counter. The method may in addition include calculating a frequency of the input clock based on the counted first number of cycles of the reference clock, the counted second number of cycles of the input clock, and a frequency of the reference clock.

The invention discloses a JTAG (Joint Test Action Group) dynamic key burning method, which comprises the following steps of: 1) acquiring physical characteristics of a main control chip, and acquiring a unique PUF (Physical Unclonable Function) correction value of equipment; 2) encrypting the obtained PUF correction value, and obtaining an encrypted key stream bound with equipment firmware; 3) calculating a hash value of the encrypted key stream, writing the hash value into an SPI-NOR fusing region, generating a laser fusing path coordinate, and outputting a fusing instruction; 4) positioning a JTAG communication path according to the coordinates of the fusing path; and executing laser fusing operation, after fusing is completed, detecting a path state, generating a corresponding fusing state code, and recording whether fusing succeeds or not. According to the method, the SM4 and the secondary encryption algorithm are combined, a complete security chain from key generation and hardware characteristic binding to physical fusing is constructed, and the security standard of the storage device is met.

The invention relates to the field of circuit board testing, in particular to an automatic switching device and switching method for a multi-processor JTAG debugging mode. A micro control unit MCU; the multi-path electronic switch comprises a plurality of control input ends and a plurality of signal channels, and the plurality of control input ends are electrically connected with GPIO (General Purpose Input / Output) pins of the MCU and are used for receiving level control signals; each processor is provided with a JTAG (Joint Test Action Group) signal pin; jTAG signal pins of the plurality of processors are connected with a plurality of signal channels of the multipath electronic switch; the multipath electronic switch switches the connection state of an internal signal channel by responding to a level control signal, and dynamically reconfigures JTAG signal pins of the plurality of processors into a cascade mode and an independent mode; through cooperative control of the micro-control unit and the multi-path electronic switch, dynamic switching of the multi-processor JTAG between a cascade mode and an independent mode is realized, the debugging efficiency and the system reliability are improved, and the area of a circuit board and interface resources are remarkably saved.

Embodiments of the present application provide an interface calling method, a chip and a computing device. A specific implementation of the method includes: receiving an access request of a first application based on a general interface, the access request being used to access a Joint Test Action Group (JTAG) register; calling an intermediate interface based on the access request, the intermediate interface being used to call a first operation instruction registered in a JTAG structure; and performing an access operation on the JTAG register through a JTAG controller based on the first operation instruction to respond to the access request. Thus, when the JTAG controller or the JTAG register changes, only the first operation instruction needs to be reconstructed to maintain the original general interface and the intermediate interface to respond to the access request, thereby improving the development efficiency of the system and reducing the maintenance cost of the system.

The invention discloses terminal equipment, a debugging system and a vehicle. Physical safety and information safety of the terminal equipment are improved. The terminal equipment comprises a processor 11, an isolator 12 and a Type-C interface 13, wherein the processor 11 is integrated with a JTAG (Joint Test Action Group) interface; a plurality of pins of the JTAG interface are connected to corresponding pins of the Type-C interface 13 according to a pin mapping logic defined by a user; the isolator 12 is connected between the JTAG interface and the Type-C interface 13, and is used for disconnecting the electrical connection between the JTAG interface and the Type-C interface 13 when the pin connection between the JTAG interface and the Type-C interface 13 is short-circuited; a level conversion circuit is integrated on the isolator 12; and among the pins of the JTAG interface and the Type-C interface 13, the pins with pin mapping logic but unmatched electrical characteristics are connected through a level conversion circuit.

The invention discloses a method for realizing SDRAM (synchronous dynamic random access memory) function performance online detection based on a JTAG (joint test action group) tool. The method comprises the following steps: designing an SDRAM function performance test program; wherein the size of a target file of the function performance test program does not exceed the size of a cache with an SRAM mode in the CPU; setting initial address information of a code segment, a static data segment, a data segment and a stack segment in the function performance test program; a CPU emulator is used for controlling a PC pointer value logic address through a JTAG interface so as to complete the skipping function of the PC pointer, and a cache with an SRAM mode in a CPU is switched to the SRAM mode; and loading the function performance test program to a cache with an SRAM mode in the CPU to realize the execution of the test program. According to the method, the problems that the boundary scanning test is low in test efficiency and the internal BIT test is insufficient in test coverage rate are solved, so that the quality and reliability of delivered products are improved.

In an implementation, a method may include receiving an input clock at an input pin of a device, the device having a Joint Test Action Group (JTAG) test access port (TAP). The method may also include counting a first number of cycles of a reference clock using a first counter. The method may furthermore include simultaneously counting a second number of cycles of the input clock received at the input pin using a second counter. The method may in addition include calculating a frequency of the input clock based on the counted first number of cycles of the reference clock, the counted second number of cycles of the input clock, and a frequency of the reference clock.