28 results about "Joint Test Action Group" patented technology

The invention relates to the technical field of circuits, in particular to a memory built-in self-test circuit generation method and device and electronic equipment. The method comprises the following steps: acquiring a parameter configuration file of which the text format is Excel; wherein the parameter configuration file comprises first configuration information of the static random access memory, second configuration information of the joint test behavior organization and an algorithm for detecting a fault in the memory; calculating the matching degree between parameters in each cell in the parameter configuration file and each pre-configured theoretical algorithm; determining a target algorithm based on the matching degree; wherein the target algorithm comprises any one of theoretical algorithms; and inputting the algorithm identifier of the target algorithm and the parameter configuration file into a circuit generation program written by adopting a SpinalHDL programming language, and generating a memory built-in self-test circuit corresponding to the target algorithm.

The application provides a control board and a test system. The control board comprises a first debug access port (DAP) connector, a master control chip electrically connected with pins of the first DAP connector, wherein a target pin of the first DAP connector is electrically connected with a 10-pin DAP emulator through a first soldering mode of two resistors, and the target pin of the first DAP connector is electrically connected with a 20-pin joint test action group (JTAG) emulator through a second soldering mode of two resistors. The control board and the test system can realize compatible design of the DAP emulator and the JTAG emulator, meet the test requirements of project development, and solve the problem of adapting to different emulator interfaces.

The invention provides a JTAG (Joint Test Action Group) switching method based on a programmable logic device, equipment and a product. Relates to the technical field of integrated circuits. The method is applied to a programmable logic device and comprises the following steps: taking a JTAG switching signal transmitted by upstream equipment; in response to the JTAG switching signal, acquiring an in-place signal of downstream equipment; according to the in-place signal, a JTAG signal corresponding to the JTAG switching signal is sent to the downstream device; and the downstream equipment responds to the JTAG signal, so that JTAG switching is realized. By means of the JTAG switching method and device, the effects of simplifying the JTAG switching structure and improving the JTAG switching applicability are achieved.

The present invention relates to a device and a system for debugging a solid state disk device, the device comprising: a joint test action group add-on board; and a Raspberry Pi. The Raspberry Pi comprises a general purpose input output interface coupled to the joint test action group add-on board; and a processing unit coupled to the general purpose input output interface. The processing unit is configured to emulate a plurality of joint test action group commands to the solid state disk device through the general purpose input output interface to dump data generated by the solid state disk device during runtime of the solid state disk device. Using the device as described above can reduce the cost required to debug the solid state disk device.

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

The application discloses an electronic device, a JTAG interface access method and a storage medium, and belongs to the technical field of communication. The electronic device comprises an SPI interface, a GPIO interface and a processor. The SPI interface comprises an SCK pin, an MISO pin and an MOSI pin. The GPIO interface comprises a first GPIO pin. A target JTAG interface comprises a TCK pin, a TDI pin, a TDO pin and a TMS pin. The processor controls the SCK pin to send a TCK signal to the TCK pin, controls the MISO pin to receive a TDO signal output from the TDO pin, and controls the MOSI pin and the first GPIO pin to output a TMS signal to the TMS pin and output a TDI signal to the TDI pin. The electronic device can simulate the JTAG interface by using the SPI interface and the GPIO interface, and access the target JTAG interface.

A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver / transmitter (UART) interface.

The invention relates to a JTAG (Joint Test Action Group) standard pin test system, which is characterized in that slots to be tested are electrically connected with each other to form different serial links to be tested, or adapter cards are electrically connected with each other through respective first JTAG input interfaces and first JTAG output interfaces or second JTAG input interfaces and second JTAG output interfaces to form different adapter card serial links. And the TAP controller provides a corresponding test signal in a JTAG format to the to-be-tested serial connection chain or the adapter card serial connection chain so as to enable the test card to test the JTAG standard pins, thereby achieving the technical effect that the test machine provides a plurality of to-be-tested slots on different to-be-tested machine boards to test the JTAG standard pins.

An SoC includes an execution domain processor for running an execution domain which hosts n partitions by accessing, for each partition, one or more SoC resources; a control point processor that generates control data with n debug enable signals corresponding to the n partitions for controlling access to the SoC resources by identifying at least a first SoC resource that each partition is allowed to access; and an access control circuit to provide, in response to the control data, a dynamic runtime isolation barrier which allows access by the debugging tool to only a specified partition running on the execution domain which has a debug enable signal set to a first active value and prevents access to the other n−1 partitions running on the execution domain, For the partition under debug, the dynamic runtime isolation barrier may block debugger access to selected memory regions accessible by the partition under debug.

The invention relates to a state machine jump control method, a JTAG (Joint Test Action Group) state machine controller, a system and computer equipment. The method comprises the following steps: acquiring a target instruction configured on the upper computer, wherein the target instruction represents a target jump path of a JTAG state machine circuit; analyzing the target instruction to obtain an analysis result supported by the JTAG state machine circuit; and sending the analysis result to the JTAG state machine circuit, wherein the analysis result is used for indicating the JTAG state machine circuit to perform state jump according to the target jump path. By adopting the method, various different state jump requirements can be supported, and the state jump response is fast.

The invention discloses an integrated circuit equipment debugging method and device, equipment and a storage medium, and relates to the technical field of integrated circuit debugging, and the method comprises the steps: monitoring a target joint test action group bus to obtain a target integrated circuit equipment debugging request; analyzing the target integrated circuit equipment debugging request to obtain a target equipment identifier, and performing preset validity verification operation on the target equipment identifier to obtain a verified equipment identifier; matching a target integrated circuit device address corresponding to the target integrated circuit device through a target mapping relation table based on the verified device identifier, and determining a target debugging link according to the target integrated circuit device address; the target debugging link is a link for linking the joint test action group debugging host and the target integrated circuit equipment; and obtaining a target debugging instruction of the target integrated circuit equipment through the target debugging link, and debugging the target integrated circuit equipment based on the target debugging instruction. Therefore, efficient and reliable automatic switching of the JTAG debugging link can be realized.

Provided is a package circuit including a plurality of homogeneous dies including a plurality of input / output terminals, and a joint test action group (JTAG) interface configured to transfer test signals applied to at least one of the plurality of homogeneous dies, wherein a test mode of the plurality of homogeneous dies operates in at least one of a first mode configured to test in series at least two dies among the plurality of homogeneous dies, a second mode configured to test in parallel at least two or more dies among the plurality of homogeneous dies, and a third mode configured to test individually any one die among the plurality of homogeneous dies, and wherein the JTAG interface includes four or five signal terminals.

The present disclosure provides an exception positioning system, method, electronic device and storage medium, and relates to the field of server exception detection.The system comprises a baseboard management controller having a first high-speed serial interface, a plurality of graphic processors, and a controller device.The graphic processors each have a joint test action group interface and a serial interface.The controller device comprises a high-speed serial switching module, a first conversion module, a second conversion module, a serial interface module and a joint test action group interface module.The baseboard management controller acquires register information and state information of the serial interface in parallel through the first high-speed serial signal line to perform exception positioning.The present disclosure can acquire joint test action group and state information of the plurality of graphic processors in parallel, and greatly improves the efficiency of exception positioning.

The invention discloses a batch online upgrading system and method for an FPGA, relates to the technical field of online upgrading, and mainly aims at solving the problems that an existing FPGA upgrading mode is tedious in operation, low in efficiency and high in cost. The system comprises an upper computer, a plurality of microcontrollers and distributed FPGA equipment; when online upgrading is processed, the upper computer carries out subpackage processing on the FPGA program to be upgraded to obtain a plurality of data packets; the upper computer sends the plurality of data packets to each microcontroller through a UART bus, so that each microcontroller stores each data packet; and each microcontroller carries out verification processing on each received data packet and feeds back a verification result to the upper computer. When the verification result received by the upper computer is that the verification is successful, indicating each microcontroller to perform JTAG (Joint Test Action Group) simulation; and each microcontroller uses a GPIO (General Purpose Input / Output) pin to simulate a JATG protocol to upgrade the distributed FPGA equipment.

The utility model discloses a small-size visual development board based on a Quartus platform, which comprises an FPGA (Field Programmable Gate Array) main chip U6, a key control circuit, a memory circuit, a storage circuit, a clock circuit, a JTAG (Joint Test Action Group) interface circuit, a USB (Universal Serial Bus) to serial port circuit, an image acquisition circuit, an image output circuit, an expansion IO (Input / Output) circuit, an Ethernet interface circuit and a power supply circuit, the power supply circuit comprises a DC power supply circuit, a power supply switching circuit, a 12V-5V conversion circuit, a 5V-3.3 V conversion circuit, a 5V-2.5 V conversion circuit and a 5V-1.2 V conversion circuit, the input end of the 12V-5V conversion circuit is electrically connected with the output end of the DC power supply circuit and the output end of the power supply switching circuit, and the power supply switching circuit is electrically connected with the DC power supply circuit and the USB to serial port circuit. An image acquired by the image acquisition circuit is calculated through the FPGA main chip U6, and the image is output through the image output circuit, so that development of a visual system is realized, the size of a visual development board is reduced, the structure is simplified, the cost is reduced, and power consumption is reduced.

The invention relates to a system for burning a FLASH of a DSP (Digital Signal Processor) board card and a burning method thereof. The system comprises a debugging machine, a simulator and a DSP board card. And the debugging machine is used for adopting a DebugServer debugging component as a background debugging service, and is in communication connection with the upper computer software and the emulator respectively so as to drive the emulator to debug the DSP chip. And the emulator is used for adopting a data path of a JTAG (Joint Test Action Group) interface to be in communication connection with the DSP board card so as to transmit a burning control instruction of the upper computer software to the DSP chip. And a DSP chip, a plurality of Flash memories and a read-only memory are embedded in the DSP board card, and the DSP board card is used for executing a burning control instruction and finishing burning of the Flash memories by adopting a shared memory. By adopting the method, the burning efficiency can be improved and the operation process can be simplified.

In an implementation, a method may include receiving an input clock at an input pin of a device, the device having a Joint Test Action Group (JTAG) test access port (TAP). The method may also include counting a first number of cycles of a reference clock using a first counter. The method may furthermore include simultaneously counting a second number of cycles of the input clock received at the input pin using a second counter. The method may in addition include calculating a frequency of the input clock based on the counted first number of cycles of the reference clock, the counted second number of cycles of the input clock, and a frequency of the reference clock.

The invention discloses a JTAG (Joint Test Action Group) dynamic key burning method, which comprises the following steps of: 1) acquiring physical characteristics of a main control chip, and acquiring a unique PUF (Physical Unclonable Function) correction value of equipment; 2) encrypting the obtained PUF correction value, and obtaining an encrypted key stream bound with equipment firmware; 3) calculating a hash value of the encrypted key stream, writing the hash value into an SPI-NOR fusing region, generating a laser fusing path coordinate, and outputting a fusing instruction; 4) positioning a JTAG communication path according to the coordinates of the fusing path; and executing laser fusing operation, after fusing is completed, detecting a path state, generating a corresponding fusing state code, and recording whether fusing succeeds or not. According to the method, the SM4 and the secondary encryption algorithm are combined, a complete security chain from key generation and hardware characteristic binding to physical fusing is constructed, and the security standard of the storage device is met.

The invention relates to the technical field of servers, and discloses a JTAG (Joint Test Action Group) link topology control device and method and a server, the device comprises a first switching module and a second switching module, during single-path control, the first switching module is used for establishing a JTAG link between a first master device and a first slave device, and the second switching module is used for establishing a JTAG link between a second master device and a second slave device; the second switching module is used for establishing a JTAG link between the second master device and the second slave device; during two-way control, the first switching module is used for establishing a JTAG link between the first master device and the first slave device, and the second switching module is used for establishing a JTAG link between the first master device and the second slave device; or, during two-way control, the first switching module is used for establishing a JTAG link between the second master device and the first slave device, and the second switching module is used for establishing a JTAG link between the second master device and the second slave device, so that the debugging and control requirements in different scenes are met, and the flexibility of the system topology is improved.

The invention relates to the field of circuit board testing, in particular to an automatic switching device and switching method for a multi-processor JTAG debugging mode. A micro control unit MCU; the multi-path electronic switch comprises a plurality of control input ends and a plurality of signal channels, and the plurality of control input ends are electrically connected with GPIO (General Purpose Input / Output) pins of the MCU and are used for receiving level control signals; each processor is provided with a JTAG (Joint Test Action Group) signal pin; jTAG signal pins of the plurality of processors are connected with a plurality of signal channels of the multipath electronic switch; the multipath electronic switch switches the connection state of an internal signal channel by responding to a level control signal, and dynamically reconfigures JTAG signal pins of the plurality of processors into a cascade mode and an independent mode; through cooperative control of the micro-control unit and the multi-path electronic switch, dynamic switching of the multi-processor JTAG between a cascade mode and an independent mode is realized, the debugging efficiency and the system reliability are improved, and the area of a circuit board and interface resources are remarkably saved.

The invention discloses a JTAG (Joint Test Action Group) authentication method and device based on a vehicle-mounted Ethernet chip, and a storage medium. The JTAG authentication method comprises the following steps: S1, configuring a chip id, an authkey0, an authkey1 and an authkey2 for each Ethernet chip; s2, according to a JTAG interface access request, the input password1 and the input password2 are compared with expected results calculated by a hardware algorithm respectively, so that whether the enabling of a JTAG access module is started or not is determined; if any secret key is not successfully verified, the access permission is not opened, retry waiting is carried out, and if the number of times of retry waiting reaches the upper limit, the hardware logic stops the authentication process, and the access channel is closed. According to the scheme, different user names and passwords can be provided for chip products of the same batch for access, the user names and the passwords must appear in pairs, otherwise, authentication is not passed, the number of access times is limited, and once the number of input mismatching times of the user names and the passwords reaches the upper limit, the authentication module immediately stops authentication and locks permission access of the JTAG, so that the authentication efficiency is improved. And the safety of the vehicle-mounted Ethernet chip is improved.

Embodiments of the present application provide an interface calling method, a chip and a computing device. A specific implementation of the method includes: receiving an access request of a first application based on a general interface, the access request being used to access a Joint Test Action Group (JTAG) register; calling an intermediate interface based on the access request, the intermediate interface being used to call a first operation instruction registered in a JTAG structure; and performing an access operation on the JTAG register through a JTAG controller based on the first operation instruction to respond to the access request. Thus, when the JTAG controller or the JTAG register changes, only the first operation instruction needs to be reconstructed to maintain the original general interface and the intermediate interface to respond to the access request, thereby improving the development efficiency of the system and reducing the maintenance cost of the system.

The application discloses a test method, a detection circuit and a system for a storage chip of a probe card, relates to the technical field of semiconductor testing, and discloses a detection circuit, which comprises a control module and an Ethernet module. The control module comprises a joint test action group interface, the joint test action group interface is connected with the Ethernet module, a test control end of the control module is used for electrical connection with a storage chip, the Ethernet module communicates with a host computer, is used for receiving a first test programming program in an Ethernet protocol format sent by the host computer, and converts the first test programming program into a second test programming program in a joint test protocol format; the control module is used for receiving the second test programming program through the joint test action group interface, and performing read-write function testing on the storage chip based on the second test programming program, so that functional detection of the storage chip on the probe card can be realized, and performance decline of the probe card caused by storage chip failure can be avoided.

The invention discloses terminal equipment, a debugging system and a vehicle. Physical safety and information safety of the terminal equipment are improved. The terminal equipment comprises a processor 11, an isolator 12 and a Type-C interface 13, wherein the processor 11 is integrated with a JTAG (Joint Test Action Group) interface; a plurality of pins of the JTAG interface are connected to corresponding pins of the Type-C interface 13 according to a pin mapping logic defined by a user; the isolator 12 is connected between the JTAG interface and the Type-C interface 13, and is used for disconnecting the electrical connection between the JTAG interface and the Type-C interface 13 when the pin connection between the JTAG interface and the Type-C interface 13 is short-circuited; a level conversion circuit is integrated on the isolator 12; and among the pins of the JTAG interface and the Type-C interface 13, the pins with pin mapping logic but unmatched electrical characteristics are connected through a level conversion circuit.

Embodiments of the present application provide a method and device for automatically testing a chip, the method comprising: automatically generating a test routine for different pins, and compiling the test routine into an executable ELF file, wherein the executable ELF file comprises all codes and data to be tested; placing the executable ELF file in a specified location; receiving an input chip model and pin information to obtain test parameters, wherein the test parameters are used to establish a Joint Test Action Group (JTAG) connection; and automatically connecting to the chip through a JTAG interface and performing a test according to the test parameters. The technical solution of the embodiments of the present application significantly reduces the technical threshold, reduces the risk of human operation errors, improves the test efficiency, greatly reduces the labor cost, and brings significant acceleration effect to the chip production and screening process.

The invention discloses a method for realizing SDRAM (synchronous dynamic random access memory) function performance online detection based on a JTAG (joint test action group) tool. The method comprises the following steps: designing an SDRAM function performance test program; wherein the size of a target file of the function performance test program does not exceed the size of a cache with an SRAM mode in the CPU; setting initial address information of a code segment, a static data segment, a data segment and a stack segment in the function performance test program; a CPU emulator is used for controlling a PC pointer value logic address through a JTAG interface so as to complete the skipping function of the PC pointer, and a cache with an SRAM mode in a CPU is switched to the SRAM mode; and loading the function performance test program to a cache with an SRAM mode in the CPU to realize the execution of the test program. According to the method, the problems that the boundary scanning test is low in test efficiency and the internal BIT test is insufficient in test coverage rate are solved, so that the quality and reliability of delivered products are improved.

The invention discloses a test method, a detection circuit and a system for a memory chip of a probe card, and relates to the technical field of semiconductor testing, the detection circuit comprises a control module and an Ethernet module, the control module comprises a joint test action group interface, the joint test action group interface is connected with the Ethernet module, and the Ethernet module is connected with the control module. The test control end of the control module is used for being electrically connected with a storage chip. The Ethernet module communicates with an upper computer and is used for receiving a first test burning program in an Ethernet protocol format sent by the upper computer and converting the first test burning program into a second test burning program conforming to a joint test protocol format. And the control module is used for receiving the second test burning program through the joint test action group interface and carrying out read-write function test on the storage chip based on the second test burning program, so that functional detection on the storage chip on the probe card can be realized, and performance reduction of the probe card caused by faults of the storage chip is avoided.

In an implementation, a method may include receiving an input clock at an input pin of a device, the device having a Joint Test Action Group (JTAG) test access port (TAP). The method may also include counting a first number of cycles of a reference clock using a first counter. The method may furthermore include simultaneously counting a second number of cycles of the input clock received at the input pin using a second counter. The method may in addition include calculating a frequency of the input clock based on the counted first number of cycles of the reference clock, the counted second number of cycles of the input clock, and a frequency of the reference clock.