10 results about "Boundary scan testing" patented technology

The application discloses a sorting control method and device for chip testing, and relates to the technical field of article sorting, and comprises the following steps: setting a carrier for chip testing; placing a plurality of to-be-tested chips on a plurality of test sites on the carrier, the pins of each to-be-tested chip comprising a scan register and a test access port; connecting a chip testing system, reading a test script corresponding to the plurality of to-be-tested chips; controlling a boundary scan tester to perform boundary scan testing according to the test script, and outputting chip response data; analyzing the chip response data, identifying abnormal chips and test sites of the abnormal chips, and controlling a sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips. The application solves the technical problems that the existing technology has slow sorting speed, unreasonable sorting line planning, and insufficient combination degree of chip testing and sorting control, and achieves the technical effects of improving the sorting speed, reasonably planning the sorting line, and improving the combination degree of chip testing and sorting control.

The invention discloses a parallel boundary scan test system based on an SVF format test input file, and the system employs a single-chip microcomputer or a microcontroller to serve as a boundary scan test actuator, and reads a test instruction and a test excitation vector described by the SVF format test input file. Test excitation and test control signals such as TDI / TMS / TCK / TRST are respectively generated on four IO pins of the boundary scan test actuator; after being driven and amplified by a bus driver, the signals are broadcasted and issued to TAP interfaces of all tested circuit boards and a reference circuit board through a star bus, all comparators judge test results according to the consistency of TDO output signals of the reference circuit board and TDO output signals of all the tested circuit boards, and finally LED lamps are used for displaying the test results of all the parallel test branches. The boundary scanning test system has the parallel test capability which is not possessed by a traditional boundary scanning test system, and is extremely high in cost-efficiency ratio.

The invention discloses a boundary scan test structure which is used for circuit board card interface interconnection test, and a test platform main control unit and a tested mainboard carry out data interaction only through a test main control and data backhaul JTAG (Joint Test Action Group) channel. According to the invention, a plurality of return JTAG wires in a traditional boundary scan test structure are canceled, and connectors, wire harnesses and EMI fault points can be reduced, so that the breakage rate of a production line is remarkably reduced, and the test reliability can be improved. According to the invention, only one JTAG line is needed on hardware, and the Dummy Card does not need an additional JTAG interface, so that the wiring complexity and the material cost are reduced. When the slot signals are independent, a plurality of slots can be tested in parallel, the test time of the whole board is shortened, and the test efficiency can be improved. The method can be implemented for any CPU with boundary scanning capability and FPGA logic conforming to IEEE 1581, is suitable for production lines of various high-reliability board cards such as server mainboards and backboards, and is high in universality.

The application discloses a boundary scan test matrix generation method based on heuristic search, which comprises the following steps: firstly, counting the number of networks in the measured circuit board and calculating the normalized distance between any two networks; then, calculating the short-circuit probability between the networks through the normalized distance between any two networks, so as to construct a short-circuit probability matrix between the networks; then, setting a test matrix and generating a plurality of row test matrices according to the test matrix; finally, searching for the test matrix with the minimum cost through the establishment of a search tree based on the test cost and the heuristic function value.

The invention relates to the technical field of electronic testing, in particular to an automatic testing method for a retiming card, which comprises the following steps of: constructing a BSI boundary scan testing system, performing coordination control through upper computer software, and forming at least one boundary scan chain by adopting the BSI boundary scan testing system; automatically executing a test sequence through the upper computer software, wherein the test sequence comprises a power supply input test, an IIC communication test, a differential signal error code test, an IO network interconnection test, a power supply on-off test and a GND connectivity test; automatically judging PASS or FAIL based on a test result, and generating a test report; wherein the test report comprises pin-level fault positioning information and test coverage rate statistics. By constructing a multi-link boundary scanning system, digital signal testing, power management and communication protocol verification are integrated, the testing precision and speed are remarkably improved, and comprehensive automatic testing of the Retimer Card is achieved.

This invention discloses a BSDL-free model I / O open / short circuit testing system and method. The BSDL-free model I / O open / short circuit testing system, used for boundary scanning, includes: a boundary scanning test card, a constant current source circuit, an ADC acquisition circuit, a switching circuit, an FPGA, and a test host computer. The constant current source circuit, ADC acquisition circuit, and switching circuit are integrated within the boundary scanning device. The output terminal of the constant current source circuit is connected to the BSDL-free model I / O pin of the chip under test (DUT) to output a constant current. The input terminal of the ADC acquisition circuit is connected to the DUT pin to acquire the pin voltage. The switching circuit connects the constant current source circuit and the ADC acquisition circuit to switch the protection diode test type. The ADC acquisition circuit is connected to the FPGA via an I2C interface, and the FPGA communicates with the test host computer. This invention enables open / short circuit testing of BSDL-free model I / O pins within a boundary scanning device, improving test coverage, reducing test costs, and increasing test efficiency.

The invention discloses a method for realizing SDRAM (synchronous dynamic random access memory) function performance online detection based on a JTAG (joint test action group) tool. The method comprises the following steps: designing an SDRAM function performance test program; wherein the size of a target file of the function performance test program does not exceed the size of a cache with an SRAM mode in the CPU; setting initial address information of a code segment, a static data segment, a data segment and a stack segment in the function performance test program; a CPU emulator is used for controlling a PC pointer value logic address through a JTAG interface so as to complete the skipping function of the PC pointer, and a cache with an SRAM mode in a CPU is switched to the SRAM mode; and loading the function performance test program to a cache with an SRAM mode in the CPU to realize the execution of the test program. According to the method, the problems that the boundary scanning test is low in test efficiency and the internal BIT test is insufficient in test coverage rate are solved, so that the quality and reliability of delivered products are improved.

The invention discloses a boundary scan test structure and method, the boundary scan test structure is used for circuit board card interface interconnection test, and a test platform main control unit and a tested mainboard carry out data interaction only through a JTAG channel; selecting three signal lines from the signal lines of each tested slot as test control and data return channels; and the test control and data return channel is used for customizing a protocol to transmit a test command and a test result. According to the invention, a parallel test scheme that a plurality of back JTAG cables are needed in the prior art is abandoned, and a technical scheme that a command-back bus formed by combining one master control JTAG channel with three signal lines in each slot in a time division multiplexing manner is redesigned, so that hardware connecting lines are replaced by software time sequences, and the number of hardware connecting lines is greatly reduced; and the reliability and the anti-interference performance of the connection in the production test are obviously improved.

A system and method for boundary scan testing of the test points of the pin under test is disclosed. When it is determined that the pin under test of the target connector cannot be subjected to boundary scan testing, the system finds the test point that is connected to and closest to the pin under test, sends a test signal to the target connector, receives the result signal generated by the test signal through the target connector, and compares the test signal and the result signal to generate a test result. This technology can use the boundary scan function to test the connectors of computer products and achieves the technical effect of improving the test range and test coverage of traditional boundary scan testing, thereby improving test efficiency and reducing test costs.