21 results about "Boundary scan testing" patented technology

The invention discloses a method and a system for boundary scan testing and effective positioning of a short circuit fault. The method comprises the following steps: acquiring first data corresponding to a short circuit fault to be subjected to boundary scan testing and positioning in real time; wherein the first data is a connection relationship of a to-be-tested connection network; based on the first data, respectively generating second data and third data corresponding to a to-be-tested connection network; according to the second data and the third data and in combination with the first data, performing binary processing on level data sent in the to-be-tested connection network; according to the transmission state of the level data in the to-be-tested connection network, fourth data corresponding to the to-be-tested connection network is generated; wherein the fourth data is short-circuit fault data of the to-be-tested connection network; according to the method, the system and the platform corresponding to the method, the short-circuit faults can be clearly checked among the connected networks, and the short-circuit fault checking efficiency is improved.

The invention relates to the field of boundary scanning test of laminated chips, in particular to a laminated chip boundary scanning test structure combining IEEE 1838 and IEEE 1149.4 standards, and mainly relates to fault and defect detection of TSV (Through Silicon Via) of a laminated chip connecting part. Chip package registers (DWR) are embedded into the two ends of a through silicon via (TSV) connected with the laminated chip in the laminated chip, a simulation test bus and a corresponding interface circuit are added into the chip to form a scanning chain, and the mixed signal boundary scanning test structure of the laminated chip is formed. When the chip works normally, the test structure does not influence the logic function of the chip; in the testing process, the testing upper computer sends different control instructions, and full-coverage online fault and defect detection of the connectivity of the laminated chips is achieved.

The invention relates to a test system and a test method, and relates to the technical field of test, and the method comprises the steps: obtaining test working condition information; generating a test case from the test condition information through a preset tool; calling an API (Application Program Interface), which is used for realizing a boundary scan test, of the Lauterbach simulator on the basis of the test case, and reading input and output signals between a chip pin related to the tested equipment and a processor core corresponding to the upper computer module; monitoring a chip software memory related to the tested equipment from the input and output signals; and performing test analysis on the monitored chip software memory to obtain a test result. According to the application, the test system capable of realizing boundary scan test is established based on the API interface of the third-party equipment Lauterbach simulator open source, and the monitoring on the chip software memory can be realized, so that in the test process of the corresponding type of the integrated equipment, whether the relevant software operation accords with the designed operation strategy or not can be accurately determined, and the test accuracy can be improved.

The application discloses a sorting control method and device for chip testing, and relates to the technical field of article sorting, and comprises the following steps: setting a carrier for chip testing; placing a plurality of to-be-tested chips on a plurality of test sites on the carrier, the pins of each to-be-tested chip comprising a scan register and a test access port; connecting a chip testing system, reading a test script corresponding to the plurality of to-be-tested chips; controlling a boundary scan tester to perform boundary scan testing according to the test script, and outputting chip response data; analyzing the chip response data, identifying abnormal chips and test sites of the abnormal chips, and controlling a sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips. The application solves the technical problems that the existing technology has slow sorting speed, unreasonable sorting line planning, and insufficient combination degree of chip testing and sorting control, and achieves the technical effects of improving the sorting speed, reasonably planning the sorting line, and improving the combination degree of chip testing and sorting control.

The present invention discloses a method and system for realizing directional configuration of FPGA core of Zynq device. In the process of testing Zynq device, JTAG daisy chain is cascaded on Zynq device; FPGA core connected to Zynq device is developed, data format of configuration information of FPGA core is obtained based on JTAG daisy chain, operation of daisy chain topology is realized through JTAG daisy chain, thereby realizing directional configuration of FPGA core of Zynq device, and JTAG daisy chain technology can be used to send instructions and receive responses from Zynq device and its connected equipment, thereby performing hardware verification, boundary scan test, troubleshooting, etc. This test method not only improves test efficiency, but also reduces test cost. Through JTAG daisy chain, developers can realize directional configuration of FPGA core in Zynq device. FPGA core can be accurately configured as specific logic function, while maintaining close cooperation with Zynq processor core.

The invention discloses a universal hardware architecture suitable for a boundary scan test and a use method thereof. The framework comprises at least three switching type connectors which are used for the boundary scan test and are located between a to-be-tested plate and a simulation test card, and the switching type connectors comprise a first switching type connector, a second switching type connector and a third switching type connector; the first switching type connector is formed by connecting at least one switching wire and at least one switching card through a golden finger; the second switching type connector is formed by connecting at least two switching wires and at least one switching card through golden fingers; the second switching type connector is formed by connecting at least one switching line and at least two switching cards through golden fingers. According to the method, hardware does not need to be repeatedly designed, the hardware development difficulty of the boundary scan test system is remarkably reduced, the jig delivery time is shortened, design errors are effectively avoided, and compared with a customized board card, the cost is effectively reduced.

The invention discloses a parallel boundary scan test system based on an SVF format test input file, and the system employs a single-chip microcomputer or a microcontroller to serve as a boundary scan test actuator, and reads a test instruction and a test excitation vector described by the SVF format test input file. Test excitation and test control signals such as TDI / TMS / TCK / TRST are respectively generated on four IO pins of the boundary scan test actuator; after being driven and amplified by a bus driver, the signals are broadcasted and issued to TAP interfaces of all tested circuit boards and a reference circuit board through a star bus, all comparators judge test results according to the consistency of TDO output signals of the reference circuit board and TDO output signals of all the tested circuit boards, and finally LED lamps are used for displaying the test results of all the parallel test branches. The boundary scanning test system has the parallel test capability which is not possessed by a traditional boundary scanning test system, and is extremely high in cost-efficiency ratio.

The present disclosure relates to a method and a system for boundary scan testing of joint test action group (JTAG)-compliant devices in massive multiple input and multiple output Radio Unit (MRU) The method comprises: (a) receiving, by receiving unit [302], a set of boundary scan description language (BSDL) files corresponding to JTAG-compliant devices; (b) determining, by determining unit [304], set of non-logical pins for each of the JTAG-compliant devices; (c) establishing, by processing unit [306], a daisy chain configuration; (d) categorizing, by processing unit [306], each of the JTAG-compliant devices into one of a passive device, a test device, and a logic device; (e) generating, by a generating unit [308], at least one test code based on the categorization and information associated with BSDL files; and (f) generating, by generating unit [308], a set of results after completion of execution of generated test code.

The utility model aims to provide a plurality of test cards which are simple in structure and convenient to operate and maintain, support a Boundy-Scan test mode, can improve the test coverage rate of a server mainboard, support step-by-step self-check conduction, and realize data storage and fault connection position detection and positioning under the conditions of high temperature, high frequency and high speed. The device comprises a JTAG signal input interface, a power supply control module, a differential signal acquisition unit, a signal acquisition module and a golden finger, the differential signal acquisition unit is connected with the power supply control module and the signal acquisition module, the power supply control module and the signal acquisition module are both connected with the JTAG signal input interface, and the golden finger is connected with the JTAG signal input interface. And the golden finger is connected with the signal acquisition module. The utility model is applied to the technical field of printed circuit board testing.

The invention discloses a riser card service life prolonging processing system and method suitable for a boundary scan test. The riser card service life prolonging processing system suitable for the boundary scan test comprises at least one boundary scan controller and an upper computer communicating with the boundary scan controller. One side of the boundary scanning controller is electrically connected with at least one boundary scanning simulation detection card; the other side of the boundary scanning controller is electrically connected with an adapter card service life processing control panel; the boundary scanning simulation detection card is in plug-in connection with at least one adapter card through a golden finger; the adapter card is in automatic butt joint with a board to be tested through a golden finger, and the butt joint action is automatically controlled through the adapter card service life processing control board. The riser card is internally provided with a first control chip used for realizing riser card service life management, and the service life of the riser card can be effectively prolonged by the adoption of the riser card service life prolonging processing method.

The invention discloses a boundary scan test structure which is used for circuit board card interface interconnection test, and a test platform main control unit and a tested mainboard carry out data interaction only through a test main control and data backhaul JTAG (Joint Test Action Group) channel. According to the invention, a plurality of return JTAG wires in a traditional boundary scan test structure are canceled, and connectors, wire harnesses and EMI fault points can be reduced, so that the breakage rate of a production line is remarkably reduced, and the test reliability can be improved. According to the invention, only one JTAG line is needed on hardware, and the Dummy Card does not need an additional JTAG interface, so that the wiring complexity and the material cost are reduced. When the slot signals are independent, a plurality of slots can be tested in parallel, the test time of the whole board is shortened, and the test efficiency can be improved. The method can be implemented for any CPU with boundary scanning capability and FPGA logic conforming to IEEE 1581, is suitable for production lines of various high-reliability board cards such as server mainboards and backboards, and is high in universality.

The application discloses a boundary scan test matrix generation method based on heuristic search, which comprises the following steps: firstly, counting the number of networks in the measured circuit board and calculating the normalized distance between any two networks; then, calculating the short-circuit probability between the networks through the normalized distance between any two networks, so as to construct a short-circuit probability matrix between the networks; then, setting a test matrix and generating a plurality of row test matrices according to the test matrix; finally, searching for the test matrix with the minimum cost through the establishment of a search tree based on the test cost and the heuristic function value.

The invention discloses a method, a system and a CPU (central processing unit) simulation structure for a mainboard boundary scan test. According to the method, a to-be-tested mainboard is placed on a jig carrier plate, a jig acts, and a first connector in the to-be-tested mainboard is connected with a second connector in a first simulation test card and a third connector in a second simulation test card in an inserted mode; according to the method, the cascade chain of the first simulation test card and the second simulation test card is subjected to the boundary scan test through the arranged boundary scan controller, and the system and the CPU simulation structure corresponding to the method can solve the defects of the conventional CPU test, achieve the boundary scan test coverage effect better than that of the conventional CPU, and have the advantages of high test reliability, high test speed and low cost. The power-on, the power-on time sequence and the power-on time of the CPU do not need to be considered, signal receiving, transmitting and reading are all completed through the DUMMY, the test effect is completely mastered at the design end of the boundary scan test, the compatibility is high, and the safety is high.

The invention relates to the technical field of electronic testing, in particular to an automatic testing method for a retiming card, which comprises the following steps of: constructing a BSI boundary scan testing system, performing coordination control through upper computer software, and forming at least one boundary scan chain by adopting the BSI boundary scan testing system; automatically executing a test sequence through the upper computer software, wherein the test sequence comprises a power supply input test, an IIC communication test, a differential signal error code test, an IO network interconnection test, a power supply on-off test and a GND connectivity test; automatically judging PASS or FAIL based on a test result, and generating a test report; wherein the test report comprises pin-level fault positioning information and test coverage rate statistics. By constructing a multi-link boundary scanning system, digital signal testing, power management and communication protocol verification are integrated, the testing precision and speed are remarkably improved, and comprehensive automatic testing of the Retimer Card is achieved.

The invention discloses a sorting control method and device for chip testing, and relates to the technical field of article sorting, and the sorting control method comprises the following steps: setting a carrier for chip testing; placing a plurality of to-be-tested chips on a plurality of test positions on a carrier, wherein pins of each to-be-tested chip comprise a scanning register and a test access port; connecting a chip test system, and reading test scripts corresponding to the plurality of chips to be tested; controlling the boundary scanning tester to perform boundary scanning testing according to the testing script, and outputting chip response data; and analyzing the chip response data, identifying an abnormal chip and a test position of the abnormal chip, and controlling a sorting mechanism to carry out abnormal sorting according to the test position of the abnormal chip. The technical problems that in the prior art, the sorting speed is low, sorting line planning is unreasonable, and the combination degree of chip testing and sorting control is not tight enough are solved, and the technical effects that the sorting speed is increased, sorting lines are reasonably planned, and the combination degree of chip testing and sorting control is increased are achieved.

The invention discloses an interconnection testing method based on a chip particle microsystem, and belongs to the technical field of chip testing. Wherein the chip particle microsystem structure is analyzed, the number of chip particle microsystem interconnection networks is determined, the interconnection networks are classified, and the method mainly comprises the steps of boundary scanning chip interconnection networks and hybrid interconnection networks, automatically generating test vectors based on the boundary scanning technology, loading and running the test vectors through ATE, and classifying the interconnection networks. And designing a real installation test system to test the hybrid internet, if the hybrid internet is judged to have a fault, triggering a boundary scan test program, and diagnosing the fault type through a boundary scan test method. By combining the boundary scanning test with the real installation test technology, on the premise that the hardware cost is not increased, the real installation test and the boundary scanning test are fused in a cross-platform mode, the high coverage rate test of the core particle microsystem interconnection network is achieved, and the application quality of the core particle microsystem is guaranteed.

This invention discloses a BSDL-free model I / O open / short circuit testing system and method. The BSDL-free model I / O open / short circuit testing system, used for boundary scanning, includes: a boundary scanning test card, a constant current source circuit, an ADC acquisition circuit, a switching circuit, an FPGA, and a test host computer. The constant current source circuit, ADC acquisition circuit, and switching circuit are integrated within the boundary scanning device. The output terminal of the constant current source circuit is connected to the BSDL-free model I / O pin of the chip under test (DUT) to output a constant current. The input terminal of the ADC acquisition circuit is connected to the DUT pin to acquire the pin voltage. The switching circuit connects the constant current source circuit and the ADC acquisition circuit to switch the protection diode test type. The ADC acquisition circuit is connected to the FPGA via an I2C interface, and the FPGA communicates with the test host computer. This invention enables open / short circuit testing of BSDL-free model I / O pins within a boundary scanning device, improving test coverage, reducing test costs, and increasing test efficiency.

The invention discloses a method for realizing SDRAM (synchronous dynamic random access memory) function performance online detection based on a JTAG (joint test action group) tool. The method comprises the following steps: designing an SDRAM function performance test program; wherein the size of a target file of the function performance test program does not exceed the size of a cache with an SRAM mode in the CPU; setting initial address information of a code segment, a static data segment, a data segment and a stack segment in the function performance test program; a CPU emulator is used for controlling a PC pointer value logic address through a JTAG interface so as to complete the skipping function of the PC pointer, and a cache with an SRAM mode in a CPU is switched to the SRAM mode; and loading the function performance test program to a cache with an SRAM mode in the CPU to realize the execution of the test program. According to the method, the problems that the boundary scanning test is low in test efficiency and the internal BIT test is insufficient in test coverage rate are solved, so that the quality and reliability of delivered products are improved.

The invention discloses a boundary scan test structure and method, the boundary scan test structure is used for circuit board card interface interconnection test, and a test platform main control unit and a tested mainboard carry out data interaction only through a JTAG channel; selecting three signal lines from the signal lines of each tested slot as test control and data return channels; and the test control and data return channel is used for customizing a protocol to transmit a test command and a test result. According to the invention, a parallel test scheme that a plurality of back JTAG cables are needed in the prior art is abandoned, and a technical scheme that a command-back bus formed by combining one master control JTAG channel with three signal lines in each slot in a time division multiplexing manner is redesigned, so that hardware connecting lines are replaced by software time sequences, and the number of hardware connecting lines is greatly reduced; and the reliability and the anti-interference performance of the connection in the production test are obviously improved.

A system and method for boundary scan testing of the test points of the pin under test is disclosed. When it is determined that the pin under test of the target connector cannot be subjected to boundary scan testing, the system finds the test point that is connected to and closest to the pin under test, sends a test signal to the target connector, receives the result signal generated by the test signal through the target connector, and compares the test signal and the result signal to generate a test result. This technology can use the boundary scan function to test the connectors of computer products and achieves the technical effect of improving the test range and test coverage of traditional boundary scan testing, thereby improving test efficiency and reducing test costs.