6 results about "Boundary scan testing" patented technology

The application discloses a boundary scan test matrix generation method based on heuristic search, which comprises the following steps: firstly, counting the number of networks in the measured circuit board and calculating the normalized distance between any two networks; then, calculating the short-circuit probability between the networks through the normalized distance between any two networks, so as to construct a short-circuit probability matrix between the networks; then, setting a test matrix and generating a plurality of row test matrices according to the test matrix; finally, searching for the test matrix with the minimum cost through the establishment of a search tree based on the test cost and the heuristic function value.

The invention relates to the technical field of electronic testing, in particular to an automatic testing method for a retiming card, which comprises the following steps of: constructing a BSI boundary scan testing system, performing coordination control through upper computer software, and forming at least one boundary scan chain by adopting the BSI boundary scan testing system; automatically executing a test sequence through the upper computer software, wherein the test sequence comprises a power supply input test, an IIC communication test, a differential signal error code test, an IO network interconnection test, a power supply on-off test and a GND connectivity test; automatically judging PASS or FAIL based on a test result, and generating a test report; wherein the test report comprises pin-level fault positioning information and test coverage rate statistics. By constructing a multi-link boundary scanning system, digital signal testing, power management and communication protocol verification are integrated, the testing precision and speed are remarkably improved, and comprehensive automatic testing of the Retimer Card is achieved.

This invention discloses a BSDL-free model I / O open / short circuit testing system and method. The BSDL-free model I / O open / short circuit testing system, used for boundary scanning, includes: a boundary scanning test card, a constant current source circuit, an ADC acquisition circuit, a switching circuit, an FPGA, and a test host computer. The constant current source circuit, ADC acquisition circuit, and switching circuit are integrated within the boundary scanning device. The output terminal of the constant current source circuit is connected to the BSDL-free model I / O pin of the chip under test (DUT) to output a constant current. The input terminal of the ADC acquisition circuit is connected to the DUT pin to acquire the pin voltage. The switching circuit connects the constant current source circuit and the ADC acquisition circuit to switch the protection diode test type. The ADC acquisition circuit is connected to the FPGA via an I2C interface, and the FPGA communicates with the test host computer. This invention enables open / short circuit testing of BSDL-free model I / O pins within a boundary scanning device, improving test coverage, reducing test costs, and increasing test efficiency.

The invention discloses a method for realizing SDRAM (synchronous dynamic random access memory) function performance online detection based on a JTAG (joint test action group) tool. The method comprises the following steps: designing an SDRAM function performance test program; wherein the size of a target file of the function performance test program does not exceed the size of a cache with an SRAM mode in the CPU; setting initial address information of a code segment, a static data segment, a data segment and a stack segment in the function performance test program; a CPU emulator is used for controlling a PC pointer value logic address through a JTAG interface so as to complete the skipping function of the PC pointer, and a cache with an SRAM mode in a CPU is switched to the SRAM mode; and loading the function performance test program to a cache with an SRAM mode in the CPU to realize the execution of the test program. According to the method, the problems that the boundary scanning test is low in test efficiency and the internal BIT test is insufficient in test coverage rate are solved, so that the quality and reliability of delivered products are improved.

A system and method for boundary scan testing of the test points of the pin under test is disclosed. When it is determined that the pin under test of the target connector cannot be subjected to boundary scan testing, the system finds the test point that is connected to and closest to the pin under test, sends a test signal to the target connector, receives the result signal generated by the test signal through the target connector, and compares the test signal and the result signal to generate a test result. This technology can use the boundary scan function to test the connectors of computer products and achieves the technical effect of improving the test range and test coverage of traditional boundary scan testing, thereby improving test efficiency and reducing test costs.