375results about "Transmission line coupling arrangements" patented technology

Millimeter wave (mmWave) technologies, devices, and methods related to transceivers, receivers, and antenna structures for wireless communications are described. Various aspects include collocated millimeter wave (mmWave) antennas and near field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication systems with MIMO support and phase noise synchronization on a single coaxial cable, passing RF signals over cable (RFoC) in distributed phased array communication systems, clock noise leakage reduction, IF to RF auxiliary chips for backward and forward compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architectures, and the like.

Embodiments included herein are directed towards a passive equalization circuit. The circuit may include a transmitter, a receiver; and a passive equalization circuit that may be located between the transmitter and the receiver. A first inductor may be located between the transmitter and a primary node net, and a second inductor may be located between the primary node net and a pad, and a third inductor may be located between the primary node net and the receiver.

Transport networks, network elements, and methods of use are described herein, including a transmitter comprising a client-side input, transmitter circuitry, and antennas. The client-side input is configured to receive baseband signals having client data encoded therein. The transmitter circuitry is configured to receive the baseband signals from the client-side input and generate antenna feed signals based on the baseband signals. The antennas are configured to receive the antenna feed signals from the transmitter circuitry, generate radiated signals based on the antenna feed signals, and couple the radiated signals into a hollow waveguide. Each of the radiated signals is a radiated electromagnetic wave configured for coherent detection and has a frequency in a range between 300 Gigahertz (GHz) and 10 Terahertz (THz).

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

The single-wire communication circuit comprises a microcontroller, the microcontroller comprises a sending pin, the single-wire communication circuit further comprises a first switch unit and a power supply, the first switch unit is electrically connected with the sending pin and the power supply, and the first switch unit is configured to be electrically connected with a negative electrode output terminal of a battery pack; the power supply is configured to supply power to the first switch unit, the power supply is further configured to respond to the microcontroller to send a high level to the first switch unit, and the power supply provides the high level for the first communication wire harness; the first switching unit is configured to electrically connect the first communication harness to the negative output terminal in response to the microcontroller transmitting a low level to the first switching unit.

A high-speed transmitter system is disclosed that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data by one or more serialization stages, a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal using PMOS transistors based on the received input. Also, the logic circuit is connected to a low-voltage power supply, whereby its output can be adjusted to be close to the switching point of a PMOS-based gm stage so as to accelerate the operation of the transmitter.

An equalizer includes a delay circuit configured to generate at least one delay signal based on at least one input signal, an encoding circuit configured to generate a plurality of driving signals and a connection switching signal, based on the input signal and the delay signal, a pre-driver configured to generate a plurality of driving switching signals based on the plurality of driving signals, a first differential circuit configured to generate a first differential output signal based on the plurality of driving switching signals, a second differential circuit configured to generate a second differential output signal based on the plurality of driving switching signals, and a connection circuit configured to adjust a connection between the first differential circuit and the second differential circuit based on the connection switching signal.

An isolated gate driver has: a register that stores the adjustment data read from a non-volatile memory; a gate driving circuit that drives the gate of a switching element with a characteristic set based on a value stored in the register; a fault detector that performs fault detection for other than the non-volatile memory; an error detection-correction circuit that performs error detection and error correction on the adjustment data written to the non-volatile memory; a first external terminal for output of the result of fault detection; a second external terminal for output of the result of error detection; and a fault controller that, if a one-bit error is detected in the adjustment data, brings the second external terminal into an error-indicating output state and continues with normal operation of the gate driving circuit and, if a two-or-more-bit error is detected in the adjustment data, forcibly stops the gate driving circuit.

The disclosure relates to a transceiver physical layer interface. Example embodiments include a transmission line transceiver (401) comprising: first and second terminals (406a, 406b); a control module (416); an amplifier module (414) connected between the control module (416) and the first and second terminals (406a, 406b); a switchable termination resistance circuit (408, 410) connected between the first and second terminals (406a, 406b), the switchable termination resistance circuit (408, 410) comprising a termination resistance (408) connected in series with a switch (410) controllable by the control module (416); a pair of series connected resistors (418a, 418b) connected between the first and second terminals (406a, 406b); a capacitor (420) connected between a node (423) connecting the pair of series connected resistors (418a, 418b) and a common node (422), wherein the control module (416) is configured to open the switch (410) to disconnect the termination resistance (408) during transmission of a signal via a transmission line (403) capacitively connected to the first and second terminals (406a, 406b).

A circuit for driving digital-to-analog converter (DAC) comprising a serializer (110, 210) configured to combine multiple signals to one input signal to drive a forward inverter (311) coupled to a first node (A) with a first impedance in serial configuration and a first capacitance (C1) in shunt configuration. The circuit includes a chain of inverters (321, 322) coupled in series to transfer the input signal from the first node (A) to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter (425) between the third node and the first node (A) to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node (A). A second feedback inverter (425) can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter (425) is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

The invention provides an optical module and a link optimization method and system. The method comprises the following steps that: the microcontroller issues a gain value, so that the continuous time linear equalizer performs equalization processing on an input voltage signal; the time processing module is used for sampling a voltage signal output by the continuous time linear equalizer to obtain sampling data; and the microcontroller determines the gain configuration of the continuous time linear equalizer based on the sampling data under different gain values. Compared with the prior art, the power consumption and the time delay of the module are equal to those of a traditional LPO, and meanwhile, the self-adaptive capability which is only achieved by a DSP scheme in the past is obtained. The application scene and deployment flexibility of the LPO technology are expanded; and meanwhile, the link performance can be always maintained near the optimal point, so that the risk that the performance is continuously deteriorated until error codes occur is fundamentally avoided, and intelligent maintenance of the link state is realized.

A circuit includes a transformer including a primary coil and a secondary coil, the primary coil and the secondary coil being inductively coupled to one another. The circuit further includes an excitation driver circuit having a driver input and a driver output. The driver output is coupled to the primary coil and a clock circuit having a clock output is coupled to the driver input. Furthermore, the circuit includes a clock detection circuit having a detection input and a detection output, wherein the detection input is coupled to the secondary coil and a data interface circuit having a clock input, a data input and an interface output, the clock input coupled to the detection output. In addition, the circuit includes a load circuit coupled between the interface output and the secondary coil, the load circuit including a modulation input coupled to the interface output.

A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

A transmitter system comprises a mapper configured to map data bits and power information to multiple subcarriers, producing mapped information. A first-level modulator converts this mapped information into subcarrier specifications, each defined by a complex number indicating amplitude and phase. The system includes multiple data stream / power channel digital paths, each with a frequency selector that processes a portion of the subcarrier specifications. An orthogonal subcarrier generator translates these specifications from frequency to time domain, generating baseband real and imaginary signals. A second-level modulator processes these signals with intermediate-frequency sine and cosine waves to produce IF I and IF Q signals. A beamformer modifies the phase and / or amplitude of these signals across multiple antenna channels, creating directed signals. Finally, a combiner adds output signals from each data stream / power channel digital path, directing them to corresponding antenna channel modules, facilitating efficient transmission across multiple channels.

A fiber optic-based communications network includes: a power insertion device, connected to multiple fiber links from a data source, configured to provide power insertion to a hybrid fiber / power cable connected to at least one fiber link of the multiple fiber links; the hybrid fiber / power cable, connecting the power insertion device to a connection interface device, configured to transmit data and power from the power insertion device to the connection interface device; and the connection interface device, configured to provide an interface for connection to an end device via a power over Ethernet (POE)-compatible connection and to provide optical to electrical media conversion for data transmitted from the power insertion device to an end device via the hybrid fiber / power cable and the PoE-compatible connection.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

A circuit is disclosed. The circuit includes a transmitter having an input terminal arranged to receive input data and a transmission node arranged to transmit intermediate data corresponding to the input data, and a receiver having a receive node arranged to receive the intermediate data and an output terminal arranged to produce output data corresponding to the input data, the receiver further including a dV / dt detector circuit coupled to the receive node and arranged to stop the production of the output data at the output terminal when the dV / dt detector circuit detects a rate of change of voltage with respect to time greater than a predetermined threshold.

A digital isolator includes a receiver configured to receive digital raw data at a primary side of the digital isolator. A digital-to-digital encoder is disposed at the primary side of the digital isolator. The digital-to-digital encoder is configured to create coded data. One or more digital isolators are configured to transmit the coded data across a transformer and an isolation barrier to create output coded data. A digital-to digital decoder is disposed at a secondary side of the digital isolator. The digital-to digital decoder is configured to decode the output coded data to create decoded data, determine error in coupling across the digital isolator based on the decoded data and the digital raw data, and provide an error signal based the error in coupling across the digital isolator.

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

The invention provides a non-fragile state estimation method and system of a Chua's circuit system under an error code condition, and belongs to the field of signal processing. The problem that the existing state estimation method cannot consider communication limitation, random change coupling, multiple random time-varying delay, nonlinearity, bounded random noise and estimator gain change at the same time, so that the state estimation performance is reduced is solved. The method comprises the following steps of: sequentially establishing a mathematical model taking a Chua's circuit as a complex network system node, a mathematical model in which a binary bit obtained by coding randomly generates an error code when being transmitted, a mathematical model for recovering a measurement signal after compensating the error code, and a mathematical model of a non-fragile state estimator, and then calculating a node state estimation error. Obtaining an overall estimation error augmentation system of the complex network system, and finally solving the unknown gain of the non-fragile state estimator. And substituting the gain into the non-vulnerability state estimator to realize estimation of the mathematical model taking the Chua's circuit as the complex network system node.

The invention relates to the technical field of visible light communication (VLC), particularly discloses a multi-band CAP digital chaotic encryption method and system in a band-limited visible light communication system, and designs three encryption modes of chaotic constellation mapping, chaotic index selection and chaotic PWC coding. According to the chaotic constellation mapping, the positions of constellation points in the corresponding original constellation set are adjusted according to the constellation bits, and a new chaotic constellation set is obtained; the chaotic index selection is used for scrambling a corresponding relation between two distinguishable constellation modes and two encrypted chaotic constellation sets; and performing sub-band sequence chaotic encryption on m sub-bands obtained after block creation by chaotic PWC coding, disorganizing the sequence of the m sub-bands, and then performing PWC coding. Three encryption modes are designed, when confidential information is located in the coverage range of the VLC system, useful information in the system can be prevented from being eavesdropped by unauthorized malicious users, and therefore the information transmission safety is enhanced.

A fiber optic-based communications network includes: a power insertion device, connected to multiple fiber links from a data source, configured to provide power insertion to a hybrid fiber / power cable connected to at least one fiber link of the multiple fiber links; the hybrid fiber / power cable, connecting the power insertion device to a connection interface device, configured to transmit data and power from the power insertion device to the connection interface device; and the connection interface device, configured to provide an interface for connection to an end device via a power over Ethernet (PoE)-compatible connection and to provide optical to electrical media conversion for data transmitted from the power insertion device to an end device via the hybrid fiber / power cable and the PoE-compatible connection.

In some examples, a method comprises communicating first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is coded via a first coding technique that comprises ON-OFF shift Keying (OOK) with a differential carrier signal. The method also includes communicating second data between the first circuit and the second circuit via the differential communication channel across the galvanic isolation barrier within the circuit package, wherein the second data is coded via a second coding technique comprises differential pulse coding.

In some examples, a method comprises communicating first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is coded via a first coding technique that comprises ON-OFF shift Keying (OOK) with a differential carrier signal. The method also includes communicating second data between the first circuit and the second circuit via the differential communication channel across the galvanic isolation barrier within the circuit package, wherein the second data is coded via a second coding technique comprises differential pulse coding.

According to one embodiment, electronic circuitry includes: transmitting circuitry to output a first waveform including N pulse waveforms (N is a natural number larger than 1) in response to an input signal; transfer circuitry to transfer the first waveform as a second waveform that includes at least N+1 pulse waveforms, via electromagnetic coupling; and receiving circuitry configured to receive the second waveform and determine the input signal based on the at least N+1 pulse waveforms.

The invention belongs to the technical field of digital array processing, and discloses a broadband digital array adaptive equalization method. The calibration component is responsible for generating and transmitting a standard linear frequency modulation signal under the control of an instruction and timing, and transmitting the standard linear frequency modulation signal to each digital component in the array after the standard linear frequency modulation signal is radiated by an internal monitoring network or an external monitoring horn; the digital component is responsible for receiving the radio frequency signal sent by the calibration component, completing signal amplification, frequency mixing, filtering, AD sampling, DDC and other processing under the control of an instruction and timing to obtain baseband IQ data, and then completing automatic calculation and programming of an equalization coefficient based on an adaptive equalization algorithm; the radar control is responsible for sending a control instruction and timing to the digital assembly and the calibration assembly through an optical fiber transmission network, and automatically completing traversal of all digital channels. According to the invention, the digital array has adaptive broadband equalization capability, so that the problem that the broadband performance is reduced due to factors such as temperature drift and device aging in a long-term working process is solved.

The invention discloses a method and a device for adjusting an adaptive weight based on coefficient prediction, and an equalization system. The method comprises the following steps: acquiring a digital signal input to an adaptive equalizer, and predicting a tap coefficient target value of the adaptive equalizer according to the digital signal; acquiring a tap coefficient actual value of the adaptive equalizer for the digital signal; and configuring an adaptive weight for the adaptive equalizer according to the tap coefficient actual value and the tap coefficient target value, so that the tap coefficient actual value of the adaptive equalizer is iteratively updated based on the adaptive weight until the tap coefficient actual value converges. According to the method, the steady-state error can be reduced while the convergence speed is ensured.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

A signal transmission device includes: a signal transmission circuit that transmits a pulse signal from a primary circuit system to a secondary circuit system in an isolated manner; a power supply circuit that generates an output voltage from an input voltage in an isolated manner; first and second abnormality detection circuits that detect an abnormality in the primary circuit system and secondary circuit system; a signal transmission path that transmits an output of the second abnormality detection circuit from the secondary circuit system to the primary circuit system in an isolated manner; and a self-diagnosis circuit that performs self-diagnosis on each of the first and second abnormality detection circuits and the signal transmission path. The first abnormality detection circuit includes, as a diagnostic target, a power supply abnormality detector that detects an abnormality in the power supply circuit. The self-diagnosis circuit first diagnoses on the power supply abnormality detector.