265 results about "Synchronizer" patented technology

The embodiment of the invention provides a synchronization method, a synchronization device, electronic equipment and a storage medium. The synchronization method comprises the following steps: aiming at a thread bundle comprising a plurality of threads, distributing a synchronization channel for a first instruction; the first instruction and the second instruction are synchronized based on the synchronization channels, a dependency relationship exists between the first instruction and the second instruction, the thread bundle corresponds to a plurality of synchronization channel groups, each synchronization channel group comprises at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. The synchronization method uses a synchronization channel mechanism based on an instruction type to realize synchronization of instructions in the thread bundle, effectively realizes decoupling of synchronization channels used by different types of instructions, and expands the number of synchronization channels, thereby improving the processing capability of the thread bundle for a workload, and improving the processing efficiency of the thread bundle. And challenges brought by continuously increasing workloads in the thread bundle can be effectively handled.

Embodiments of the present disclosure relate to synchronizing and managing data. A first event is received from a data source. The first event comprises an envelope comprising schema information associated with the first event. Schema drift is detected based at least in part on the schema information. A signal indicative of the schema drift is emitted to a mapping module. An activation ticket is received from the mapping module. The activation ticket corresponds to an updated mapping profile. The updated mapping profile is based at least in part on the signal. A second event is received from the data source. The second event is bound with the updated mapping profile.

The present disclosure is directed to systems and methods for data synchronization by an edge computing device. The method includes (1) receiving, by a feedback loop interface, a request for an update of a data set via a data-acquisition-and-computing (DAC) engine in an edge computing device, (2) transmitting, by the feedback loop interface, the request for the update of the data set to an actor node in a network; (3) receiving, by the feedback loop interface, an indication regarding the update of the data set from the actor node; and (4) transmitting, by the feedback loop interface, the indication regarding the update of the data set via the DAC engine in the recurring cycle. The DAC engine includes a synchronizer to control sequences in a recurring cycle of the network. The synchronizer communicates with a configuration manager or receives configuration information from network nodes for managing the data set.

A computerized method of information access handover between a first device and a second device of a user is presented. The method comprises displaying, on the first device, a QR code generated by a synchronizer. The method further comprises capturing the QR code with the second device for displaying the data record and providing a registration option for associating the data record with the user at a relying party. The method further comprises performing a web authentication registration and, in response to that the web authentication registration flow has been performed successfully, performing an information access handover and securing process. The information access handover and securing process comprises sharing, by the second device, the unique user identifier and the device identifier with the first device, storing them at the first device, and securing access to the data record. A corresponding system and computer program are provided, too.

The invention belongs to the technical field of clock synchronization, and provides a clock synchronization device and a clock synchronization method of a distributed system. Wherein the distributed system comprises a master node and a plurality of slave nodes, the master node and the slave nodes are in two-way communication, and the clock synchronization device comprises a single-core optical cable, an optical switch and a double-frequency-mixing phase discriminator and is used for connecting the master node and the slave nodes; the optical switch is switched between a communication mode and a short circuit mode; when the optical switch is in a communication mode, the single-core optical cable is connected with the master node for transmitting and the slave node for receiving, or is connected with the slave node for transmitting and the master node for receiving; when the optical switch is in a short-circuit mode, the single-core optical cable is connected with transceiving of the master node or transceiving of the slave node; and the dual-mixing phase discriminator is used for measuring the phase difference between the local clock and the received data recovery clock. According to the invention, respective transmit-receive delays of the master and slave nodes and bidirectional transmission delays between the master and slave nodes can be obtained, the clock difference can be conveniently obtained according to the unidirectional transmission delays, and the synchronization precision is improved.

The embodiment of the invention discloses an asynchronous path acquisition method and device for a chip, electronic equipment and a storage medium. According to the scheme, in the process of performing static time sequence analysis on the test chip, time sequence violation check can be performed on the test chip by adding the time sequence analysis command, the asynchronous path is obtained based on the time sequence violation check result, and the starting endpoint and the ending endpoint of the asynchronous path are traversed, so that the accuracy of the static time sequence analysis is improved. And carrying out preliminary screening on the asynchronous paths according to the traversed clock signals, and excluding associated registers in the asynchronous paths according to beating nodes of a synchronizer so as to realize secondary screening on the asynchronous paths. According to the method, the asynchronous path is captured from the time sequence report in a mode of constructing the time sequence violation, and screening is performed based on the end points of the asynchronous path, so that the capturing and screening efficiency of the asynchronous path is effectively improved.

The invention provides a method and equipment for testing the punctuality precision of a time synchronization device, belongs to the technical field of time frequency, and aims to solve the problems of low test automation, difficulty in quantification of environmental influence, inaccurate evaluation and high result subjectivity in the prior art. The method comprises the following steps: simulating an external signal interruption punctuality scene through a dual-channel radio frequency switch, and synchronously acquiring an output signal (time deviation data compared with a high-precision reference clock) of a time synchronization device and temperature, humidity and air pressure environment data; and analyzing the stability of the crystal oscillator through a TIE algorithm and Arron variance, and correlating modeling to quantify the environmental influence to generate a multi-dimensional evaluation report. The objective performance portrait containing parameters such as frequency drift and stability is provided, the defects of a traditional method are overcome, and a scientific basis is provided for equipment research and development optimization and model selection design.

The invention relates to the technical field of serial interfaces, and discloses a PCIe verification device and system, and the device comprises a bus conversion model unit, a register model unit and a synchronizer unit. The bus conversion model unit is used for receiving an access request sent for the verification component and converting the access request into a command in a specified format; the access request is used for accessing an extended configuration space of the to-be-tested device; the register model unit is used for generating a target expansion configuration space; the target expansion configuration space is used for storing each register value; the command in the specified format is used for accessing a target expansion configuration space; and the synchronizer unit is used for performing data synchronization on the to-be-tested equipment and the target expansion configuration space. According to the scheme, the verification compatibility can be improved while the accuracy of the verification result is ensured, so that each sub-layer can be verified in the development process of each sub-layer of the chip, and the verification convergence rate is improved.

A computerized method of information access handover between a first device and a second device of a user is presented. The method comprises displaying, on the first device, a QR code generated by a synchronizer. The method further comprises capturing the QR code with the second device for displaying the data record and providing a registration option for associating the data record with the user at a relying party. The method further comprises performing a web authentication registration and, in response to that the web authentication registration flow has been performed successfully, performing an information access handover and securing process. The information access handover and securing process comprises sharing, by the second device, the unique user identifier and the device identifier with the first device, storing them at the first device, and securing access to the data record. A corresponding system and computer program are provided, too.

The invention relates to the technical field of gearbox detection, in particular to a gearbox synchronizer dynamic performance detection system based on multi-modal signal fusion, comprising: a working condition simulation module comprising a first simulation unit for simulating a light-load driving working condition and a second simulation unit for simulating a heavy-load driving working condition; comprising a synchronization time length acquisition unit and a peak value acquisition unit; the state determining module is used for judging the performance grade of the synchronizer according to the operation stability characterization value of the synchronizer; the processing module is used for secondarily determining the performance grade of the synchronizer according to the abnormal vibration peak value proportion under the condition that the performance grade of the synchronizer is the second grade; and the strategy determination module is used for determining the reason of the synchronizer at the third grade according to the working condition failure ratio of the synchronizer under the condition that the performance grade of the synchronizer is the third grade. According to the invention, the synchronizer detection accuracy is improved.

A synchronization device is for a vehicle equipped with a plurality of sensors including an image sensor. The synchronization device acquires, as data related to a motion state of the vehicle, first time-series data based on detection data detected by the image sensor and second time-series data based on detection data detected by a sensor other than the image sensor. The synchronization device calculates shift time required for matching the first time-series data with the second time-series data.

The invention discloses a renewable energy coupling hydrogen production control method and system based on a virtual synchronous machine. The control method comprises the steps that a virtual synchronous machine controller obtains renewable energy power generation system parameters; setting a given value of a virtual synchronous machine controller; establishing a power distribution strategy of the ALK hydrogen production system, the PEM hydrogen production system and the electric energy storage device BMS system according to the output active power condition of the renewable energy power generation system; constructing a virtual synchronous machine model of the renewable energy coupling hydrogen production system according to the obtained parameters, and associating the current condition of the coupling hydrogen production system according to the model; output parameters of the virtual synchronous machine model are sent to a grid-side converter, and a switching signal required by a switching tube is generated; and distributing the given output of the power distribution strategy to the corresponding system through the grid-side converter. The problems that an existing system is not high in integration degree, electric power splicing of a renewable energy system and a hydrogen production system is singly considered, and the renewable energy fluctuation stabilizing capacity is limited are solved.

The present application relates to the technical field of audio and video synchronization processing, more particularly to an audio and video synchronization method and system based on TS stream and a storage medium. The method comprises reading TS stream data frames and unpacking the TS stream data frames; a synchronization device acquires and calculates the difference between the PTS of the current frame and the previous frame, determines whether the difference is a TS abnormal data type; when the difference is a TS abnormal data type, the synchronization device further determines the type of the current frame; if the type of the current frame is a video frame, the synchronization device discards the current frame; if the type of the current frame is an audio frame, the synchronization device adjusts the offset value and determines whether the current frame is subjected to decoding processing; if the current frame is subjected to decoding processing, a transcoder performs decoding processing. The present application realizes normal transcoding and audio and video synchronization by offset detection and correction error avoidance stream.

The application relates to the technical field of inductive synchro technology, and discloses an inductive synchro temperature self-adaptive compensation method, device and equipment, wherein the method comprises the following steps: determining initial linear coefficients of an initial linear model; acquiring a current environment temperature and a current measurement angle of the inductive synchro, and determining initial iteration parameters of the initial linear model according to the current environment temperature and the current measurement angle; iteratively updating the initial linear coefficients according to the initial iteration parameters to obtain target linear coefficients, wherein data format conversion is performed in each iteration updating process, and the next iteration is performed according to the conversion result; updating the initial linear model based on the target linear coefficients to obtain an updated target linear model, and determining a measurement angle compensation value of the inductive synchro according to the target linear model. The application can realize high-precision and self-adaptive real-time temperature compensation of the inductive synchro in a hot vacuum environment, and simultaneously adapt to the hardware design and reliability requirements of an aircraft.

Embodiments of the present disclosure relate to the field of processor hardware architecture, and provide an artificial intelligence chip and a computing system. The artificial intelligence chip comprises a first computing core, a shared memory device corresponding to the first computing core, and a data synchronization device. The first computing core is configured to issue a first data request instruction. The data synchronization device is configured to perform a read operation on first data, a flag detection operation, and a synchronization operation according to the first data request instruction. The first data is stored in a global memory device coupled to the artificial intelligence chip. The synchronization operation comprises sending the first data to the shared memory device. The shared memory device is configured to store the first data sent by the data synchronization device for reading by the first computing core. Embodiments of the present disclosure hardwareize data synchronization and retry, significantly reduce communication delay, and release core computing resources of the artificial intelligence chip.

The application relates to the technical field of wireless Mesh networks, and discloses a synchronization method for a wireless Mesh network, wherein the Mesh network comprises a plurality of Mesh network nodes connected to each other, the synchronization method comprises the following steps: obtaining external relative execution time in a Mesh control message received by a Mesh network node; obtaining internal relative execution time saved by the Mesh network node; and correcting the internal relative execution time in the case that the external relative execution time is less than the internal relative execution time. The synchronization operation of the Mesh network node is realized by using the relative time mode, the Mesh network node is clocked by using an internal crystal oscillator, the device of the Mesh network node does not need to quickly re-synchronize the network clock after being powered off and then powered on, and the accuracy of the synchronization operation of the device of the Mesh network node in the Mesh network can be improved. The application further discloses a synchronization device for a wireless Mesh network and an electronic equipment.

Embodiments of a clock synchronization unit of an all-digital phase-locked loop (ADPLL), a successive approximation register (SAR) time-to-digital converter (TDC) of the ADPLL, and a clock synchronization method in the ADPLL are disclosed. In one embodiment, the clock synchronization unit of the ADPLL includes a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation instead. Other embodiments are also described.

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

The utility model belongs to the technical field of industrial automation, and provides an industrial network synchronization device which comprises an installation shell, a network synchronization module is arranged in the installation shell, vertical installation plates are symmetrically arranged on the inner top wall of the installation shell, the network synchronization module is located between the two installation plates, and the network synchronization module is located between the two installation plates. A heat dissipation chamber is formed between one side, far away from the network synchronization module, of the mounting plate and the mounting shell; the network synchronization module further comprises heat dissipation holes, the heat dissipation holes are formed in the side wall, right facing the installation shell, of the installation plate and are distributed in a multi-layer height mode, and a heat dissipation fan is arranged above the network synchronization module. Through the designed heat dissipation structure, the heat dissipation efficiency of the industrial network synchronizer can be improved, and the service life of internal parts can be prolonged.

The application discloses a chip testing method and system, the system comprises: interference synchronization device and interference device; the first end of the interference synchronization device is connected with the measured chip; the second end of the interference synchronization device and one end of the interference device are connected, the third end of the interference synchronization device and the other end of the interference device are connected; wherein, when the interference synchronization device receives the synchronization instruction sent by the measured chip, the interference device generates a synchronization interference signal and tests the measured chip; the measured chip sends a confirmation signal to the interference synchronization device at a fixed time during the test; if the interference synchronization device does not receive the confirmation signal within a preset time, an abnormal signal is sent to the measured chip to output abnormal processing information. Through the accurate control of the timing of the interference signal by the interference synchronization device, the accurate control can make the interference signal coupled with the sensitive instruction, and thus the abnormal performance of the chip under specific interference conditions can be effectively exposed, so that effective fault detection and positioning of the chip can be realized.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

This invention discloses a hardware and software matching method for a synchronization system, comprising the following steps: 1) learning the position of the shift fork synchronization point, the synchronizer slider force, and the synchronization capacity of the synchronization system during self-learning; 2) calculating the required speed difference to be synchronized based on the collected input and output shaft speeds when shifting gears is required; 3) calculating the required shifting force based on the speed difference, the required synchronization time, and the synchronization capacity of the self-learned synchronization system; 4) when the calculated required shifting force is less than the slider force of the target gear synchronizer, only the target gear synchronizer is activated; when the calculated required shifting force is greater than or equal to the slider force of the target gear synchronizer, multiple synchronizers are activated together to eliminate the speed difference. This invention has the advantages of simple structure, more compact layout, and the ability to eliminate speed differences.

The utility model relates to the technical field of synchronizers, in particular to a synchronizer gear hub disc core which comprises a disc core body, a base is installed on the lower surface of the disc core body, four supporting plates are fixedly connected to the side face of the base, and the four supporting plates are all tightly attached to the disc core body. The sides, close to the disc core body, of the four supporting plates are fixedly connected with second clamping plates, the second clamping plates are tightly attached to the disc core body, the sides, close to the disc core body, of the four supporting plates are fixedly connected with first clamping plates, and the sides, away from the base, of the supporting plates are fixedly connected with bent rods. According to the synchronizer gear hub plate core, the problem that in the process of assembling a synchronizer by using the synchronizer gear hub plate core, the synchronizer gear hub plate core often needs to be lifted up, then other synchronizer parts are installed on the synchronizer gear hub plate core, and then a tool needs to be used for controlling the elastic piece for positioning to contract, so that the work of assembling the synchronizer is relatively complex is solved.

The invention relates to a development machine packaging method and system in a K8S cluster, which is characterized in that development machine resources are defined based on CRD and a controller, configuration information is described, and automatic life cycle management is realized in combination with operators; cRD is deployed in a host cluster, and is synchronized to K8S space of each tenant through an exclusive synchronizer; an SSH access path is opened by means of node port type service resources and an exclusive layer 4 forwarding entry; a public network IP path is automatically allocated by using the load balancer type service resources in combination with a metal load balancer component; remote access and safety control of the Zhu service are realized through a gateway, a signature verification mechanism and a domain name system analysis function of list monitoring; and deploying an exclusive daemon process set at each host node.

The invention provides a multi-mode man-machine environment data synchronous acquisition method and system and a medium, and relates to the technical field of human factor engineering and ergonomics. The method is suitable for a multi-mode man-machine environment data synchronous acquisition system, the system comprises master machine environment data acquisition equipment, a clock synchronization device and at least one slave man-machine environment data acquisition equipment, and for the slave man-machine environment data acquisition equipment, the method comprises the following steps: responding to a received clock pulse signal from the clock synchronization device, and transmitting the received clock pulse signal to the master machine environment data acquisition equipment; the received clock pulse signal is used as a clock signal for local data synchronization processing, a first physiological signal is obtained, the clock pulse signal is generated by host machine environment data acquisition equipment based on a clock crystal oscillator of the host machine environment data acquisition equipment and sent to the clock synchronization device, and the frequency of data synchronization processing is smaller than that of the clock pulse signal. Through the method disclosed by the invention, the clock synchronization effect is improved, and the data synchronization processing effect is further improved.

The application discloses a time synchronization device and communication equipment, a PTP sending module receives an Ethernet frame to output a first sending data packet start identification signal and a first sending signal; a time stamp processing module assigns a first current time stamp to a first sending time latch signal, and assigns the first sending time latch signal to a time stamp t1 register; a processor acquires the time stamp t1 to stamp a synchronization message / follow-up message, a PCS receiving module receives to output a first receiving data packet start identification signal; a PTP receiving module analyzes a delay request message to output the first receiving data packet start identification signal; the time stamp processing module assigns a second current time stamp to a first receiving time latch signal, and assigns the first receiving time latch signal to a time stamp t4 register; the processor acquires the time stamp t4 to stamp a delay response message. The application can realize high-precision time synchronization.

The disclosed embodiments provide an instruction synchronization device, chip, computer device, and data processing method. By inserting trigger instructions and wait instructions into an instruction queue and adjusting the count value of a counter using the trigger instructions and wait instructions, the instructions following the wait instruction can only be sent if the count value meets a preset numerical condition. Therefore, the above-mentioned method can control the order in which instructions in the multiple instruction queues are sent, thereby achieving instruction synchronization between the multiple instruction queues. The above-mentioned embodiments use hardware to achieve synchronization between instruction queues, thereby improving the efficiency of the hardware system.

The invention relates to a device and a transmission system for synchronizing symbol clocks during data transmission between a sender and a receiver, the device having an estimation means (30) and a symbol synchronizer (40). An estimation unit (30) receives a first signal (S1) generated by a sender (10) and estimates a phase deviation (POFF) and / or a frequency deviation (FOFF) between a symbol clock of the sender (10) and a symbol clock of a receiver (20) on the basis of the first signal, generates the first signal (S1) on the basis of the symbol clock of the sender, and analyzes and evaluates the first signal in the receiver on the basis of the symbol clock of the receiver. The device (5) initializes the symbol synchronizer (40) on the basis of the evaluated phase deviation (POFF) and / or the evaluated frequency deviation (FOFF). The symbol synchronizer (40) receives a second signal (S2) generated by the sender (10) in order to generate, on the basis of the second signal (S2), an output signal (SO) representing symbols transmitted inside the second signal (S2) synchronized with the symbol clock of the receiver (20).

The invention provides a rotating speed synchronization judgment method during gear shifting of a synchronizer-free gearbox and related equipment, and belongs to the technical field of vehicle control. The control method comprises the steps that according to the rotating speed of a shaft where a joint sleeve is located, the rotating speed of a shaft where joint teeth are located is adjusted through closed-loop control; judging whether the joint teeth and the joint sleeve are synchronous in rotating speed or not; when the rotating speeds are synchronous or asynchronous and the duration is less than or equal to the time threshold, determining that the rotating speed is in a rotating speed synchronous state; and when the rotating speeds are not synchronous and the duration is greater than the time threshold, determining to quit the rotating speed synchronization state. The method can adapt to the working characteristics of the synchronizer-free gearbox, the real synchronous state is effectively recognized, misjudgment caused by instantaneous disturbance is restrained, and the reliability and smoothness of gear shifting control are improved.

The present disclosure provides a game attribute synchronization method, a game attribute synchronization device, a computer readable storage medium and an electronic device, and relates to the technical field of games. The game attribute synchronization method comprises: synchronizing attribute content of a first attribute in an engine layer based on attribute content of a to-be-synchronized game attribute; finding a second attribute corresponding to the first attribute in a script layer according to the first attribute; and synchronizing attribute content of the second attribute based on the attribute content of the to-be-synchronized game attribute. The present disclosure can improve the efficiency of game attribute synchronization in a terminal device.