95 results about "Synchronizer" patented technology

Embodiments of the present disclosure relate to synchronizing and managing data. A first event is received from a data source. The first event comprises an envelope comprising schema information associated with the first event. Schema drift is detected based at least in part on the schema information. A signal indicative of the schema drift is emitted to a mapping module. An activation ticket is received from the mapping module. The activation ticket corresponds to an updated mapping profile. The updated mapping profile is based at least in part on the signal. A second event is received from the data source. The second event is bound with the updated mapping profile.

The invention provides a method and equipment for testing the punctuality precision of a time synchronization device, belongs to the technical field of time frequency, and aims to solve the problems of low test automation, difficulty in quantification of environmental influence, inaccurate evaluation and high result subjectivity in the prior art. The method comprises the following steps: simulating an external signal interruption punctuality scene through a dual-channel radio frequency switch, and synchronously acquiring an output signal (time deviation data compared with a high-precision reference clock) of a time synchronization device and temperature, humidity and air pressure environment data; and analyzing the stability of the crystal oscillator through a TIE algorithm and Arron variance, and correlating modeling to quantify the environmental influence to generate a multi-dimensional evaluation report. The objective performance portrait containing parameters such as frequency drift and stability is provided, the defects of a traditional method are overcome, and a scientific basis is provided for equipment research and development optimization and model selection design.

The present application relates to the technical field of audio and video synchronization processing, more particularly to an audio and video synchronization method and system based on TS stream and a storage medium. The method comprises reading TS stream data frames and unpacking the TS stream data frames; a synchronization device acquires and calculates the difference between the PTS of the current frame and the previous frame, determines whether the difference is a TS abnormal data type; when the difference is a TS abnormal data type, the synchronization device further determines the type of the current frame; if the type of the current frame is a video frame, the synchronization device discards the current frame; if the type of the current frame is an audio frame, the synchronization device adjusts the offset value and determines whether the current frame is subjected to decoding processing; if the current frame is subjected to decoding processing, a transcoder performs decoding processing. The present application realizes normal transcoding and audio and video synchronization by offset detection and correction error avoidance stream.

The application relates to the technical field of inductive synchro technology, and discloses an inductive synchro temperature self-adaptive compensation method, device and equipment, wherein the method comprises the following steps: determining initial linear coefficients of an initial linear model; acquiring a current environment temperature and a current measurement angle of the inductive synchro, and determining initial iteration parameters of the initial linear model according to the current environment temperature and the current measurement angle; iteratively updating the initial linear coefficients according to the initial iteration parameters to obtain target linear coefficients, wherein data format conversion is performed in each iteration updating process, and the next iteration is performed according to the conversion result; updating the initial linear model based on the target linear coefficients to obtain an updated target linear model, and determining a measurement angle compensation value of the inductive synchro according to the target linear model. The application can realize high-precision and self-adaptive real-time temperature compensation of the inductive synchro in a hot vacuum environment, and simultaneously adapt to the hardware design and reliability requirements of an aircraft.

Embodiments of the present disclosure relate to the field of processor hardware architecture, and provide an artificial intelligence chip and a computing system. The artificial intelligence chip comprises a first computing core, a shared memory device corresponding to the first computing core, and a data synchronization device. The first computing core is configured to issue a first data request instruction. The data synchronization device is configured to perform a read operation on first data, a flag detection operation, and a synchronization operation according to the first data request instruction. The first data is stored in a global memory device coupled to the artificial intelligence chip. The synchronization operation comprises sending the first data to the shared memory device. The shared memory device is configured to store the first data sent by the data synchronization device for reading by the first computing core. Embodiments of the present disclosure hardwareize data synchronization and retry, significantly reduce communication delay, and release core computing resources of the artificial intelligence chip.

The application relates to the technical field of wireless Mesh networks, and discloses a synchronization method for a wireless Mesh network, wherein the Mesh network comprises a plurality of Mesh network nodes connected to each other, the synchronization method comprises the following steps: obtaining external relative execution time in a Mesh control message received by a Mesh network node; obtaining internal relative execution time saved by the Mesh network node; and correcting the internal relative execution time in the case that the external relative execution time is less than the internal relative execution time. The synchronization operation of the Mesh network node is realized by using the relative time mode, the Mesh network node is clocked by using an internal crystal oscillator, the device of the Mesh network node does not need to quickly re-synchronize the network clock after being powered off and then powered on, and the accuracy of the synchronization operation of the device of the Mesh network node in the Mesh network can be improved. The application further discloses a synchronization device for a wireless Mesh network and an electronic equipment.

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

The utility model belongs to the technical field of industrial automation, and provides an industrial network synchronization device which comprises an installation shell, a network synchronization module is arranged in the installation shell, vertical installation plates are symmetrically arranged on the inner top wall of the installation shell, the network synchronization module is located between the two installation plates, and the network synchronization module is located between the two installation plates. A heat dissipation chamber is formed between one side, far away from the network synchronization module, of the mounting plate and the mounting shell; the network synchronization module further comprises heat dissipation holes, the heat dissipation holes are formed in the side wall, right facing the installation shell, of the installation plate and are distributed in a multi-layer height mode, and a heat dissipation fan is arranged above the network synchronization module. Through the designed heat dissipation structure, the heat dissipation efficiency of the industrial network synchronizer can be improved, and the service life of internal parts can be prolonged.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

The utility model relates to the technical field of synchronizers, in particular to a synchronizer gear hub disc core which comprises a disc core body, a base is installed on the lower surface of the disc core body, four supporting plates are fixedly connected to the side face of the base, and the four supporting plates are all tightly attached to the disc core body. The sides, close to the disc core body, of the four supporting plates are fixedly connected with second clamping plates, the second clamping plates are tightly attached to the disc core body, the sides, close to the disc core body, of the four supporting plates are fixedly connected with first clamping plates, and the sides, away from the base, of the supporting plates are fixedly connected with bent rods. According to the synchronizer gear hub plate core, the problem that in the process of assembling a synchronizer by using the synchronizer gear hub plate core, the synchronizer gear hub plate core often needs to be lifted up, then other synchronizer parts are installed on the synchronizer gear hub plate core, and then a tool needs to be used for controlling the elastic piece for positioning to contract, so that the work of assembling the synchronizer is relatively complex is solved.

The invention relates to a development machine packaging method and system in a K8S cluster, which is characterized in that development machine resources are defined based on CRD and a controller, configuration information is described, and automatic life cycle management is realized in combination with operators; cRD is deployed in a host cluster, and is synchronized to K8S space of each tenant through an exclusive synchronizer; an SSH access path is opened by means of node port type service resources and an exclusive layer 4 forwarding entry; a public network IP path is automatically allocated by using the load balancer type service resources in combination with a metal load balancer component; remote access and safety control of the Zhu service are realized through a gateway, a signature verification mechanism and a domain name system analysis function of list monitoring; and deploying an exclusive daemon process set at each host node.

The invention provides a multi-mode man-machine environment data synchronous acquisition method and system and a medium, and relates to the technical field of human factor engineering and ergonomics. The method is suitable for a multi-mode man-machine environment data synchronous acquisition system, the system comprises master machine environment data acquisition equipment, a clock synchronization device and at least one slave man-machine environment data acquisition equipment, and for the slave man-machine environment data acquisition equipment, the method comprises the following steps: responding to a received clock pulse signal from the clock synchronization device, and transmitting the received clock pulse signal to the master machine environment data acquisition equipment; the received clock pulse signal is used as a clock signal for local data synchronization processing, a first physiological signal is obtained, the clock pulse signal is generated by host machine environment data acquisition equipment based on a clock crystal oscillator of the host machine environment data acquisition equipment and sent to the clock synchronization device, and the frequency of data synchronization processing is smaller than that of the clock pulse signal. Through the method disclosed by the invention, the clock synchronization effect is improved, and the data synchronization processing effect is further improved.

The application discloses a time synchronization device and communication equipment, a PTP sending module receives an Ethernet frame to output a first sending data packet start identification signal and a first sending signal; a time stamp processing module assigns a first current time stamp to a first sending time latch signal, and assigns the first sending time latch signal to a time stamp t1 register; a processor acquires the time stamp t1 to stamp a synchronization message / follow-up message, a PCS receiving module receives to output a first receiving data packet start identification signal; a PTP receiving module analyzes a delay request message to output the first receiving data packet start identification signal; the time stamp processing module assigns a second current time stamp to a first receiving time latch signal, and assigns the first receiving time latch signal to a time stamp t4 register; the processor acquires the time stamp t4 to stamp a delay response message. The application can realize high-precision time synchronization.

The present disclosure provides a game attribute synchronization method, a game attribute synchronization device, a computer readable storage medium and an electronic device, and relates to the technical field of games. The game attribute synchronization method comprises: synchronizing attribute content of a first attribute in an engine layer based on attribute content of a to-be-synchronized game attribute; finding a second attribute corresponding to the first attribute in a script layer according to the first attribute; and synchronizing attribute content of the second attribute based on the attribute content of the to-be-synchronized game attribute. The present disclosure can improve the efficiency of game attribute synchronization in a terminal device.

A shield tunneling and segment assembling synchronization device (100), a control method therefor and a thrust allocation method therefor, and a shield machine (200). The shield tunneling and segment assembling synchronization device (100) comprises a thrust cylinder assembly (110), a segment assembling assembly (120), and a controller (140); the controller (140) is configured to activate a semi-shield tunneling and segment assembling synchronization mode when the advance speed of the shield machine (200) is greater than or equal to a preset speed or when it is detected that the tunnel strata belong to a first type of strata; the controller (140) is configured to activate a full-shield tunneling and segment assembling synchronization mode when the advance speed of the shield machine (200) is less than the preset speed or when it is detected that the tunnel strata belong to a second type of strata; and the hardness of the first type of strata is less than that of the second type of strata.

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

The present disclosure relates to apparatuses and methods for delay measurement initialization. An example apparatus includes a clock enable circuit that provides a first clock signal having one-half the frequency of an input clock signal and a second clock signal having one-quarter the frequency of the input clock signal, a coarse delay that provides the first clock signal with a coarse delay, a fine delay that provides the first clock signal with the coarse delay and a fine delay as an output clock signal, a model delay that has a feedback delay equal to the sum of the delays of an input stage and an output stage and that provides a feedback signal that is the output clock signal with the feedback delay, and a measurement initialization circuit that performs measurement initialization. The measurement initialization circuit includes a synchronizer that receives the feedback signal and the second clock signal and provides a stop signal to the coarse delay.

This invention provides a synchronizer gear ring structure, belonging to the field of automotive parts. It solves the problem of poor lifespan of existing gear rings. This synchronizer gear ring structure includes an outer ring and an inner ring. An annular shoulder is formed on the inner wall of the lower end of the outer ring, and the bottom surface of the inner ring is pressed tightly against the annular shoulder. An annular cavity is formed between the inner ring, outer ring, and annular shoulder. A plastic ring is placed inside the annular cavity, formed by injection molding and becoming an integral part of the inner and outer rings. A first strip groove runs axially through the outer wall of the inner ring, and a second strip groove runs axially on the inner wall of the outer ring. A key block 1, matching the first strip groove, extends integrally from the inner wall of the plastic ring towards the first strip groove, and a second key block 2, matching the second strip groove, extends integrally from the outer wall of the plastic ring towards the second strip groove. This synchronizer gear ring structure has a long lifespan.

Hardware synchronization method for computers. One aspect of the invention relates to a method, implemented by a synchronization device, for synchronizing a second computer with a first computer, the synchronization device being included in the second computer, the synchronization device being a configurable integrated circuit.

The utility model discloses a multifunctional time code synchronizer, which comprises an MCU (Microprogrammed Control Unit) module, a control panel connected with the MCU module, a power supply module connected with the MCU module, a plurality of interface modules and an interface circuit connected between the interface modules and the MCU module, the interface module at least comprises an MIDI IN interface and an MIDI OUT interface which can be used for transmitting an MIDI time code, an LTC IN interface and an LTC OUT interface which can be used for transmitting an SMPTE LTC time code, and an Ethernet port which can be used for transmitting an RTP MIDI time code and an ArtTimecode time code, and the MCU module can transmit and synchronize corresponding time code information through an interface circuit connected with the MIDI IN interface, the MIDI OUT interface, the LTC IN interface, the LTC OUT interface and the Ethernet port. Compared with the prior art, the device has the synchronization of the MIDI time code and the SMPTE LTC time code, and also has the network time codes of the ArtTimecode and the RTP-MIDI, so that the LTC time code can be transmitted more flexibly.

A frequency generating device and an operation method thereof are provided. The frequency generating device includes an oscillator circuit and a processor circuit. The oscillator circuit generates a clock signal and adjust a clock frequency of the clock signal according to a control voltage generated by the processor circuit. The processor circuit calculates a current frequency aging rate value based on a current clock frequency. The processor circuit calculates a control voltage regulation rate value based on the current frequency aging rate value and a control voltage slope, and compensates the control voltage based on the control voltage regulation rate value in the holdover state. Alternatively, the processor circuit calculates a frequency regulation value based on the current frequency aging rate value and an oscillator resolution of the synchronizer, and provides the frequency regulation value to the synchronizer in the holdover state to compensate an output frequency of the synchronizer.

Embodiments of this disclosure provide an asynchronous signal transmission circuit, method, chip, and electronic device. The asynchronous signal transmission circuit includes a synchronization circuit, a comparison circuit, and a storage circuit. The synchronization circuit is configured to sample asynchronous input data using at least two synchronizers based on a target clock signal and output first sampled data. The target clock signal is the clock signal of the target circuit. The comparison circuit is configured to compare the first sampled data with second sampled data delayed from the first sampled data, and output a comparison result and second sampled data to the storage circuit. The storage circuit is configured to store the output data and determine whether to update the stored output data with the second sampled data based on the comparison result. This solves the problems of current asynchronous signal transmission methods, such as sampling incorrect intermediate values ​​or being unable to use circuits that are difficult to provide handshake signals.

A kind of synchronous timing control system for strong laser plasma interaction experiment, including a femtosecond laser device, a square wave signal generator, a jet signal synchronizer, three delay timers, a 12-way signal synchronizer, two shutter controllers, a YAG laser, a jet controller, multiple experimental acquisition instruments including an electron spectrometer, a rear imaging CCD, a spectrometer CCD.The present application is mainly applied to the field of strong laser plasma interaction, which can accurately control the interaction time of femtosecond laser pulse and nanosecond gate plasma channel, and accurately control the start acquisition time and acquisition duration of various experimental data, improve the signal-to-noise ratio, and the whole timing system is very easy to adjust.The present application also has strong expansibility, when ionized gas is not needed to form plasma channel, the 1Hz pulse signal timing of the right half of the dashed line can be removed, so that the interaction time of femtosecond laser pulse and millisecond gate jet gas can be accurately controlled.The expansibility of the present application is also reflected in that enough output ports have been reserved, and suitable functional elements can be connected subsequently.

The embodiment of the invention provides a time synchronization method and synchronization device for a multimode redundancy computer system level, and the method comprises the steps: each module has a handshake pulse receiving moment and a handshake pulse generating moment at the same time in a preset synchronization time period, which indicates that the two modules are used as a target module when the handshake synchronization is successful; acquiring a handshake pulse receiving moment and a handshake pulse generating moment of the target module from a handshake synchronization sub-module of the target module through a clock phase locking synchronous control state machine of the target module; a clock phase difference of each target module is determined through a timer comparison output logic unit of each target module according to a handshake pulse receiving moment and a handshake pulse generating moment of the target module; and adopting a synchronization pulse to adjust a square wave signal for timing the local clock of the target module according to the phase difference, so that the phase of the clock of the target module is synchronized. And the time synchronization of the flight control computer with multimode system level redundancy is realized.

High-precision wireless synchronization can be achieved between multiple devices. [Solution] The synchronization device comprises a control unit, a clock, and a synchronization unit, wherein the clock is equipped with a self-propelled oscillator that acts as a clock source, and the synchronization unit controls its own oscillator to synchronize with an oscillator provided by another synchronization device. Furthermore, the synchronization unit controls the rise time of its own oscillator to synchronize its frequency and phase with an oscillator provided by another synchronization device.

Embodiments of the present application provide a cache synchronization method, a cache synchronization device, a computer device and a computer readable storage medium, and relate to the technical field of double control storage devices. The method comprises: receiving write data; recording the write data into each memory block device of a storage pool configured by a first controller, the storage pool comprising at least a first memory block device created based on the memory of the first controller and a second memory block device created based on the memory of a second controller and mapped to a remote block device in the first controller; and transmitting the write data to the second memory block device of the second controller through a cache channel between the first controller and the second controller; wherein the cache channel is created based on a high-speed network card supporting remote direct data access (RDMA). In the cache synchronization process, the present application does not need to modify the system internally, and can ensure stability while realizing low threshold and small difficulty.

The invention provides a database synchronization method which can be applied to the technical field of big data. The method comprises the steps of obtaining at least one source database, a target database and a synchronization object of the source database; based on the type of the target database, the synchronization object and a preset mapping rule, obtaining full data synchronization logic and incremental data synchronization logic; based on the full-amount data synchronization logic, the source database is subjected to full-amount synchronization to the target database, and a full-amount synchronization starting timestamp is recorded; in response to the source database generating incremental data after the full synchronization start timestamp, the incremental data is synchronized to the target database based on incremental data synchronization logic. The invention further provides a database synchronization device and equipment, a storage medium and a program product.

A multi-node server, a method and an apparatus applied to the multi-node server, and a medium are provided by the present application, The multi-node server includes a master node, a slave node, a power-on synchronization apparatus, and at least one shared card shared between the master node and the slave node; the target shared card is connected to the master node and the slave node, and the master node and the slave node are configured to supply power to the target shared card. The power-on synchronization apparatus includes an isolation module, a master node signal interconnection module, and a slave node signal interconnection module. The master node signal interconnection module is connected to the master node. The slave node signal interconnection module is connected to the slave node.

A laser automatic compensation control device includes a controller, a digital array, a decoder, a compensation array and a synchronizer. The controller is configured for receiving a number of laser energy signals and comparing each laser energy signal with a corresponding preset energy value to obtain a corresponding output digital signal. The digital array is electrically connected to the controller and configured for storing the output digital signals. The decoder is electrically connected to the digital array and configured for converting the output digital signals into a number of analog compensation signals. The compensation array is electrically connected to the decoder and configured for storing the analog compensation signals. The synchronizer is electrically connected to the compensation array and configured for receiving the analog compensation signals, and synchronously outputting the analog compensation signals to a laser diode array.

The application designs a synchronizer qualified product determination method, electronic equipment and storage medium. The determination method comprises the following steps: positioning the graduation circle of the combination tooth, the circumference of the graduation circle intersects with the first side to form an intersection point, and the plane where a plurality of intersection points are located is used as a reference section; on the reference section, the intersection point is used as a starting point, a reference line is drawn along the first side, and the end point of the reference line is used as a reference point; a reference circle is drawn on the reference section, so that as many reference points as possible fall into the circumference of the reference circle; based on the number of the reference points falling into the circumference and the parameters of the reference circle, it is determined whether the synchronizer is a qualified product. The determination method provided by the application is simple and easy to operate, greatly reduces the workload of obtaining and calculating detection data, shortens the detection time, can quickly determine whether the synchronizer is a qualified product, and reduces the detection cost.