355 results about "Synchronizer" patented technology

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

The invention relates to a virtual synchronous machine transient stability optimization control system and method, and the method comprises the steps: sampling a three-phase power grid to detect the angular frequency of a power grid in real time, carrying out the subtraction of the angular frequency and the angular frequency outputted by an active-frequency control module of a virtual synchronous machine, multiplying a coefficient, and introducing into a reactive-voltage control module. The voltage sag dynamic state of the virtual synchronous machine under the power grid voltage drop is slowed down by means of angular frequency fluctuation caused by active power adjustment of the virtual synchronous machine under the power grid voltage drop, and the transient voltage supporting capacity of the virtual synchronous machine under the fault is improved. Under stable operation, the output angular frequency of the active power-frequency control module of the virtual synchronous machine is equal to the angular frequency of the power grid, so that the additional loop has no influence on the virtual synchronous machine during stable operation. According to the invention, the difference between the power grid angular frequency and the output angular frequency of the active-frequency control module is introduced into the reactive-voltage control module, so that the system can maintain good damping characteristics during the transient period, and the transient stability of the virtual synchronous machine system is improved.

The embodiment of the invention provides a synchronization method, a synchronization device, electronic equipment and a storage medium. The synchronization method comprises the following steps: aiming at a thread bundle comprising a plurality of threads, distributing a synchronization channel for a first instruction; the first instruction and the second instruction are synchronized based on the synchronization channels, a dependency relationship exists between the first instruction and the second instruction, the thread bundle corresponds to a plurality of synchronization channel groups, each synchronization channel group comprises at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. The synchronization method uses a synchronization channel mechanism based on an instruction type to realize synchronization of instructions in the thread bundle, effectively realizes decoupling of synchronization channels used by different types of instructions, and expands the number of synchronization channels, thereby improving the processing capability of the thread bundle for a workload, and improving the processing efficiency of the thread bundle. And challenges brought by continuously increasing workloads in the thread bundle can be effectively handled.

Embodiments of the present disclosure relate to synchronizing and managing data. A first event is received from a data source. The first event comprises an envelope comprising schema information associated with the first event. Schema drift is detected based at least in part on the schema information. A signal indicative of the schema drift is emitted to a mapping module. An activation ticket is received from the mapping module. The activation ticket corresponds to an updated mapping profile. The updated mapping profile is based at least in part on the signal. A second event is received from the data source. The second event is bound with the updated mapping profile.

The invention provides a synchronization device and method for photon counting communication, and the device comprises an array single photon detection module which is used for outputting single photon pulse signals PHOTOON1, PHOTOON2,..., PHOTOONn after receiving communication photons; the gating signal module is used for outputting M gating signals; the multi-path signal counting processing module is used for counting all the single photon pulse signals according to each gating signal so as to output M total count values; the comparison module is used for screening out the maximum total count value from the M total count values; and the synchronous clock selection module is used for selecting a target gating signal corresponding to the maximum total count value from the M gating signals as a synchronous clock. The synchronization device designed by the invention is simple in structure, system resources are saved, the problem of counting loss under photon pulse signal stacking is effectively optimized, and the synchronization device is suitable for single-photon communication under a long-distance weak link when an array single-photon detector is adopted by a receiving end.

The present disclosure is directed to systems and methods for data synchronization by an edge computing device. The method includes (1) receiving, by a feedback loop interface, a request for an update of a data set via a data-acquisition-and-computing (DAC) engine in an edge computing device, (2) transmitting, by the feedback loop interface, the request for the update of the data set to an actor node in a network; (3) receiving, by the feedback loop interface, an indication regarding the update of the data set from the actor node; and (4) transmitting, by the feedback loop interface, the indication regarding the update of the data set via the DAC engine in the recurring cycle. The DAC engine includes a synchronizer to control sequences in a recurring cycle of the network. The synchronizer communicates with a configuration manager or receives configuration information from network nodes for managing the data set.

A computerized method of information access handover between a first device and a second device of a user is presented. The method comprises displaying, on the first device, a QR code generated by a synchronizer. The method further comprises capturing the QR code with the second device for displaying the data record and providing a registration option for associating the data record with the user at a relying party. The method further comprises performing a web authentication registration and, in response to that the web authentication registration flow has been performed successfully, performing an information access handover and securing process. The information access handover and securing process comprises sharing, by the second device, the unique user identifier and the device identifier with the first device, storing them at the first device, and securing access to the data record. A corresponding system and computer program are provided, too.

The invention belongs to the technical field of clock synchronization, and provides a clock synchronization device and a clock synchronization method of a distributed system. Wherein the distributed system comprises a master node and a plurality of slave nodes, the master node and the slave nodes are in two-way communication, and the clock synchronization device comprises a single-core optical cable, an optical switch and a double-frequency-mixing phase discriminator and is used for connecting the master node and the slave nodes; the optical switch is switched between a communication mode and a short circuit mode; when the optical switch is in a communication mode, the single-core optical cable is connected with the master node for transmitting and the slave node for receiving, or is connected with the slave node for transmitting and the master node for receiving; when the optical switch is in a short-circuit mode, the single-core optical cable is connected with transceiving of the master node or transceiving of the slave node; and the dual-mixing phase discriminator is used for measuring the phase difference between the local clock and the received data recovery clock. According to the invention, respective transmit-receive delays of the master and slave nodes and bidirectional transmission delays between the master and slave nodes can be obtained, the clock difference can be conveniently obtained according to the unidirectional transmission delays, and the synchronization precision is improved.

The embodiment of the invention discloses a data synchronization method. The method comprises the steps that primary key information of a to-be-synchronized data table in a source database is determined; determining a target data table used for synchronously storing data in the to-be-synchronized data table in a target database; determining data processing parameters based on the to-be-synchronized data table, the target data table, the primary key information and synchronous configuration; based on the data processing parameters and the synchronization configuration, processing data in the to-be-synchronized data table to obtain a target synchronization data set; and synchronizing the target synchronous data set to the target data table. The embodiment of the invention also discloses a data synchronization device and equipment, a storage medium and a computer program product.

The embodiment of the invention discloses an asynchronous path acquisition method and device for a chip, electronic equipment and a storage medium. According to the scheme, in the process of performing static time sequence analysis on the test chip, time sequence violation check can be performed on the test chip by adding the time sequence analysis command, the asynchronous path is obtained based on the time sequence violation check result, and the starting endpoint and the ending endpoint of the asynchronous path are traversed, so that the accuracy of the static time sequence analysis is improved. And carrying out preliminary screening on the asynchronous paths according to the traversed clock signals, and excluding associated registers in the asynchronous paths according to beating nodes of a synchronizer so as to realize secondary screening on the asynchronous paths. According to the method, the asynchronous path is captured from the time sequence report in a mode of constructing the time sequence violation, and screening is performed based on the end points of the asynchronous path, so that the capturing and screening efficiency of the asynchronous path is effectively improved.

The invention provides a method and equipment for testing the punctuality precision of a time synchronization device, belongs to the technical field of time frequency, and aims to solve the problems of low test automation, difficulty in quantification of environmental influence, inaccurate evaluation and high result subjectivity in the prior art. The method comprises the following steps: simulating an external signal interruption punctuality scene through a dual-channel radio frequency switch, and synchronously acquiring an output signal (time deviation data compared with a high-precision reference clock) of a time synchronization device and temperature, humidity and air pressure environment data; and analyzing the stability of the crystal oscillator through a TIE algorithm and Arron variance, and correlating modeling to quantify the environmental influence to generate a multi-dimensional evaluation report. The objective performance portrait containing parameters such as frequency drift and stability is provided, the defects of a traditional method are overcome, and a scientific basis is provided for equipment research and development optimization and model selection design.

The invention relates to the technical field of serial interfaces, and discloses a PCIe verification device and system, and the device comprises a bus conversion model unit, a register model unit and a synchronizer unit. The bus conversion model unit is used for receiving an access request sent for the verification component and converting the access request into a command in a specified format; the access request is used for accessing an extended configuration space of the to-be-tested device; the register model unit is used for generating a target expansion configuration space; the target expansion configuration space is used for storing each register value; the command in the specified format is used for accessing a target expansion configuration space; and the synchronizer unit is used for performing data synchronization on the to-be-tested equipment and the target expansion configuration space. According to the scheme, the verification compatibility can be improved while the accuracy of the verification result is ensured, so that each sub-layer can be verified in the development process of each sub-layer of the chip, and the verification convergence rate is improved.

The invention provides a distributed Internet of Things simulation system based on time synchronization, event driving and a message bus, and the system comprises a simulation model which is used for simulating different types of Internet of Things equipment or communication entities; the model management system is used for managing and controlling the life cycle, configuration and version management of the simulation model so as to ensure that the system adds, deletes or modifies different simulation models; the time synchronizer is used for ensuring that all nodes in distributed simulation keep a unified time reference so as to ensure the sequence and synchronous execution of events; the message bus is used for transmitting messages, events and data among the simulation nodes so as to ensure real-time communication and cooperation of each unit in the distributed system; and the front-end interface is used for monitoring a simulation process, operating equipment and checking simulation data in real time. According to the invention, the problem of low operation and maintenance efficiency of Internet of Things simulation software in the prior art can be solved.

A computerized method of information access handover between a first device and a second device of a user is presented. The method comprises displaying, on the first device, a QR code generated by a synchronizer. The method further comprises capturing the QR code with the second device for displaying the data record and providing a registration option for associating the data record with the user at a relying party. The method further comprises performing a web authentication registration and, in response to that the web authentication registration flow has been performed successfully, performing an information access handover and securing process. The information access handover and securing process comprises sharing, by the second device, the unique user identifier and the device identifier with the first device, storing them at the first device, and securing access to the data record. A corresponding system and computer program are provided, too.

The invention discloses a control plane and data plane decoupling message transmission method, device and equipment, and the method comprises the steps: carrying out the interaction with a Socket interface of a kernel through a control plane protocol in a user mode, transmitting a protocol message through the Socket interface and a data forwarding module, and dynamically generating a far-end routing table according to the protocol message; issuing the far-end routing table to a kernel through the control plane protocol, and synchronizing the far-end routing table to a data forwarding module outside the kernel through a synchronizer component outside the kernel by the kernel; and forwarding a service message through the data forwarding module according to the remote routing table, synchronizing the learned local routing table item to the kernel through the synchronizer component, and synchronizing the learned local routing table item to the control plane protocol through the kernel. Therefore, the problem of how to issue a remote routing table of a data plane to a user mode VPP / OVS / hardware chip to guide data forwarding under the condition that a control plane protocol and a user plane protocol are not greatly modified is solved.

The invention relates to the technical field of gearbox detection, in particular to a gearbox synchronizer dynamic performance detection system based on multi-modal signal fusion, comprising: a working condition simulation module comprising a first simulation unit for simulating a light-load driving working condition and a second simulation unit for simulating a heavy-load driving working condition; comprising a synchronization time length acquisition unit and a peak value acquisition unit; the state determining module is used for judging the performance grade of the synchronizer according to the operation stability characterization value of the synchronizer; the processing module is used for secondarily determining the performance grade of the synchronizer according to the abnormal vibration peak value proportion under the condition that the performance grade of the synchronizer is the second grade; and the strategy determination module is used for determining the reason of the synchronizer at the third grade according to the working condition failure ratio of the synchronizer under the condition that the performance grade of the synchronizer is the third grade. According to the invention, the synchronizer detection accuracy is improved.

The invention relates to a time synchronization device, and the device comprises an FPGA chip which is used for dividing the clock frequency of a received initial clock synchronization signal into a first clock frequency point and a second clock frequency point; the clock chip comprises a first phase-locked loop and a second phase-locked loop, and the first phase-locked loop is used for obtaining a system clock according to the first clock frequency point and sending the system clock to the second phase-locked loop; the second phase-locked loop is used for acquiring the PTP clock offset frequency according to the system clock and sending the PTP clock offset frequency to the FPGA chip; the FPGA chip comprises a pulse generator, and the pulse generator is used for generating a pulse signal per second and adjusting the phase of the pulse signal per second according to the PTP clock offset frequency, so that the phase is consistent with the pulse phase per second of the initial clock synchronization signal, and time synchronization is completed. According to the application, clock synchronization of the application equipment and the upstream equipment is realized by utilizing the FPGA chip and the clock chip.

The invention provides a GPU synchronization device and an image processing system. The synchronization device comprises a first processing unit used for receiving a preset effective clock signal and outputting the effective clock signal to at least one GPU; the second processing unit is used for receiving the first frame synchronization signal of the at least one GPU and outputting a second frame synchronization signal to the at least one GPU; wherein the second frame synchronization signal is an effective synchronization signal under the condition that the first frame synchronization signal indicates that the GPU is in a frame synchronization state; the effective synchronization signal is used for indicating that the at least one GPU is in a frame synchronization state; and based on the effective clock signal, the GPU outputs frame data to be displayed in a state that the second frame synchronization signal is the effective synchronization signal.

The model learning unit (401) performs a learning process for estimating the time of the base host based on the time synchronization information of the sub-base host. The inference unit (402) estimates the time of the base host based on the time synchronization information of the sub-base host using the learned model obtained by the learning process. The synchronization control unit (204) performs time synchronization according to the acquired time when the time is obtained from the base host, and performs time synchronization according to the time estimated by the inference unit (402) when the time is not obtained from the base host.

A synchronization device is for a vehicle equipped with a plurality of sensors including an image sensor. The synchronization device acquires, as data related to a motion state of the vehicle, first time-series data based on detection data detected by the image sensor and second time-series data based on detection data detected by a sensor other than the image sensor. The synchronization device calculates shift time required for matching the first time-series data with the second time-series data.

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. Synchronizer flip-flop circuit (100) includes a first latch sub-circuit (112) coupled to receive input data (101) and a second latch sub-circuit (117) coupled to the first latch sub-circuit (112). The first latch subcircuit (112) includes a first group of inverters, a first diode-connected transistor (113) coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor (114) coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.

The invention provides a time synchronization method, which comprises the following steps: in response to a first edge of a received time reference signal, acquiring a first system time value and first duration information sent by a master device; determining a second system time value according to the first duration information, wherein the precision of the second system time value is higher than that of the first system time value; and according to the first system time value, the second system time value and the local time of the to-be-synchronized device, determining a time deviation between the to-be-synchronized device and the master device so as to synchronize the local time of the to-be-synchronized device with the master device based on the time deviation. The invention further provides a time synchronization device.

A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

The invention discloses a renewable energy coupling hydrogen production control method and system based on a virtual synchronous machine. The control method comprises the steps that a virtual synchronous machine controller obtains renewable energy power generation system parameters; setting a given value of a virtual synchronous machine controller; establishing a power distribution strategy of the ALK hydrogen production system, the PEM hydrogen production system and the electric energy storage device BMS system according to the output active power condition of the renewable energy power generation system; constructing a virtual synchronous machine model of the renewable energy coupling hydrogen production system according to the obtained parameters, and associating the current condition of the coupling hydrogen production system according to the model; output parameters of the virtual synchronous machine model are sent to a grid-side converter, and a switching signal required by a switching tube is generated; and distributing the given output of the power distribution strategy to the corresponding system through the grid-side converter. The problems that an existing system is not high in integration degree, electric power splicing of a renewable energy system and a hydrogen production system is singly considered, and the renewable energy fluctuation stabilizing capacity is limited are solved.

The present application relates to the technical field of audio and video synchronization processing, more particularly to an audio and video synchronization method and system based on TS stream and a storage medium. The method comprises reading TS stream data frames and unpacking the TS stream data frames; a synchronization device acquires and calculates the difference between the PTS of the current frame and the previous frame, determines whether the difference is a TS abnormal data type; when the difference is a TS abnormal data type, the synchronization device further determines the type of the current frame; if the type of the current frame is a video frame, the synchronization device discards the current frame; if the type of the current frame is an audio frame, the synchronization device adjusts the offset value and determines whether the current frame is subjected to decoding processing; if the current frame is subjected to decoding processing, a transcoder performs decoding processing. The present application realizes normal transcoding and audio and video synchronization by offset detection and correction error avoidance stream.

The application relates to the technical field of inductive synchro technology, and discloses an inductive synchro temperature self-adaptive compensation method, device and equipment, wherein the method comprises the following steps: determining initial linear coefficients of an initial linear model; acquiring a current environment temperature and a current measurement angle of the inductive synchro, and determining initial iteration parameters of the initial linear model according to the current environment temperature and the current measurement angle; iteratively updating the initial linear coefficients according to the initial iteration parameters to obtain target linear coefficients, wherein data format conversion is performed in each iteration updating process, and the next iteration is performed according to the conversion result; updating the initial linear model based on the target linear coefficients to obtain an updated target linear model, and determining a measurement angle compensation value of the inductive synchro according to the target linear model. The application can realize high-precision and self-adaptive real-time temperature compensation of the inductive synchro in a hot vacuum environment, and simultaneously adapt to the hardware design and reliability requirements of an aircraft.

The invention provides a multivariate parameter driven synchronizer structure adaptive optimization method, and relates to the technical field of synchronizer structure optimization, and the method comprises the steps: building an integrated simulation model; executing gear shifting clamping stagnation scene collection under high load for the target synchronizer; inputting the plurality of high-load test scenes into the integrated simulation model to carry out a gear shifting test, and carrying out impact analysis on gear engagement according to a test result; whether the meshing impact resistance index meets a preset impact resistance index or not is judged, and if not, a structure optimization module is activated; and optimizing the multi-element structure design parameters to generate recommended structure design parameters meeting a preset impact resistance index. The technical problem that in the prior art, due to the fact that a synchronizer cannot completely eliminate impact of gear meshing, the clamping stagnation phenomenon occurs in the gear shifting process, and the gear shifting process is unstable can be solved, the actual operation condition under the high load is simulated through integrated simulation, and the stability of the synchronizer in the gear shifting process is improved.

Embodiments of the present disclosure relate to the field of processor hardware architecture, and provide an artificial intelligence chip and a computing system. The artificial intelligence chip comprises a first computing core, a shared memory device corresponding to the first computing core, and a data synchronization device. The first computing core is configured to issue a first data request instruction. The data synchronization device is configured to perform a read operation on first data, a flag detection operation, and a synchronization operation according to the first data request instruction. The first data is stored in a global memory device coupled to the artificial intelligence chip. The synchronization operation comprises sending the first data to the shared memory device. The shared memory device is configured to store the first data sent by the data synchronization device for reading by the first computing core. Embodiments of the present disclosure hardwareize data synchronization and retry, significantly reduce communication delay, and release core computing resources of the artificial intelligence chip.

The application relates to the technical field of wireless Mesh networks, and discloses a synchronization method for a wireless Mesh network, wherein the Mesh network comprises a plurality of Mesh network nodes connected to each other, the synchronization method comprises the following steps: obtaining external relative execution time in a Mesh control message received by a Mesh network node; obtaining internal relative execution time saved by the Mesh network node; and correcting the internal relative execution time in the case that the external relative execution time is less than the internal relative execution time. The synchronization operation of the Mesh network node is realized by using the relative time mode, the Mesh network node is clocked by using an internal crystal oscillator, the device of the Mesh network node does not need to quickly re-synchronize the network clock after being powered off and then powered on, and the accuracy of the synchronization operation of the device of the Mesh network node in the Mesh network can be improved. The application further discloses a synchronization device for a wireless Mesh network and an electronic equipment.

Embodiments of a clock synchronization unit of an all-digital phase-locked loop (ADPLL), a successive approximation register (SAR) time-to-digital converter (TDC) of the ADPLL, and a clock synchronization method in the ADPLL are disclosed. In one embodiment, the clock synchronization unit of the ADPLL includes a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation instead. Other embodiments are also described.