1865results about "Pulse manipulation" patented technology

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

The invention discloses a high-precision delay synchronization system with a phase jitter compensation function. The high-precision delay synchronization system comprises an upper computer, an external trigger module, a time reference module, a master control ZYNQ module, a frequency synthesis and trigger mode selection module, a jitter compensation module, a precise delay circuit and an output signal conditioning circuit. According to the invention, the pulse output with adjustable delay time, amplitude and polarity can be realized, the high-precision delay synchronization of signals is realized, and the stability is higher.

The embodiment of the invention discloses a phase adjustment circuit and method and a memory. The phase adjustment circuit includes: a multi-phase clock signal generator configured to generate an initial multi-phase clock signal, a phase error detector configured to detect a phase error of the initial multi-phase clock signal, and a phase error canceller configured to cancel a phase error of the initial multi-phase clock signal; the phase error detector is connected with the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signals to obtain error signals used for representing phase difference information among the initial multi-phase clock signals; the phase error eliminator is connected with the phase error detector and is configured to detect the error signal to obtain an error elimination code; and the multi-phase clock signal generator is also connected with the phase error eliminator and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention discloses an engine rotating speed signal filtering processing method, device and equipment and a medium, and relates to the technical field of engine rotating speed signal processing, and the method comprises the steps: obtaining a rotating speed signal, and calculating the period of the rotating speed signal, the average time length of a high level in one period, and the period change rate; determining whether a processing position corresponding to the rotating speed signal is a gear normal position or a gear tooth missing position; and filtering interference signals at different processing positions by adopting different filtering strategies. The method is used for solving the problem that in the prior art, the filtering effect of interference signals in engine rotating speed signals is poor, and effective filtering of the interference signals in the engine rotating speed signals is achieved.

Provided are an apparatus and a method for adjusting a skew between data and a clock. The apparatus driven by a supply voltage includes a clock circuit that adjusts a skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop, based on a phase difference between data and a clock. The first loop operation is performed until there is no phase difference between the data and the clock, and the second loop operation is performed until a first slope representing a change in delay of the data with respect to the levels of the power voltage and a second slope representing a change in delay of the clock become identical to each other.

The embodiment of the invention provides an excitation signal generation method and system and a digital eddy current sensor, and the method comprises the steps: outputting a square wave signal through a pulse width modulation assembly of a microcontroller unit, and enabling the frequency and resolution of the square wave signal to be adaptive to eddy current probes with different inductance values; inputting the square wave signal into a low-pass filter for filtering, and setting the cut-off frequency of the low-pass filter, the suppression times of higher harmonics and the attenuation slope so as to output a sine wave signal with a target total harmonic distortion range; the amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty ratio and the passband gain of a low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is subjected to self-adaptive adjustment and correction and is output; and taking the sine wave signal as an excitation source of an eddy current probe, and driving the eddy current probe to carry out nondestructive testing. According to the invention, the excitation signal which gives consideration to high-frequency signal generation, deep harmonic suppression and digital adaptive adjustment can be generated.

Clock calibration adjustments are provided. Some embodiments disclosed herein are related to a device. A device can include a first conductive element configured to receive a first signal at a first functional block. The device can include a second conductive element configured to convey the first signal to a second functional block of the device. The device can include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase-shift. The device can include a first circuit configured to determine the phase-shift between the first signal and the second signal. The device can include a second circuit configured to generate a third signal based on the phase-shift, the first signal, the second signal.

The invention provides a delay chain circuit, a voltage drop detection circuit, a chip and electronic equipment, and belongs to the field of electronic circuits. The delay chain circuit comprises m stages of delay units, each stage of delay unit comprises an output end and n input ends, m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2; at least one input end of the ith-level delay unit is connected with the output end of the (i-1) th-level delay unit, and i is an integer greater than or equal to 2; the sensitivity of each stage of delay unit is adjustable, and each stage of delay unit comprises n delay branches which are connected in parallel; the n delay branches comprise at least one controllable delay branch, and the state of each controllable delay branch comprises an on state or an off state. By adjusting the sensitivity of the delay chain circuit, different load changes can be adapted, and the maximum voltage gain of a chip can be supported when a dynamic frequency reduction technology is used.

The invention relates to a low-noise fast duty cycle detector and a duty cycle detection method thereof. The duty cycle detector includes a current directing network to direct a first current to a second current to charge the first capacitance when the clock is in a first state of an even cycle and to direct the first current to a third current to charge the second capacitance when the clock is in a second state of the even cycle; the first charge sharing switch is used for promoting charge sharing between the first capacitor and the third capacitor when the clock is in the second state; the second charge sharing switch is used for promoting charge sharing between the second capacitor and the fourth capacitor when the clock is in the first state; the first discharge network is used for discharging the first capacitor when the clock is in a first state of an odd number period; and the second discharging network is used for discharging the second capacitor when the clock is in the second state of the odd number period.

A reconfigurable driver in an I / O circuit has a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. A gate of the first transistor receives a data signal. The control signal is an inverted, delayed version of the data signal in a first mode. The control signal turns off the second transistor in a second mode. The control circuit generates the control signal using a version of the data signal when operated in a third mode. The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

Disclosed is a method and standard module for amplifying pulsed power. The key point of the technical solution is as follows: a method for amplifying pulsed power is formed by means of the joint action of a LASER mode of a crystal medium, a carrier multiplication amplification mode of a semiconductor medium, and a plasma breakdown amplification mode of a gas medium. Electric power which is amplified is converted into optical power first, the optical power is amplified again, and the amplified optical power is converted into electric power again by a photoelectric conversion and amplification device. A gas switch is triggered based on a photoconductive switch to generate a timing-synchronized high-power electric pulse. The high-power electric pulse may be directly outputted or distributed in multiple channels to obtain multiple timing-synchronized trigger signals. In combination with pulse charge of a capacitor, multiple timing-synchronized high-power electric pulses are outputted.

A system includes an inverter including: a first galvanic isolator separating a primary voltage area from a secondary voltage area; a second galvanic isolator separating the primary voltage area from the secondary voltage area; a first bias network in the secondary voltage area, and connected to the first galvanic isolator; a second bias network in the secondary voltage area, and connected to the second galvanic isolator; a first amplifier in the secondary voltage area, and connected to the first bias network; a second amplifier in the secondary voltage area, and connected to the second bias network; and an open connection detector in the secondary voltage area, the open connection detector connected to the first amplifier and connected to the second amplifier, wherein the open connection detector includes one or more voltage-to-current converters.

A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

An example integrated circuit disclosed herein includes a first die including first microbumps associated with a source-synchronous data interface of a three-dimensional (3D) die stack, a first one of the first microbumps in circuit with a clock output of the first die, a second one of the first microbumps in circuit with a data output of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. The example integrated circuit also includes a second die including second microbumps associated with the source-synchronous data interface of the 3D die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.

According to some embodiments, a method includes connecting a first cluster controller of a first battery cluster to a serial communication bus, connecting a second cluster controller of a second battery cluster to the serial communication bus, sending synchronization data to the first cluster controller and the second cluster controller over the serial communication bus, controlling a first bridge of the first battery cluster to connect a first battery terminal of the first battery cluster to an output terminal based on the synchronization data and a first rank assigned to the first battery cluster to generate a first component of a waveform, and controlling a second bridge of the second cluster to connect a second battery terminal of the second battery cluster to the output terminal based on the synchronization data and a second rank assigned to the second battery cluster to generate a second component of the waveform.

Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.

The invention provides a counter, a phase-locked loop, an automatic frequency control system and a control method, and the counter comprises a sampling window generation module which generates a sampling window signal according to a reference clock signal; the counting module is used for counting the number of cycles of the local oscillator clock signal according to the sampling window signal to obtain an initial count value; the edge detector is used for detecting clock edges of the reference clock signal and the local oscillator clock signal and obtaining an addition and subtraction indication signal according to detected edge information; and the counter calibrates the initial count value according to the addition and subtraction indication signal to obtain a counting result. According to the scheme of the invention, an additional edge detection mechanism is added in the counter, and the counting result of the counting module is calibrated, so that the counting precision of the counter is improved, and the accuracy of a frequency control result can be ensured.

The embodiment of the invention provides a clock generation circuit and a memory, an ith clock generation sub-circuit is used for carrying out sampling processing and latching processing on an ith register input signal according to an inverted clock signal to generate an ith register signal; performing first logic processing on the ith register signal and the delay clock signal to generate an ith target clock signal; the jth clock generation sub-circuit is used for sampling and latching a (j-1) th register signal according to a preset clock signal to generate a jth register signal; and performing second logic processing on the jth register signal and the delayed clock signal to generate a jth target clock signal.

A reference noise cancellation device for a transient electromagnetic field is provided. The device includes a transmitter, a transmitting loop, a reference coil, a signal coil and a receiver. The transmitter generates a measurement timing sequence to trigger the receiver to synchronously record the induction signal in the signal coil and the electromagnetic noise in the reference coil. A bipolar current waveform is generated and is injected into the transmitting loop through the first connecting line. The signal coil receives an induced magnetic field of an underground conductor and surrounding magnetic field noise. The reference coil receives surrounding electromagnetic noise. The receiver receives and records the induced magnetic field and surrounding electromagnetic noise of the underground conductor in the signal coil and the surrounding electromagnetic noise in the reference coil.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

According to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. The first and second switching elements being configured to switch between states based on a first clock signal.

Some embodiments include a voltage regulator including a clock node to receive an input clock signal, and first and second power switching blocks coupled to the clock node. The first power switching block includes a first clock generator and first switched capacitor circuitry. The first clock generator includes clock output nodes to provide first clock signals based on the input clock signal. The first switched capacitor circuitry includes input nodes to receive first control signals generated based on the first clock signals. The second power switching block includes a second clock generator and second switched capacitor circuitry. The second clock generator includes clock output nodes to provide second clock signals based on the input clock signal. The second switched capacitor circuitry includes input nodes to receive second control signals generated based on the second clock signals.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

The invention discloses a multi-channel output pulse synchronization device with adjustable delay time, which relates to the field of power systems. The invention comprises an FPGA, an SMA connector, a host computer, a serial communication terminal, and an output channel. The FPGA serves as a central controller, and a pulse trigger input from the SMA connector terminal is given to the FPGA, and the output of the FPGA is given to the output channel. The FPGA communicates with the host computer via the serial port to set the delay data in each channel register. When the FPGA receives an input pulse signal, it reads the delay data stored in the register according to the setting of the program, and outputs the pulse to the PIN pin of each output channel. The multi-channel output pulse synchronization device with adjustable delay time of the invention has an adjustable minimum accuracy of 52ps, and each channel can independently adjust the output delay time, and has strong controllability and adaptability.