1021results about "Pulse manipulation" patented technology

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The embodiment of the invention provides an excitation signal generation method and system and a digital eddy current sensor, and the method comprises the steps: outputting a square wave signal through a pulse width modulation assembly of a microcontroller unit, and enabling the frequency and resolution of the square wave signal to be adaptive to eddy current probes with different inductance values; inputting the square wave signal into a low-pass filter for filtering, and setting the cut-off frequency of the low-pass filter, the suppression times of higher harmonics and the attenuation slope so as to output a sine wave signal with a target total harmonic distortion range; the amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty ratio and the passband gain of a low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is subjected to self-adaptive adjustment and correction and is output; and taking the sine wave signal as an excitation source of an eddy current probe, and driving the eddy current probe to carry out nondestructive testing. According to the invention, the excitation signal which gives consideration to high-frequency signal generation, deep harmonic suppression and digital adaptive adjustment can be generated.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

The technology described herein is directed towards a design and implementation of a subarray of unit cells for an active reconfigurable intelligent surface that is power efficient. The reconfigurable intelligent surface design integrates a power amplifier with subarrays of unit cells to amplify the reflected signal, resulting in an active reconfigurable intelligent surface with relatively low power consumption. For example, rather than equipping each unit cell with its own power amplifier, a power amplifier is shared by a m×n (e.g., 3×3) subarray of unit cells, which can be arranged as a module of a larger reconfigurable intelligent surface. Further, the design provides a device for receiving and reflecting the electromagnetic signal in the same polarization by coupling the RF energy, processing, amplifying, and then introducing a delay module to not create unwanted harmonics and amplifying the signal without breaking the signal link.

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

The invention discloses a multi-channel high-precision time sequence pulse transmitting system, and the system comprises a control panel which comprises a command receiving control unit and a time sequence generation unit; the command receiving control unit is configured to receive a control command and analyze the control command into pulse basic information; the time sequence generation unit is configured to receive the pulse basic information, generate a coarse delay pulse signal according to the pulse basic information, and generate a driving signal; the daughter board comprises a pulse precise delay unit and an optical port output unit; the pulse fine delay unit is configured to receive the driving signal, perform fine delay adjustment on the coarse delay pulse signal and generate a time pulse sequence; the optical port output unit is configured to receive the time pulse sequence and convert the time pulse sequence into an optical signal. The delay precision of the system can be effectively improved.

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

The invention discloses an anti-interference circuit and method for capacitance detection, and the circuit comprises a to-be-measured unit which is provided with a to-be-measured capacitor, a reference voltage and a common-mode voltage, the first end of the to-be-measured capacitor is selectively connected with the reference voltage and the common-mode voltage, and the second end of the to-be-measured capacitor is connected with a ground potential; the quantization unit is connected with the to-be-measured unit and the integration unit and is used for quantizing an integration capacitor in the integration unit; the integration unit comprises an integrator and an integration capacitor, and the input end of the integration unit is connected with the unit to be measured; the counting unit is connected with the output end of the integration unit; wherein the integrating capacitor comprises a first integrating capacitor and a second integrating capacitor, the first integrating capacitor and the second integrating capacitor are connected in parallel, and the quantization unit quantizes the first integrating capacitor and the second integrating capacitor respectively.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

An isolated gate drive circuit and a driver, the isolated gate drive circuit includes signal restoration module, modulation module with first terminal and second terminal, high-pass filter module, and falling edge monitoring module; first pulse signal output from the first and second terminals are rail-to-rail differential pulse signals; When the isolated gate drive circuit restores the pulse width modulation signal, the isolated gate drive circuit monitors the first pulse signals output from the first and second terminals of the modulation module. When the pulse signal in the first pulse signal output from the first terminal or the second terminal of the modulation module is in a falling edge state, the falling edge monitoring module outputs a third pulse signal to the signal restoration module, the signal restoration module can quickly output the restored the pulse width modulation signal, improving the reliability of the isolated gate drive circuit.

Phase interpolators are provided, the phase interpolators including: a first phase interpolator having a first output that outputs a first interpolated clock signal based on quadrature clock signals and a first phase interpolator control signal; a second phase interpolator having a second output that outputs a second interpolated clock signal based on the quadrature clock signals and a second phase interpolator control signal that is shifted from the first phase interpolator control signal by half of an integral nonlinearity (INL) period of the first phase interpolator; and a phase combiner that outputs a third interpolated clock signal based on the first interpolated clock signal and the second interpolated clock signal. In some of these embodiments, the phase interpolators further comprise a first amplitude limiter that receives the first interpolated clock signal and outputs a first amplitude-limited interpolated clock signal that is provided to the phase combiner.

Methods, systems, and devices for devices and techniques to modify a clock signal are described. A memory system may include a delay adjustment circuit coupled with a clock signal path to compensate for changes in the delay of a clock signal due to fluctuations in a supply voltage. The delay adjustment circuit may include a current mirror, a first compensation component coupled with the clock signal path, and a second compensation component coupled with the clock signal path. The current mirror may be configured to output, based on the supply voltage, a first control signal to the first compensation component and a second control signal to the second compensation component. The compensation components may be configured to modify the clock signal along the clock signal path based on the received control signals.

A memory device is provided which comprises a first signal pin configured to receive a data clock; a second signal pin configured to transmit a read clock; and a data clock circuit receiving the data clock and configured to perform first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock in response to the first duty cycle monitoring; perform second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock in response to the second duty cycle monitoring; calculate an offset of the read clock in response to the timing-adjusted data clock, the first result and the second result, and correct a duty error of the read clock using a read clock offset code derived in relation to the offset of the read clock.

The embodiment of the invention provides a clock control circuit, a memory and a clock control method, and the clock control circuit comprises a delay adjustment circuit which is configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, and when the memory is in a duty ratio adjustment training mode, adjusting the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal according to the judgment result signal, or adjusting the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal, outputting a first target clock signal, and outputting a second target clock signal. A second target clock signal, a third target clock signal and a fourth target clock signal; the judgment circuit is electrically connected with the delay adjustment circuit, and is configured to record the self-refreshing mode exit moment of the memory and the phase sequence of the first phase clock signal and the third phase clock signal, and compare the phase sequence with the last self-refreshing mode exit moment and the phase sequence of the first phase clock signal and the third phase clock signal; and outputting a judgment result signal according to whether the two phase sequences are consistent or not. The embodiment of the invention is at least beneficial to improving the phase difference among the four-phase clock signals.

A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.

The invention provides a semiconductor device, a memory system and an operating method thereof. The semiconductor device includes: a delay-locked loop (DLL) configured to output a first correction value corresponding to a single period of a clock; and a duty cycle correction circuit including a frequency divider configured to divide the clock into half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty cycle of 5: 5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

Various techniques are described for correcting distortion in an analog input signal after digitization in a receiver signal chain. The techniques include a system that stores concatenated distortion correction terms, allowing for efficient data handling and processing. The techniques further include a system that has a smaller number of replica memories compared to primary memories, which store operational data. The replica memories are updated with new data and may be swapped with primary memories to update them without interrupting system operations. The techniques further include a dither system that uses two memories to store and process the dithered signals, which are then combined to produce a noise-corrected digital output. The techniques further include a system to correct distortions in analog input signals processed through multiple parallel paths.

A driving system for a lighting apparatus comprising a plurality of light sources, the driving system comprising a controller configured to provide a first digital control signal to the lighting apparatus, the first digital control signal having a first duty cycle and a first frequency, and control the first frequency of the first digital control signal.

A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.

Embodiments relate to a system and method of generating a duty-cycle matched differential clock divider circuit. The duty-cycle matched differential clock divider circuit may include a primary latch, differential latch, and a first inverter. The primary latch may be coupled to receive a feedback signal and complementary input clock signals. The primary latch may be configured to produce a first output signal. The differential latch may be coupled to receive the first output signal produced by the primary latch and the complementary input clock signals. The differential latch may be configured to produce a second output signal and a third output signal. The first inverter may be coupled to receive the second output signal produced by the differential latch, and may be configured to produce the feedback signal applied to an input of the primary latch.

A switching converter controller includes: mode control logic; and a pulse-frequency modulation (PFM) timer circuit coupled to the mode control logic. The PFM timer circuit includes: a first terminal; a second terminal; a digital-to-analog converter (DAC); a current source; a capacitor; and a comparator. A first terminal of the DAC is coupled to the first terminal of the PFM timer circuit. The current source has a first terminal, a second terminal, and a third terminal. The second terminal of the current source is coupled to a second terminal of the DAC. A first terminal of the capacitor is coupled to the first terminal of the current source. The comparator has first, second, and third terminals. The first terminal of the comparator is coupled to the first terminal of the capacitor. The third terminal of the comparator is coupled to the second terminal of the PFM timer circuit.

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

The application discloses a multi-path fan-out circuit and a clock driver, and relates to the field of clock drivers, which comprises an amplification circuit, a bias circuit and a plurality of LVPECL output circuits, the bias circuit is connected with the amplification circuit and each LVPECL output circuit respectively, and is used for providing current bias and switching signals. The LVPECL output circuit comprises two mirror-symmetrical conversion circuits. The amplification circuit is connected with the LVPECL output circuit, and is used for amplifying a differential input signal and outputting a first level standard signal and a second level standard signal. The LVPECL output circuit is used for converting the first level standard signal and the second level standard signal into a first output signal and a second output signal. The application can realize the function of converting a group of differential input signals into multi-path high-speed data output, and due to the mirror-symmetrical arrangement of the two conversion circuits, the signal output by each conversion circuit can realize low skew when serving as a clock signal.

To provide a superconducting circuit capable of reducing crosstalk.SOLUTION: A superconducting circuit (1) includes: a ground plane (30) that has a superconducting member; multiple superconducting parts (10) surrounded at intervals from the ground plane by non-conducting parts (40), the multiple superconducting parts each having four coupling ports that interact with the other superconducting parts; a superconducting quantum interference device (12) that sets the resonance frequency of the first superconducting part included in the multiple superconducting parts; and a three-dimensional wiring that forms a superconducting loop surrounding the superconducting quantum interference device with the ground plane. The superconducting quantum interference device is placed in a position where a magnetic field is applied by a current from the bias line (13G) to the first superconducting part in the region within the superconducting loop.SELECTED DRAWING: Figure 3

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

In one example, an RF oscillator system includes a laser source configured to emit laser light, a housing, a crystalline microresonator disposed within the housing, and a photonic integrated circuit disposed within the housing, the photonic integrated circuit including an optical waveguide network and configured to generate a clock signal based on the laser light. The RF oscillator system may further include at least one photonic wirebond configured to couple the laser light between the optical waveguide network and the crystalline microresonator via evanescent coupling; laser control circuitry disposed within the housing and configured to lock a frequency of the laser light to a resonance of the microresonator to generate the clock signal; and a direct digital synthesizer disposed within the housing and configured to produce a tunable oscillator signal based on the clock signal.