94results about "Pulse manipulation" patented technology

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

A reference signal calibration and distribution system (10) is configured to time calibrate and distribute high frequency reference signals on an electronic circuit A low frequency synchronization (synch) signal is derived from the high frequency reference signal, and edge- synchronized to it. Both the low frequency synch signal and the high frequency reference signal are distributed to a plurality of termination points, the latter through a network (22) of adjustable-delay buffers. The former is distributed using a central buffer (16) and passive distribution network, with series RC terminations (38), where C is high ohmic at the synchronization frequency. The high frequency reference signal is sampled by the low frequency synch signal at a subset of the termination points. Based on the sampled voltages, the delays of buffers in the high frequency reference signal distribution network (22) are adjusted, to make sampled voltages near the target, close to mid-range.

A clock generation circuit performs a delay-locked operation on a reference clock signal. The clock generation circuit is configured to perform the delay-locked operation by comparing the phases of a division reference clock signal and a feedback clock signal. After the delay-locked operation is completed, the clock generation circuit is configured to selectively invert the phase of the division reference clock signal by comparing the phases of the division reference clock signal and the delay feedback clock signal.

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

This disclosure relates to glitch suppression for FSK demodulation. According to an embodiment, a glitch suppression circuit includes a first-stage averaging circuit with programmable length, a second-stage averaging circuit, and a hysteresis comparator. The first stage uses a FIFO buffer to implement recursive shifting and averaging to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses a programmable threshold set based on the peak signal value to generate a clean output signal. This circuit removes glitches from the input signal of the frequency shift keying (FSK) demodulator while maintaining signal integrity at high bit rates. The programmable parameters allow for optimization based on desired glitch characteristics and system requirements.

The application discloses a high-speed differential clock switching circuit without burr and with low delay, and belongs to the technical field of integrated circuit design, which comprises a first synchronization module, a second synchronization module, a first level trigger module, a second level trigger module, a first logic gate, a second logic gate and an output module. The application adjusts the logic gate from the front stage to the rear stage of the flip-flop, and adopts the level trigger module to replace the edge trigger, so that the path of the control signal is optimized. Compared with the traditional clock switching circuit without burr, the application can reduce the delay consumed in the switching process from 2 clock cycles to 1 clock cycle when the input is the differential clock, greatly improves the precision of phase adjustment and the system response speed, meanwhile, the advantages of the burr-free switching are retained, and the circuit can work stably at high speed.

A memory device correcting a data strobe signal when performing a write operation includes a correction circuit configured to receive the data strobe signal and to generate a reference delay for the received data strobe signal, and a main circuit configured to correct the data strobe signal based on the reference delay generated by the correction circuit. The correction circuit includes a delay cell configured to generate a reference delay for the data strobe signal received by the main circuit and to store the generated reference delay, when a data signal is input to the main circuit, a first counter configured to adjust the reference delay, and a second counter configured to determine a delay of the data strobe signal received by the main circuit, when a write operation is performed.

The present invention provides an apparatus and method for generating different time / delay types using only a single capacitor. [Solution] The system 100 includes a first current source 102 that provides a first bias current and a second current source 104 that provides a second bias current, wherein the first bias current is greater than the second bias current. The system also includes a current switch, which receives the first and second bias currents at its two input terminals 103 and 105 and provides an output current at its output terminal 107. The output current is one of the first and second bias currents selected by the current switch control signal. The system further includes a capacitor 108 coupled between the output terminal and the ground terminal, which is charged by the output current and provides an output voltage at the output terminal.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

The application discloses a multi-phase clock generation circuit, comprising: a main clock generator generating a first-stage source clock; a first frequency divider receiving the first-stage source clock and generating first-stage phase information; a second frequency divider receiving the first-stage phase information and outputting second-stage phase information; a plurality of sub-clock generation modules, each of which comprises a first-stage sampling clock generation unit, a first first-stage sampling clock generation unit being connected with the first frequency divider, each first-stage sampling clock generation unit receiving first-stage phase information output by a previous first-stage sampling clock generation unit and the first-stage source clock respectively and outputting phase-shifted first-stage phase information, the first-stage sampling clock generation unit generating a first-stage sampling clock and a second-stage source clock; and a plurality of second-stage sampling clock generation units. The application adopts a distributed and modular clock generation method, the layout is simplified, and the phase error is smaller.

The present disclosure provides a power generation system comprising a plurality of power amplifier modules and a controller configured to determine delay values for actuating the plurality of power amplifier modules. The controller implements delay values, measures performance metrics from an output voltage waveform including rise time, fall time, overshoot, and undershoot, analyzes the measured performance metrics, and adjusts the delay values based on the analyzed performance metrics. A controller for a power generation system having a plurality of power amplifier modules comprises a processor and memory storing instructions that cause the controller to determine delay values by implementing delay values, measuring performance metrics from an output voltage waveform including rise time, fall time, overshoot, and undershoot, analyzing the measured performance metrics, and iteratively adjusting the delay values.

Phase-locked loop circuitry is provided that includes a time-to-digital converter, a first frequency divider circuit coupled to an output of the time-to-digital converter, and a second frequency divider circuit coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator with a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit. The phase interpolator can be calibrated using the time-to-digital converter.

A delay buffer unit and an operating method thereof, a computing device and an operating method thereof. The delay buffer unit includes a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit, an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit; an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit; the delay adjustment sub-unit is connected between a first terminal of the first-stage inverter and a first operating voltage terminal, and the delay adjustment sub-unit includes a memristor and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal.

A device may include: a reference divider circuit for dividing a reference clock; a phase-frequency detector circuit for detecting a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock; a loop filter circuit for filtering the detector output; a voltage-controlled oscillator (VCO) control output pin coupled to the loop filter output; a VCO clock divider control output pin for selecting the divisor of an external clock divider circuit; a divider VCO clock input pin coupled to the output of the external clock divider circuit; a pulse width modulation (PWM) circuit having a PWM clock input coupled to the divider VCO clock input pin; a period register for storing a period value; a duty cycle register for storing a duty cycle value; and a PWM output based on the period value and the duty cycle value.

The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

A semiconductor integrated circuit device includes: a zero-crossing detection unit configured to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a comparison signal; a logic unit configured to count a period of the comparison signal and estimate a zero-cross of the AC signal using the count value, so as to generate a zero-crossing detection signal; and a monitoring unit configured to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit, where a first chip, in which the monitoring unit is integrated, is cut out in a rectangular shape having a substantially equal ratio between a short side and a long side in a plan view.

This invention relates to a circuit for suppressing glitches on digital signals. The circuit includes a delay chain, an AND logic module, an OR logic module, and a latch. Input signals are connected to the input terminals of the delay chain, the AND logic module, and the OR logic module, respectively. Simultaneously, the output terminal of the delay chain is connected to the input terminals of the AND logic module and the OR logic module. The output terminal of the AND logic module is connected to one input terminal of the latch, and the output terminal of the OR logic module is connected to the other input terminal of the latch. The output terminal of the latch outputs a signal. This invention is based on combinational logic gates and latches, and can filter out high-level and low-level glitches on digital signals without a clock. It is particularly suitable for low-power scenarios where a clock is not required.

The application provides an asynchronous clock generation device and an analog-to-digital converter, and belongs to the technical field of electronic circuits.The device comprises a signal generation module, a current source module, an asynchronous clock biasing module, a hysteresis clock generation module and a control module; the signal generation module is used for generating a handshake signal according to an external signal, a target clock signal sent by the hysteresis clock generation module and a control instruction sent by the control module, and sending the handshake signal to the current source module; the current source module is used for generating a target electric signal meeting the control instruction based on the handshake signal, and sending the target electric signal to the asynchronous clock biasing module; the asynchronous clock biasing module is used for adjusting an output voltage according to the target electric signal, and the hysteresis clock generation module is used for generating the target clock signal based on the adjusted output voltage, and sending the target clock signal to the signal generation module. The application can realize linear adjustment of delay and improve the adjustment precision.

To provide a differential interface circuit capable of receiving a multiple-value PAM signal accurately.SOLUTION: A first stage 420_1 of a differential interface circuit 400A includes a first transistor MN11, a second transistor MN12, a third transistor MN13, and a fourth transistor MN14. Gates of the first transistor MN11 and the second transistor MN12 are connected to input terminals INP, INN. The third transistor MN13 and the fourth transistor MN14 are connected in parallel to the first transistor MN11 and the second transistor MN12. A gate of the third transistor MN13 is connected to a drain of the second transistor MN12, and a gate of the fourth transistor MN14 is connected to a drain of the first transistor MN11.SELECTED DRAWING: Figure 3

A system comprising: a processing circuit; and a memory storing instructions, which, based on being executed by the processing circuit, cause the processing circuit to perform: determining a first value of a signal at a first clock edge of a clock signal; determining a second value of the signal at a second clock edge of the clock signal; generating an output value based on a computation of at least the first value and the second value; determining a status of the clock signal based on a comparison between the output value and a reference value; and adjusting the clock signal based on the status.

The purpose of this invention is to provide a method for implementing pulse interference detection and elimination circuitry, comprising the following steps: S1: Data from the analog-to-digital converter is input to a data buffer circuit; S2: The data from the analog-to-digital converter is simultaneously input to a numerical judgment and statistics circuit; S3: The numerical judgment and statistics circuit detects and statistically analyzes the interference in the data from the analog-to-digital converter; S4: The data buffer circuit outputs delayed data to a data clearing selection circuit; S5: The data clearing selection circuit outputs the data. This invention can achieve pulse interference detection and elimination. Pulse interference typically exhibits a much higher concentration in the time domain than background noise, and the amplitude of sample data affected by pulse interference is significantly higher than at other locations. This method can be implemented without delay and only triggers processing when interference is present.

Methods, systems, and devices for four-phase clocking techniques, and in particular for a hybrid clock cycle correction and quadrature error correction (DCC-QEC) circuit, are described. The DCC-QEC circuit comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibrating without receiving a reference signal.The DCC-QEC circuit further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuits comprising a pair of phase dividers configured to convert the two-phase clock signals into four-phase clock signals, and an offset matcher configured to match clock offsets associated with a subset of the four-phase clock signals based on QEC matching codes and in an open-loop manner, wherein data from multiple lanes of parallel data channels based on the offset-matched four-phase clock signals are serialized and sent to outside a device comprising the DCC-QEC circuit.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

The application provides a TDC circuit, a time interval measurement circuit and an electronic device, comprising: a first ring delay chain, a second ring delay chain, a first timer, and a second timer; the first ring delay chain is configured to cyclically transmit the timing start signal; the second ring delay chain is configured to cyclically transmit the timing end signal; the first counter is configured to count the number of cycles of the cyclic transmission of the timing start signal during the cyclic transmission of the timing start signal, and obtain first count information; the second counter is configured to count the number of cycles of the cyclic transmission of the timing start signal during the cyclic transmission of the timing start signal, and obtain second count information; and a processing module is configured to obtain the first count information and the second count information, and determine current time interval information based on the first count information and the second count information.

The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

According to an embodiment, a glitch rejection circuit includes a first stage averaging circuit with programmable length, a second stage averaging circuit, and a hysteresis comparator. The first stage implements a recursive moving sum average using a FIFO buffer to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses programmable thresholds set based on peak signal values to generate a clean output signal. The circuit removes glitches from frequency-shift keying (FSK) demodulator input signals while maintaining signal integrity at high bitrates. The programmable parameters allow optimization based on expected glitch characteristics and system requirements.

The application discloses a clock oscillation circuit, a key detection system and a chip. The clock oscillation circuit comprises a trigger unit, a clock oscillator and a counter. The trigger unit is used for generating an enable signal based on a key state signal. The clock oscillator is connected with the trigger unit and is used for generating a clock signal based on the enable signal. The counter is connected with the clock signal generation unit and is used for receiving the clock signal and generating a count value based on the clock signal. A control unit is connected between the trigger unit and the counter. The control unit is used for adjusting the level of the enable signal based on the count value and controlling the clock oscillator to continuously work or shut down. The clock oscillator is started by detecting the edge jump of the key state signal, and the clock oscillator is automatically stopped. The circuit structure is simple, and the power consumption of the circuit is greatly reduced.

To provide a semiconductor device and its manufacturing method capable of designing the intended delay with high precision using fewer steps. The manufacturing method of the semiconductor device disclosed herein arranges multiple circuits on a plane and connects wiring to each, comprising: a placement step of arranging a digital circuit that operates based on timing signals and a delay circuit configured with multiple delay paths having different input / output delay amounts, where one of the multiple delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay adjustment step of selecting one of the multiple delay paths by connecting a predetermined voltage as the selection signal, and selecting the delay amount so that the input / output timing of the digital circuit meets predetermined conditions.