701results about "Pulse manipulation" patented technology

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

An isolated gate drive circuit and a driver, the isolated gate drive circuit includes signal restoration module, modulation module with first terminal and second terminal, high-pass filter module, and falling edge monitoring module; first pulse signal output from the first and second terminals are rail-to-rail differential pulse signals; When the isolated gate drive circuit restores the pulse width modulation signal, the isolated gate drive circuit monitors the first pulse signals output from the first and second terminals of the modulation module. When the pulse signal in the first pulse signal output from the first terminal or the second terminal of the modulation module is in a falling edge state, the falling edge monitoring module outputs a third pulse signal to the signal restoration module, the signal restoration module can quickly output the restored the pulse width modulation signal, improving the reliability of the isolated gate drive circuit.

Phase interpolators are provided, the phase interpolators including: a first phase interpolator having a first output that outputs a first interpolated clock signal based on quadrature clock signals and a first phase interpolator control signal; a second phase interpolator having a second output that outputs a second interpolated clock signal based on the quadrature clock signals and a second phase interpolator control signal that is shifted from the first phase interpolator control signal by half of an integral nonlinearity (INL) period of the first phase interpolator; and a phase combiner that outputs a third interpolated clock signal based on the first interpolated clock signal and the second interpolated clock signal. In some of these embodiments, the phase interpolators further comprise a first amplitude limiter that receives the first interpolated clock signal and outputs a first amplitude-limited interpolated clock signal that is provided to the phase combiner.

Methods, systems, and devices for devices and techniques to modify a clock signal are described. A memory system may include a delay adjustment circuit coupled with a clock signal path to compensate for changes in the delay of a clock signal due to fluctuations in a supply voltage. The delay adjustment circuit may include a current mirror, a first compensation component coupled with the clock signal path, and a second compensation component coupled with the clock signal path. The current mirror may be configured to output, based on the supply voltage, a first control signal to the first compensation component and a second control signal to the second compensation component. The compensation components may be configured to modify the clock signal along the clock signal path based on the received control signals.

The embodiment of the invention provides a clock control circuit, a memory and a clock control method, and the clock control circuit comprises a delay adjustment circuit which is configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal and a judgment result signal, and when the memory is in a duty ratio adjustment training mode, adjusting the delay of the second phase clock signal, the third phase clock signal and the fourth phase clock signal according to the judgment result signal, or adjusting the delay of the first phase clock signal, the second phase clock signal and the fourth phase clock signal, outputting a first target clock signal, and outputting a second target clock signal. A second target clock signal, a third target clock signal and a fourth target clock signal; the judgment circuit is electrically connected with the delay adjustment circuit, and is configured to record the self-refreshing mode exit moment of the memory and the phase sequence of the first phase clock signal and the third phase clock signal, and compare the phase sequence with the last self-refreshing mode exit moment and the phase sequence of the first phase clock signal and the third phase clock signal; and outputting a judgment result signal according to whether the two phase sequences are consistent or not. The embodiment of the invention is at least beneficial to improving the phase difference among the four-phase clock signals.

The invention provides a semiconductor device, a memory system and an operating method thereof. The semiconductor device includes: a delay-locked loop (DLL) configured to output a first correction value corresponding to a single period of a clock; and a duty cycle correction circuit including a frequency divider configured to divide the clock into half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty cycle of 5: 5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

Various techniques are described for correcting distortion in an analog input signal after digitization in a receiver signal chain. The techniques include a system that stores concatenated distortion correction terms, allowing for efficient data handling and processing. The techniques further include a system that has a smaller number of replica memories compared to primary memories, which store operational data. The replica memories are updated with new data and may be swapped with primary memories to update them without interrupting system operations. The techniques further include a dither system that uses two memories to store and process the dithered signals, which are then combined to produce a noise-corrected digital output. The techniques further include a system to correct distortions in analog input signals processed through multiple parallel paths.

A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

The application discloses a multi-path fan-out circuit and a clock driver, and relates to the field of clock drivers, which comprises an amplification circuit, a bias circuit and a plurality of LVPECL output circuits, the bias circuit is connected with the amplification circuit and each LVPECL output circuit respectively, and is used for providing current bias and switching signals. The LVPECL output circuit comprises two mirror-symmetrical conversion circuits. The amplification circuit is connected with the LVPECL output circuit, and is used for amplifying a differential input signal and outputting a first level standard signal and a second level standard signal. The LVPECL output circuit is used for converting the first level standard signal and the second level standard signal into a first output signal and a second output signal. The application can realize the function of converting a group of differential input signals into multi-path high-speed data output, and due to the mirror-symmetrical arrangement of the two conversion circuits, the signal output by each conversion circuit can realize low skew when serving as a clock signal.

To provide a superconducting circuit capable of reducing crosstalk.SOLUTION: A superconducting circuit (1) includes: a ground plane (30) that has a superconducting member; multiple superconducting parts (10) surrounded at intervals from the ground plane by non-conducting parts (40), the multiple superconducting parts each having four coupling ports that interact with the other superconducting parts; a superconducting quantum interference device (12) that sets the resonance frequency of the first superconducting part included in the multiple superconducting parts; and a three-dimensional wiring that forms a superconducting loop surrounding the superconducting quantum interference device with the ground plane. The superconducting quantum interference device is placed in a position where a magnetic field is applied by a current from the bias line (13G) to the first superconducting part in the region within the superconducting loop.SELECTED DRAWING: Figure 3

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

In one example, an RF oscillator system includes a laser source configured to emit laser light, a housing, a crystalline microresonator disposed within the housing, and a photonic integrated circuit disposed within the housing, the photonic integrated circuit including an optical waveguide network and configured to generate a clock signal based on the laser light. The RF oscillator system may further include at least one photonic wirebond configured to couple the laser light between the optical waveguide network and the crystalline microresonator via evanescent coupling; laser control circuitry disposed within the housing and configured to lock a frequency of the laser light to a resonance of the microresonator to generate the clock signal; and a direct digital synthesizer disposed within the housing and configured to produce a tunable oscillator signal based on the clock signal.

A clock tree 900 comprises a first clock buffer 906 electrically connected to a second clock buffer 910. The first clock buffer comprises a first transistor 972, a second transistor 974, a first resis

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

This application is directed to providing a configurable and scalable load that emulates a dynamic current profile of an electronic system. The load is provided by an electronic device including a control signal interface providing control data, a clock signal interface providing an operating clock signal, a load controller, and a set of load modules. The control data indicate one or more dynamic current characteristics of the load, and are applied by the load controller to generate a plurality of load control signals that are synchronized according to a temporal pattern. Each load module is controlled by a respective load control signal to generate an output signal based on the operating clock signal. The load controller controls the set of load modules to generate respective output signals according to the temporal pattern, allowing the set of load modules to operate jointly to emulate the dynamic current characteristics of the load.

A clock signal correction device includes a first clock signal generator configured to generate an internal clock signal in a first mode, a divider configured to generate a plurality of first clock signals having different phases based on the internal clock signal, a calibration circuit configured to generate a first skew code corresponding to a skew between a first clock signal and a second clock signal of the plurality of first clock signals and a second skew code corresponding to a skew between a third clock signal and a fourth clock signal of the plurality of first clock signals, and a skew adjustment circuit configured to adjust the phases of a plurality of second clock signals having different phases generated using a clock signal received from an external source based on the first skew code and the second skew code in a second mode different from the first mode.

A reference signal calibration and distribution system (10) is configured to time calibrate and distribute high frequency reference signals on an electronic circuit A low frequency synchronization (synch) signal is derived from the high frequency reference signal, and edge- synchronized to it. Both the low frequency synch signal and the high frequency reference signal are distributed to a plurality of termination points, the latter through a network (22) of adjustable-delay buffers. The former is distributed using a central buffer (16) and passive distribution network, with series RC terminations (38), where C is high ohmic at the synchronization frequency. The high frequency reference signal is sampled by the low frequency synch signal at a subset of the termination points. Based on the sampled voltages, the delays of buffers in the high frequency reference signal distribution network (22) are adjusted, to make sampled voltages near the target, close to mid-range.

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

Embodiments of the present application provide a clock signal calibration circuit, method and chip, comprising: the output end of a first clock delay module is connected with the input end of a second clock delay module through an inverter, the output end of the first clock delay module is connected with the input end of a clock information detection module through a first AND gate, the output end of the second clock delay module is connected with the input end of the clock information detection module through the first AND gate, the first clock delay module is used for receiving and adjusting an original clock signal, and outputs a first clock signal to the inverter and the first AND gate; the second clock delay module is used for receiving and adjusting the first clock signal performing logical NOT through the inverter, and outputs a second clock signal to the first AND gate; the clock information detection module is used for receiving a target clock signal, and determining a first parameter used for calibrating the target clock signal. The problem of low precision and large energy consumption of clock calibration technology is solved, and the effect of improving clock signal calibration precision and reducing energy consumption is achieved.

The present disclosure provides an information transmission method, a memory, a control device and an electronic device, the method comprising: receiving a first target instruction sent externally; outputting first duty cycle data of an internal data clock signal through a first group of data ports based on the first target instruction, and the first duty cycle data lasting in the first group of data ports at least until a first end instruction sent externally is received.

A kind of analog-digital converter is disclosed.The analog-digital converter includes: comparator, is configured to: input signal is compared with reference signal, and output comparison signal indicating corresponding comparison result;Control logic is configured to output control signal for adjusting reference signal based on comparison signal;And reference signal adjusting circuit is configured to adjust reference signal based on control signal.Comparator includes: first preamplifier, is configured to: using first transistor with first size, the difference between input signal and reference signal is amplified;Second preamplifier, is configured to: using second transistor with second size different from first size, the difference between input signal and reference signal is amplified;And latch, is configured to: using at least one of the output of first preamplifier and the output of second preamplifier, comparison signal is generated.First preamplifier and second preamplifier share latch.

Various techniques are described for correcting distortion in an analog input signal after digitization in a receiver signal chain. The techniques include a system that stores concatenated distortion correction terms, allowing for efficient data handling and processing. The techniques further include a system that has a smaller number of replica memories compared to primary memories, which store operational data. The replica memories are updated with new data and may be swapped with primary memories to update them without interrupting system operations. The techniques further include a dither system that uses two memories to store and process the dithered signals, which are then combined to produce a noise-corrected digital output. The techniques further include a system to correct distortions in analog input signals processed through multiple parallel paths.

According to one embodiment, semiconductor integrated circuit includes: first and second pulse generators that generate first and second pulse signals based on a first signal, and third and fourth pulse signal based on a second signal, respectively; first and second inversion buffers that output a third signal based on inputs of the first and third pulse signals, and a fourth signal based on inputs of the second and fourth pulse signal, respectively; wherein, when a logic level of the first or the third pulse signal changes from a first logic level to a second logic level, the first inversion buffer changes a logic level of the third signal, and when a logic level of the second or the fourth pulse signal changes from the first logic level to the second logic level, the second inversion buffer changes a logic level of the fourth signal.