1370results about "Pulse manipulation" patented technology

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention discloses an engine rotating speed signal filtering processing method, device and equipment and a medium, and relates to the technical field of engine rotating speed signal processing, and the method comprises the steps: obtaining a rotating speed signal, and calculating the period of the rotating speed signal, the average time length of a high level in one period, and the period change rate; determining whether a processing position corresponding to the rotating speed signal is a gear normal position or a gear tooth missing position; and filtering interference signals at different processing positions by adopting different filtering strategies. The method is used for solving the problem that in the prior art, the filtering effect of interference signals in engine rotating speed signals is poor, and effective filtering of the interference signals in the engine rotating speed signals is achieved.

The embodiment of the invention provides an excitation signal generation method and system and a digital eddy current sensor, and the method comprises the steps: outputting a square wave signal through a pulse width modulation assembly of a microcontroller unit, and enabling the frequency and resolution of the square wave signal to be adaptive to eddy current probes with different inductance values; inputting the square wave signal into a low-pass filter for filtering, and setting the cut-off frequency of the low-pass filter, the suppression times of higher harmonics and the attenuation slope so as to output a sine wave signal with a target total harmonic distortion range; the amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty ratio and the passband gain of a low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is subjected to self-adaptive adjustment and correction and is output; and taking the sine wave signal as an excitation source of an eddy current probe, and driving the eddy current probe to carry out nondestructive testing. According to the invention, the excitation signal which gives consideration to high-frequency signal generation, deep harmonic suppression and digital adaptive adjustment can be generated.

The invention provides a delay chain circuit, a voltage drop detection circuit, a chip and electronic equipment, and belongs to the field of electronic circuits. The delay chain circuit comprises m stages of delay units, each stage of delay unit comprises an output end and n input ends, m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2; at least one input end of the ith-level delay unit is connected with the output end of the (i-1) th-level delay unit, and i is an integer greater than or equal to 2; the sensitivity of each stage of delay unit is adjustable, and each stage of delay unit comprises n delay branches which are connected in parallel; the n delay branches comprise at least one controllable delay branch, and the state of each controllable delay branch comprises an on state or an off state. By adjusting the sensitivity of the delay chain circuit, different load changes can be adapted, and the maximum voltage gain of a chip can be supported when a dynamic frequency reduction technology is used.

The invention relates to a low-noise fast duty cycle detector and a duty cycle detection method thereof. The duty cycle detector includes a current directing network to direct a first current to a second current to charge the first capacitance when the clock is in a first state of an even cycle and to direct the first current to a third current to charge the second capacitance when the clock is in a second state of the even cycle; the first charge sharing switch is used for promoting charge sharing between the first capacitor and the third capacitor when the clock is in the second state; the second charge sharing switch is used for promoting charge sharing between the second capacitor and the fourth capacitor when the clock is in the first state; the first discharge network is used for discharging the first capacitor when the clock is in a first state of an odd number period; and the second discharging network is used for discharging the second capacitor when the clock is in the second state of the odd number period.

Disclosed is a method and standard module for amplifying pulsed power. The key point of the technical solution is as follows: a method for amplifying pulsed power is formed by means of the joint action of a LASER mode of a crystal medium, a carrier multiplication amplification mode of a semiconductor medium, and a plasma breakdown amplification mode of a gas medium. Electric power which is amplified is converted into optical power first, the optical power is amplified again, and the amplified optical power is converted into electric power again by a photoelectric conversion and amplification device. A gas switch is triggered based on a photoconductive switch to generate a timing-synchronized high-power electric pulse. The high-power electric pulse may be directly outputted or distributed in multiple channels to obtain multiple timing-synchronized trigger signals. In combination with pulse charge of a capacitor, multiple timing-synchronized high-power electric pulses are outputted.

A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

The invention provides a counter, a phase-locked loop, an automatic frequency control system and a control method, and the counter comprises a sampling window generation module which generates a sampling window signal according to a reference clock signal; the counting module is used for counting the number of cycles of the local oscillator clock signal according to the sampling window signal to obtain an initial count value; the edge detector is used for detecting clock edges of the reference clock signal and the local oscillator clock signal and obtaining an addition and subtraction indication signal according to detected edge information; and the counter calibrates the initial count value according to the addition and subtraction indication signal to obtain a counting result. According to the scheme of the invention, an additional edge detection mechanism is added in the counter, and the counting result of the counting module is calibrated, so that the counting precision of the counter is improved, and the accuracy of a frequency control result can be ensured.

The embodiment of the invention provides a clock generation circuit and a memory, an ith clock generation sub-circuit is used for carrying out sampling processing and latching processing on an ith register input signal according to an inverted clock signal to generate an ith register signal; performing first logic processing on the ith register signal and the delay clock signal to generate an ith target clock signal; the jth clock generation sub-circuit is used for sampling and latching a (j-1) th register signal according to a preset clock signal to generate a jth register signal; and performing second logic processing on the jth register signal and the delayed clock signal to generate a jth target clock signal.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

The invention discloses a multi-channel output pulse synchronization device with adjustable delay time, which relates to the field of power systems. The invention comprises an FPGA, an SMA connector, a host computer, a serial communication terminal, and an output channel. The FPGA serves as a central controller, and a pulse trigger input from the SMA connector terminal is given to the FPGA, and the output of the FPGA is given to the output channel. The FPGA communicates with the host computer via the serial port to set the delay data in each channel register. When the FPGA receives an input pulse signal, it reads the delay data stored in the register according to the setting of the program, and outputs the pulse to the PIN pin of each output channel. The multi-channel output pulse synchronization device with adjustable delay time of the invention has an adjustable minimum accuracy of 52ps, and each channel can independently adjust the output delay time, and has strong controllability and adaptability.

The invention relates to a reference voltage optimization method, circuit and device, and the method comprises the steps: carrying out the sampling of data transmitted on at least one data line through changing the phase of a sampling clock, and obtaining a sampling clock phase interval under the condition that the sampling data on the at least one data line are all correct; obtaining an optimized sampling clock phase according to the sampling clock phase interval; sampling data transmitted on each data line in the at least one data line by optimizing a sampling clock phase and changing a sampling voltage to obtain an effective reference voltage interval of each data line; and obtaining an optimized reference voltage of each data line according to the effective reference voltage interval of each data line. According to the invention, the identification accuracy of the signal receiving end on the received signal can be improved, and the anti-interference capability of the signal receiving end on receiving the signal can be improved.

The embodiment of the invention relates to the field of ultrasonic sensors, and discloses a signal transmitting device, module and equipment for ultrasonic fingerprint identification. The signal transmitting device for ultrasonic fingerprint identification comprises a booster circuit, a control circuit, an oscillating circuit and an ultrasonic transducer, the boosting circuit is used for boosting the power supply voltage into a first voltage according to an input boosting clock; the first voltage is the power supply voltage of the control circuit; the control circuit is used for driving the oscillating circuit to generate a second voltage according to an input control signal; the ultrasonic transducer is used for generating an ultrasonic signal according to the second voltage; and the boost circuit is also used for controlling the input of the boost clock according to the edge detection result of the control signal. Therefore, stepped water ripples with light and shade changes in the fingerprint identification process are avoided. And the accuracy of fingerprint identification is improved.

The technology described herein is directed towards a design and implementation of a subarray of unit cells for an active reconfigurable intelligent surface that is power efficient. The reconfigurable intelligent surface design integrates a power amplifier with subarrays of unit cells to amplify the reflected signal, resulting in an active reconfigurable intelligent surface with relatively low power consumption. For example, rather than equipping each unit cell with its own power amplifier, a power amplifier is shared by a m×n (e.g., 3×3) subarray of unit cells, which can be arranged as a module of a larger reconfigurable intelligent surface. Further, the design provides a device for receiving and reflecting the electromagnetic signal in the same polarization by coupling the RF energy, processing, amplifying, and then introducing a delay module to not create unwanted harmonics and amplifying the signal without breaking the signal link.

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

The invention relates to a digital pre-distortion high-precision phase interpolator with a constant input load. The digital pre-distortion high-precision phase interpolator comprises a multi-phase clock generation circuit, an input buffer circuit, two pre-filter circuits, a phase interpolation core circuit, a CML2CMOS circuit and a control code decoder circuit. The two pre-filter circuits are used for converting the two full-swing square wave signals into two sine clocks; and the phase interpolation core circuit is used for carrying out nonlinear interpolation on the two paths of sine clocks according to the two paths of weight control codes by using a constant input load, and outputting a small-swing signal. According to the phase interpolator, the interpolation precision is greatly improved, digital pre-distortion of the interpolation weight can be realized by adjusting the control code decoder, the precision of the phase interpolator is further improved, a high-speed and high-precision output clock is realized, and the phase interpolator is suitable for clock generation modules such as a clock data recovery circuit and a phase-locked loop in a high-speed SerDes system.

The invention discloses a multi-channel high-precision time sequence pulse transmitting system, and the system comprises a control panel which comprises a command receiving control unit and a time sequence generation unit; the command receiving control unit is configured to receive a control command and analyze the control command into pulse basic information; the time sequence generation unit is configured to receive the pulse basic information, generate a coarse delay pulse signal according to the pulse basic information, and generate a driving signal; the daughter board comprises a pulse precise delay unit and an optical port output unit; the pulse fine delay unit is configured to receive the driving signal, perform fine delay adjustment on the coarse delay pulse signal and generate a time pulse sequence; the optical port output unit is configured to receive the time pulse sequence and convert the time pulse sequence into an optical signal. The delay precision of the system can be effectively improved.

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

The invention discloses an anti-interference circuit and method for capacitance detection, and the circuit comprises a to-be-measured unit which is provided with a to-be-measured capacitor, a reference voltage and a common-mode voltage, the first end of the to-be-measured capacitor is selectively connected with the reference voltage and the common-mode voltage, and the second end of the to-be-measured capacitor is connected with a ground potential; the quantization unit is connected with the to-be-measured unit and the integration unit and is used for quantizing an integration capacitor in the integration unit; the integration unit comprises an integrator and an integration capacitor, and the input end of the integration unit is connected with the unit to be measured; the counting unit is connected with the output end of the integration unit; wherein the integrating capacitor comprises a first integrating capacitor and a second integrating capacitor, the first integrating capacitor and the second integrating capacitor are connected in parallel, and the quantization unit quantizes the first integrating capacitor and the second integrating capacitor respectively.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

A method of a signal transmission device includes: providing at least one delay line circuit having a plurality of first delay units connected in series; providing a control voltage as a supply voltage provided for a first delay unit of the at least one delay line circuit; and adjusting the control voltage to maintain a delay amount of the first delay unit at a specific delay amount when a variation of the delay amount of the first delay unit occurs.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

An isolated gate drive circuit and a driver, the isolated gate drive circuit includes signal restoration module, modulation module with first terminal and second terminal, high-pass filter module, and falling edge monitoring module; first pulse signal output from the first and second terminals are rail-to-rail differential pulse signals; When the isolated gate drive circuit restores the pulse width modulation signal, the isolated gate drive circuit monitors the first pulse signals output from the first and second terminals of the modulation module. When the pulse signal in the first pulse signal output from the first terminal or the second terminal of the modulation module is in a falling edge state, the falling edge monitoring module outputs a third pulse signal to the signal restoration module, the signal restoration module can quickly output the restored the pulse width modulation signal, improving the reliability of the isolated gate drive circuit.

The current disclosure is directed to a phase interpolator (PI) with phase correction circuitry. The phase interpolator may generate a clock signal with a phase value. The phase correction circuitry may adjust the phase value of the clock signal to compensate for at least a portion of the undesired distortions. The phase correction circuitry may store pre-determined delay values to at least partially compensate for the undesired distortions of the clock signal based on the control signals. The phase correction circuitry may output the clock signal, as adjusted, with improved phase value accuracy and / or clock signal linearity. In some cases, the phase correction circuitry may improve operations of the phase interpolator, or an electronic system including the phase interpolator, across variations in process, voltage, and / or temperature.

The utility model relates to a clock source device and test equipment applied to multiple test machines, the clock source device comprises a clock distribution module and a calibration module, the clock distribution module comprises a clock generator and delay controllers, each delay controller is connected with the clock generator and the corresponding test machine, and the calibration module is connected with the clock generator. The calibration module is connected with each test machine and each delay controller; wherein the clock generator outputs a clock signal to each delay controller; the delay controller outputs a clock signal to a corresponding test machine, and adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is in a set error range; the calibration module receives a calibration clock of the test machine and outputs a phase difference value to the corresponding delay controller. The clock transmitted to the testing machine is adjusted by combining the phase difference value output by the calibration module, so that clock frequency synchronization and phase synchronization of different testing machines are realized, and the synchronization control accuracy is improved.