246results about "Printed inductances" patented technology

Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.

An example device includes a first primary coil, a second primary coil, a combined power output, a first directional coupler output, a second directional coupler output. The example device also includes a secondary coil coupled to the combined power output, configured to magnetically couple to the first primary coil, and configured to magnetically couple to the second primary coil. The example device further includes a tertiary coil configured to magnetically couple to the secondary coil and including a first end coupled to the first directional coupler output, and a second end coupled to the second directional coupler output.

To provide a chip-type electronic component that can achieve both sufficient bonding strength during mounting and mitigation of stress concentration at the boundary between the base body and the electrode portion. [Solution] The chip-type electronic component 1A comprises a base body 2 formed by stacking a plurality of base layers 11, an internal conductor 3 disposed inside the base body 2, and an external electrode 4 electrically connected to the internal conductor 3 and embedded in the base body 2 flush with the outer surface of the base body 2. The outer surface of the base body 2 is provided with grooves M extending in a direction perpendicular to the stacking direction of the base layers 11 across the base body 2 and the external electrode 4.

A semiconductor device is provided. The semiconductor device includes a first conductive layer and second conductive layer. The second conductive layer is disposed opposite to the first conductive layer. One of the first conductive layer and the second conductive layer includes a first grounding net and a first signal ball-pad. The first grounding net has a first ground void, and the first signal ball-pad is disposed in the first ground void. The first signal ball-pad has a first ball-pad diameter, the first ground void has a first ground void diameter, and a ratio of the first ground void diameter to the first ball-pad diameter is equal to or greater than 1.2.

The present disclosure relates to semiconductor device packages and methods of manufacturing the same. The semiconductor device package includes a substrate having a first surface and a second surface opposite the first surface. The semiconductor device package also includes a first electrically conductive layer disposed over the first surface of the substrate and an insulating layer disposed over the first surface of the substrate. The semiconductor device package also includes a magnetically conductive layer disposed between the first electrically conductive layer and the insulating layer. The magnetically conductive layer has a bottom surface facing the first surface of the substrate, a top surface opposite the first surface of the substrate, and a side surface extending between the bottom surface of the magnetically conductive layer and the top surface of the magnetically conductive layer. Another embodiment of the present disclosure relates to a method of manufacturing a semiconductor device package.

This invention provides an inductor component. There is a concern that the lead-out electrodes may excessively interrupt magnetic flux when current flows through the inductor wiring. The inductor component (10) includes a blank (20). The blank (20) has a mounting surface (21) and a top surface (22) that are parallel to each other, a first end surface (23) and a second end surface (24) that are parallel to each other, and a first side surface and a second side surface that are parallel to each other. Inductor wiring (30) is disposed inside the blank (20). A first lead-out electrode (40) is connected to a first end in the extending direction of the inductor wiring (30). A second lead-out electrode (50) is connected to a second end in the extending direction of the inductor wiring (30). The lower surfaces of the first lead-out electrode (40) and the second lead-out electrode (50) are exposed from the mounting surface (21) of the blank (20). The first lead-out electrode (40) is a quadrangular prism extending in the height direction (Td). The first lead electrode (40) is exposed from the first end face (23) and the first side face.

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.

The invention provides a coil component which is not easy to generate a flash phenomenon on a circuit substrate. A coil component (100) is provided with: an element body (110) having a mounting surface (111); a coil part embedded in the element body (110) and comprising conductor layers (L1-L4) stacked in a Z direction parallel to the mounting surface (111); an insulating resin (130) positioned between the element body (110) and the coil part; a terminal electrode (121) that protrudes from the mounting surface (111) and is connected to one end of the coil part; and a terminal electrode (122) that protrudes from the mounting surface (111) and is connected to the other end of the coil part. The insulating resin (130) has an exposed portion (131) which is located between the terminal electrode (121) and the terminal electrode (122) on the mounting surface (111) and which is exposed so as to protrude from the mounting surface (111).

A laminated coil component includes an element body, a first terminal electrode and a second terminal electrode, and a coil, the coil includes a first wiring portion, a second wiring portion, and a pillar portion, the pillar portion has a first pillar member and a second pillar member alternately laminated in a second direction, and an area of a first surface and an area of a second surface of the first pillar member are larger than an area of a first surface and an area of a second surface of the second pillar member, or smaller than the area of the first surface and the area of the second surface of the second pillar member.

A laminated coil component includes an element body including insulating layers laminated in a lamination direction, a coil inside the element body, and an external electrode on a surface of the element body and electrically connected to the coil. The coil includes a coil conductors laminated in the lamination direction and electrically connected via a via conductor penetrating the insulating layer in the lamination direction. The coil conductors include a first laminated portion including three or more of the coil conductors adjacent to each other, a second laminated portion including the coil conductors adjacent to each other such that a number of the coil conductors in the second laminated portion is the same as a number of the coil conductors in the first laminated portion, and an intermediate portion adjacent to and between the first and second laminated portions and including one or two of the coil conductors.

A laminate non-planar radio-frequency (RF) choke device includes a first RF choke. The first RF choke has a first winding structure including a plurality of first conductive traces and a plurality of first vias. The first conductive traces are formed on a first layer and a second layer of a laminate. The first vias are formed between the first layer and the second layer of the laminate. The first vias are stitched in a winding direction through the first conductive traces.

Microelectronic integrated circuit package structures include a package substrate with a core, and an inductor having a length extending vertically through the core. The inductor includes a magnetic material on a sidewall of the core, and a first conductive liner on a sidewall of the magnetic material, where a portion of the first conductive liner that is in a plane orthogonal to the length of the inductor comprises a first opening. A portion of a second conductive liner on the sidewall of the magnetic material that is in the plane comprises a second opening, where the first opening and the second opening face each other and are separated by a distance.

An electronic module includes a circuit board, a plurality of electronic components disposed on and electrically connected to the circuit board, a package disposed on the circuit board to encapsulate the plurality of electronic components, wherein a first recess is formed in the package, and a first electrode, wherein at least a portion of an electrode of an external component is disposed in the first recess and electrically connected to the first electrode of the electronic module.

The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure including a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.

Systems, apparatus, products, and methods for supplying power through a package substrate comprising a stack of glass layers having different coefficients of thermal expansion are disclosed. [Solution] An exemplary substrate for an integrated circuit package comprises: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE being different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between the inner wall of the first hole and the conductive material.

A signal transmission element includes a first insulating layer on a semiconductor substrate, first and second coils thereon, a second insulating layer covering the first and second coils, third and fourth coils thereon, and a protective film covering the third and fourth coils. The first and third coils are magnetically coupled, the second and fourth coils are magnetically coupled, the first and second coils are connected to each other such that a current generated by mutual induction between the first coil and the third coil flows through the second coil, and the protective film includes a plurality of openings reaching two ends of the third coil and two ends of the fourth coil.

To provide a method of manufacturing a laminated coil component capable of suppressing occurrence of variations in characteristics.SOLUTION: In the manufacturing method of the laminated coil component 1, the element body 2 is formed by laminating a plurality of resin layers, the coil 5 including the first wiring portion 6, the second wiring portion 7, and the pillar portion 8 is formed by using a photolithography method, and the pillar portion 8 includes a first pillar member 8A and a second pillar member 8B alternately laminated in the second direction D2. The area of the first surface 8A and the area of the second surface 8Aa of the first pillar member 8Ab are made larger than the area of the first surface 8B and the area of the second surface 8Ba of the second pillar member 8Bb, or made smaller than the area of the first surface 8B and the area of the second surface 8Ba of the second pillar member 8Bb.SELECTED DRAWING: Figure 2

This application is directed to a magnetic device implemented as a thin film inductor. The magnetic device includes a first magnetic layer, a second magnetic layer, and a conductive wire. The conductive wire is configured to carry an electric current flowing along a first direction. The magnetic device further includes an insulation structure having a varying thickness on a cross section that is perpendicular to the first direction. The cross section of the insulation structure includes a central region and two flux regions. The central region separates the conductive wire from the first magnetic layer. The two flux regions are located on two opposite sides of the central region and separate the second magnetic layer from the first magnetic layer. Each of the two flux regions is defined according to a flux separation threshold and has a respective width less than a parasitic width threshold.

The invention relates to inductors with air gap electrical isolation. Structures including inductors and methods of forming such structures are disclosed. The structure includes a semiconductor substrate including a plurality of first sealed cavities, and a back-end process stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end process stack includes an inductor having a winding overlapping the sealed cavity.

An apparatus includes a substrate that includes a first integrated inductor. The first integrated inductor includes a first core material disposed within a first cavity of the substrate. The first integrated inductor also includes a first set of conductive windings that at least partially encircle the first core material within the first cavity.

This specification presents a method for fabricating an inductor or inductor pair through a substrate, such as a substrate core or carrier. The inductor has at least one winding that connects through the substrate. The inductor suffers from loss performance due to the winding penetrating the substrate, but this allows for placement according to a common center of gravity approach during manufacturing and in use after manufacturing. This produces nearly identical inductors suitable for matching or pairing.

To provide an inductor component which improves inductance characteristics and Q characteristics.SOLUTION: An electronic component includes an element body 10, a coil 20 provided in the element body, and first and second external electrodes 30, 40 provided on the element body and electrically connected to the coil, wherein the element body includes first and second end surfaces 15, 16, a bottom surface 17, and a top surface 18, and the first external electrode has a first end surface portion extending along the first end surface 15 and a first bottom surface portion connected to the first end surface portion and extending along the bottom surface. The second external electrode includes a second end surface portion extending along the second end surface and a second bottom surface portion connected to the second end surface portion and extending along the bottom surface, the axis is parallel to the bottom surface and intersects the first side surface and the second side surface, and when viewed in the axial direction, the coil is annularly arranged from a first portion facing the top surface to eighth portions 21 to 28 facing the second end surface, the second portion is closer to the first end surface than the third portion, the eighth portion is closer to the second end surface than the seventh portion, and the fifth portion is closer to the bottom surface than the fourth portion and the sixth portion.SELECTED DRAWING: Figure 2

To provide a multilayer inductor for improved reliability.SOLUTION: In a multilayer inductor 10, an internal electrode 20 includes auxiliary conductors 26 and 28, and the auxiliary conductors 26 and 28 are joined to external electrodes 14A and 14B at the end surfaces 12a and 12b, and therefore, when a problem occurs in some of the through conductors, a current flows through the remaining through conductor and also through the auxiliary conductor. Therefore, overheating at the joint surfaces S between the remaining through conductors and the external electrodes 14A and 14B is suppressed, and fusion starting from the joint surfaces S can be suppressed.SELECTED DRAWING: Figure 3

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the sealed cavities.

An integrated circuit structure is provided. The integrated circuit structure includes a substrate, a patterned ground shield structure, and a shielded circuit. The patterned ground shield structure is disposed above the substrate. The patterned ground shield structure includes a central portion and branches. The branches are connected to the central portion. The branches substantially extend radially from a central point of the central portion and surround the central portion. The shielded circuit including at least one conductive line is located directly above the patterned ground shield structure.