914results about "Printed inductances" patented technology

Disclosed embodiments may include systems, devices and methods for fabricating high-density charge-storage devices and power conversion devices. In one embodiment, a device is disclosed, comprising an inductor. The inductor includes a first inductor surface and a second inductor surface opposite the first inductor surface. The inductor further includes a first inductor substrate including a cavity. A seed layer is formed on a bottom surface of the cavity, and a magnetic layer is formed on the seed layer. The magnetic layer includes a plurality of stacked magnetic layers separated from each other by an insulating material layer.

Aspects of the present disclosure include galvanically-isolated (voltage-isolated) transformer-based integrated circuit (IC) packages providing cavities or spaces, which can, in some examples, be formed by preferentially heating the included magnetic core or a material coating the magnetic core. The provision of a space around the magnetic core allows the magnetic core to underdo size changes due to magnetostriction during use without being constrained or substantially constrained, thus, providing for improved magnetic performance. The circuits, ICs and IC packages and modules may include various types of circuits. In some examples, IC packages or modules may include a galvanically-isolated gate driver or other high voltage circuit.

A packaged integrated circuit (IC) including a package substrate. The package substrate includes pins; a first metal layer on the pins; a second metal layer on the first metal layer; vias on the second metal layer; an insulation material covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins and the vias. The packaged IC further includes a semiconductor die on the package substrate, the semiconductor die having a surface opposing the second metal layer; metal posts coupled between the semiconductor die and the exposed surfaces of the vias; and a mold compound covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer by the insulation material and the mold compound.

The invention discloses a radio frequency signal matching network, a frequency mixer, a phase shifter, a radar sensor and electronic equipment, the radio frequency signal matching network comprises a first inductor with an I-path input end, a second inductor with a Q-path input end, and a third inductor which is inductively coupled with the first inductor and the second inductor, and the third inductor is provided with an output end; wherein the I-path input end is set to receive I-path radio frequency signals, and the Q-path input end is set to receive Q-path radio frequency signals.

An example planar inductor includes a winding structure including a plurality of conductive windings arranged in layers of a printed circuit board (PCB) around a core, where the plurality of conductive windings include at least a top winding and a bottom winding. The planar inductor includes a conductive shield encasing the winding structure. The conductive shield includes an upper conductive shield layer disposed over the winding structure in a first direction, a lower conductive shield layer disposed under the winding structure in a second direction opposite the first direction, an inner conductive shield disposed within and around the plurality of conductive windings, and an outer conductive shield disposed around and outside the plurality of conductive windings.

A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

Described herein are inductor devices formed using wafer processing techniques. The inductor devices are singulated and can be mounted into different packages or computing systems. The magnetic material included in the inductor devices have higher aspect ratios (e.g., relatively tall and thin magnetic regions), which may be achieved using electroplating. The electroplated magnetic material is highly concentrated, which enables a higher inductance density.

The invention provides a coil assembly. The coil component includes: a body including a first surface and a second surface opposite to each other in a first direction and a third surface and a fourth surface opposite to each other in a second direction; a coil disposed in the main body; a first extraction electrode connected to an outer end of the coil and protruding to the first surface; a second extraction electrode connected to an inner end of the coil and protruding to the second surface; a first external electrode disposed on the third surface, extending to the first surface, and connected to the first extraction electrode; and a second external electrode disposed on the third surface, extending to the second surface, and connected to the second extraction electrode, in which a thickness of each of the first extraction electrode and the second extraction electrode in the second direction is smaller than a thickness of the coil in the second direction.

A packaged integrated circuit (IC) (300) including a package substrate (110). The package substrate includes pins (321); a first metal layer (323) on the pins; a second metal layer (325) on the first metal layer; vias (322, 324, 326) on the second metal layer; an insulation material (308a, 308b) covering the pins, the first metal layer, the second metal layer, and the vias, and exposing surfaces of the pins and the vias. The packaged IC further includes a semiconductor die (101) on the package substrate, the semiconductor die having a surface (301) opposing the second metal layer; metal posts (305a, 305b) coupled between the semiconductor die and the exposed surfaces of the vias (326); and a mold compound (304, 304a) covering the semiconductor die and the metal posts, in which the surface is separated from the second metal layer (325) by the insulation material (308a) and the mold compound (304a).

Proposed is a laminated common mode filter in which a ground pattern is interposed between coil patterns to form additional capacitance. The proposed laminated common mode filter comprises: an upper electrode layer composed of a laminate having a first coil pattern, a second coil pattern, and a third coil pattern; a ground layer that is arranged on the lower portion of the upper electrode layer and has a ground pattern; and a lower electrode layer that is arranged on the lower portion of the ground layer and is composed of a laminate having a forth coil pattern, a fifth coil pattern, and a sixth coil pattern, wherein the ground pattern is arranged to overlap the coil patterns of the upper electrode layer and the coil patterns of the lower electrode layer to form capacitance.

An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

The embodiment of the present application discloses an inductor device wiring architecture, including an inductor device and multiple virtual metals located below the inductor device. The multiple virtual metals are arranged in a multi-layer metal layer, each metal layer in the multi-layer metal layer corresponds to a portion of the virtual metals of the multiple virtual metals, and in the direction away from the inductor device, the arrangement area of ​​the virtual metals corresponding to at least two metal layers in the multi-layer metal layer increases. The above-mentioned inductor device wiring architecture can reduce the adverse effects on the performance of the inductor device and improve the product yield. The embodiment of the present application also discloses an integrated circuit and a communication device.

The inductor includes a substrate, a plurality of first horizontal wires above an upper surface of the substrate, a plurality of second horizontal wires above a back surface of the substrate, and a plurality of vertical wires, wherein the plurality of vertical wires connect the plurality of first horizontal wires to the plurality of second horizontal wires to form a spiral.

A passive component includes a body portion having a first main surface and a passive element at least a part of which is provided inside the body portion. The first main surface at least partially includes a flat surface made of an inorganic substance and having a surface roughness of equal to or less than 1 / 1000 of a thickness of the body portion in a direction orthogonal to the first main surface or equal to or less than 10 nm.

The present invention improves the strength of a terminal part in a coil component having a planar coil pattern that can be electrically accessed from the front and back. A coil component (100) includes a planar coil pattern (10), a first resin layer (21) covering a first main surface (11) of the coil pattern, and a magnetic body (30) covering a second main surface (12) of the coil pattern. The coil pattern includes a terminal portion (10A) at an end portion, the first resin layer has a first opening portion (V1) in a portion overlapping a first main surface of the terminal portion, and the magnetic body has a second opening portion (V2) in a portion overlapping a second main surface of the terminal portion. The first main surface of the terminal portion has a first portion (A1) overlapping the first opening portion, and a second portion (A2) covered by the first resin layer. The second main surface of the terminal portion has a third portion (A3) overlapping the second opening portion, and a fourth portion (A4) covered by the magnetic body.

An electronic device may include wireless circuitry having an on-chip transformer. The transformer may convey a radio-frequency signal and may include a primary coil and a secondary coil. The primary coil may have a center tap. A distributed capacitor array (DCA) may be coupled to the primary coil around the center tap. The DCA may include switchable capacitors coupled in parallel between ground and points on the primary coil on either side of the center tap. When active, each switchable capacitor contributes a different weighting to the operation of the transformer based on its distance from the center tap. A set of one or more of the switchable capacitors may be activated to contribute an asymmetric weighting to the operation of the transformer that mitigates process-related asymmetry in the transformer. This may serve to mitigate undesired common mode to direct mode signal conversion by the transformer.

A multilayer inductor is provided. The multilayer inductor includes a multilayer winding portion comprising a plurality of coil layers that are vertically stacked, and having an inner surface that defines a hollow of the plurality of coil layers and having an outer surface that defines an outer side and a magnetic compensator made of a soft magnetic material and comprising a magnetic wall located at at least one of the inner surface or the outer surface of the multilayer winding portion.

A coil component 100A comprising: a coil part 10 that includes a first spiral conductor part 11 which has a spiral shape when viewed in in a first direction (Z1-Z2 direction); a body part 30 that contacts and covers the coil part in a manner such that both ends of the coil part 10 are exposed, and that contains a magnetic powder; a separate conductor part 400 that has a portion which is embedded in the body part 30 and that is separate from the coil part 10; and a pair of external electrodes (first terminal part 41, second terminal part 42) that respectively contact both ends of the coil part 10 which are exposed from the body part 30, and that are electrically connected via the coil part 10, wherein, when a plane that is along the first direction (Z1-Z2 direction) and that is shared with the first spiral conductor part 11 is defined as a first plane, the separate conductor part 400 includes a first separate conductor part 401 which has a first exposed surface 401a that is exposed from the body part 30 in an in-plane direction of the first plane, and the first separate conductor part 401 contacts one of the pair of external electrodes (first terminal part 41, second terminal part 42) at the first exposed surface 401a.

Provided is a smaller filter circuit. The filter circuit has an LC circuit, one end of which is connected to a signal path connecting an input terminal and an output terminal, and the other end of which is connected to a reference potential. A filter circuit according to a first embodiment includes a substrate and a plurality of electrodes provided on a main surface or inside of the substrate. The LC circuit includes a first capacitor, a first inductor connected in parallel, and a second capacitor connected in series. The electrodes overlap each other at least partially when viewed in the thickness direction of the substrate. The portion where the electrodes overlap each other is the electrode of the first capacitor or the second capacitor.

A three-dimensional inductor and a method of manufacturing the same are disclosed. The three-dimensional inductor includes a substrate, a plurality of first horizontal wirings over an upper surface of the substrate, a plurality of second horizontal wirings over a back surface of the substrate, and a plurality of vertical wirings, the plurality of vertical wirings connect the plurality of first horizontal wirings to the plurality of second horizontal wirings to form a spiral body.

Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

A multilayer coil component includes an element body, a coil, and an external terminal. The element body includes a plurality of insulator layers that is laminated. The coil is disposed in the element body. The external terminal includes a plurality of conductor layers that is laminated. The external terminal is electrically connected to the coil. The element body includes a main face and a first side face adjacent to the main face. The external terminal is embedded in the element body in such a way as to be separated from the first side face and exposed from the main face. The external terminal includes a first separated face that is separated from the first side face as being separated from the main face.

A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

A structure includes a first layer having inductor windings. An inner area of the first layer is at least partially enclosed by the inductor windings and an outer area of the first layer is separated from the inner area by the inductor windings. This structure further includes a second layer having structural fill elements. The first layer and the second layer are parallel, and the second layer is relatively below the first layer in a direction perpendicular to the first layer. The density of the structural fill elements aligned below the inner area is less than the density of the structural fill elements aligned below the outer area.

Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.

A coil electronic component includes a support substrate, a coil pattern disposed on the support substrate, an encapsulant encapsulating at least portions of the support substrate and the coil pattern, and external electrodes disposed externally on the encapsulant and connected to the coil pattern. The coil pattern includes a seed layer having a thickness of 1.5 μm or less and a plating layer disposed on the seed layer.

A coil electronic component includes: a first coil; a second coil spaced apart from the first coil; an intermediate layer disposed to extend from a first region between a first core (hollow space) of the first coil and a second core of the second coil to a second region between the first coil and the second coil; and a magnetic body surrounding the first coil, the second coil, and the intermediate layer, wherein the intermediate layer has a smaller permeability than that of the magnetic body.

An example device includes a first primary coil, a second primary coil, a combined power output, a first directional coupler output, a second directional coupler output. The example device also includes a secondary coil coupled to the combined power output, configured to magnetically couple to the first primary coil, and configured to magnetically couple to the second primary coil. The example device further includes a tertiary coil configured to magnetically couple to the secondary coil and including a first end coupled to the first directional coupler output, and a second end coupled to the second directional coupler output.

A matching network of a radio frequency signal, a mixer, a phase shifter, a radar sensor and an electronic apparatus. The matching network of the radio frequency signal includes a first inductor (L1) having an I input terminal, a second inductor (L2) having a Q input terminal, and a third inductor (L3) inductively coupled to both the first inductor and the second inductor, the third inductor has an output terminal; wherein the I input terminal is configured to receive a radio frequency signal of an I channel, and the Q input terminal is configured to receive a radio frequency signal of a Q channel.

A multilayer common mode filter of the present disclosure is a filter comprising a plurality of coils configuring mutually different channels, wherein a plurality of coil patterns, and a plurality of via conductors connecting the coil patterns are provided inside a coil stack, and the plurality of via conductors are arranged, on a floor plan of the coil stack, in positions where same do not overlap with each other.