18179 results about "Integrated circuit" patented technology

The invention relates to the technical field of defect detection, and discloses an integrated circuit mask plate defect multispectral cooperative detection method, which comprises the following steps: carrying out preliminary scanning on a mask plate by using a multispectral camera, selecting an optimal wave band combination, switching to a target wave band through a liquid crystal adjustable optical filter, and obtaining a high-confidence multispectral image; the optical path offset is calculated through the linear relation, the deflection angle of the micro-mirror is dynamically adjusted, and images are collected for the second time after imaging offset is compensated; image filtering and registration are completed in the FPGA, and a high-contrast fusion image is generated; if the confidence coefficient is insufficient, triggering a wave band reselection mechanism to recheck; dynamically optimizing a defect type-spectrum mapping table based on real-time detection data; when the environment fluctuation exceeds the limit, an anti-interference mode is automatically switched, and micro-mirror calibration is triggered; and monitoring performance degradation of the optical assembly in real time, switching redundant optical paths, cleaning damaged parts, triggering manual reinspection when conflicts occur, and finally generating a visual report. According to the invention, the detection accuracy of the integrated circuit mask plate can be improved.

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

A chip package includes a housing, one or more electrical connections coupled to an exterior of the housing, a photonic integrated circuit, and a scanning unit. Both the photonic integrated circuit and the scanning unit are disposed within the housing. The photonic integrated circuit has at least one waveguide designed to guide a beam of light. The scanning unit is designed to laterally scan the beam of light across a focal plane outside of the housing. The scanning unit is aligned with the photonic integrated circuit such that the beam of light is coupled between the photonic integrated circuit and the scanning unit.

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention provides a PCIe resource dynamic configuration method and device, and relates to the technical field of computer hardware resource management. The method comprises the following steps of: establishing communication connection with the pluggable equipment through an expansion interface, and reading equipment identification information pre-stored in a characteristic value storage module of the pluggable equipment by utilizing an I2C (Inter-Integrated Circuit) interface; identifying mainboard PCIe resource allocation parameters and the equipment identification information; displaying configurable PCIe resource parameters on a system configuration interface, and providing configuration options which can be operated by a user; according to the device identification information and a configuration option selected by a user, a pre-stored PCIe configuration mapping table is inquired, a corresponding PCIe resource configuration instruction is generated, and the PCIe configuration mapping table comprises the device identification information and the corresponding relation between the configuration option and the PCIe resource configuration instruction; and configuring PCIe resource allocation of the mainboard according to the PCIe resource allocation instruction.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

The present invention discloses an integrated circuit chip with an address code, a key, and a mechanical keyboard. The integrated circuit chip contains a programmable address code, integrates a magnetic induction circuit, a GRB magic color drive circuit, and includes a power pin, a ground pin, and a data pin. The power pins of n integrated circuit chips are connected in parallel to share a power network VCC, the ground pins are connected in parallel to share a ground network GND, and the data pins are connected in parallel to share a data line network DIO connected to an MCU, and data information is transmitted on the data line network DIO. Another integrated circuit chip with an address code only requires a power network VCC and a ground network GND, and data information is modulated and transmitted on the power network, which greatly saves wiring space, reduces the difficulty of PCB design, and exponentially reduces the number of electronic components. In addition, a variety of different customized code sending methods and working modes are provided, making its application simpler, more efficient, and more reliable.

The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium, is suitable for a processor comprising a first integrated circuit unit and a second integrated circuit unit, and comprises the following steps: acquiring to-be-transmitted data and providing the to-be-transmitted data to the first integrated circuit unit; the verification information of the data to be transmitted is generated, the verification information comprises state information of a forward error correction code, data information of the forward error correction code and state information of cyclic redundancy check, and the data information of the forward error correction code and error data in the data to be transmitted have a corresponding relation; and sending the verification information and the to-be-transmitted data to the second integrated circuit unit, so that the second integrated circuit unit sends the to-be-transmitted data to the second integrated circuit unit under the condition that the state information of the forward error correction code is error-free or correctable error and the state information of the cyclic redundancy check is error-free. And a correct cyclic redundancy check code is calculated based on the received data to be transmitted and the data information of the forward error correction code, so that efficient data transmission is realized.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

The invention discloses an intelligent equivalent modeling and simulation optimization method based on machine learning and multi-physics field coupling, and the method employs a 2.5 D chip stress simulation method combining a customized material with equivalent parameters output by a Python script, and can remarkably reduce the calculation time and memory resource consumption on the premise of guaranteeing high precision. Based on DNN trained by large-scale historical data, an equivalent model can be dynamically adjusted in the simulation process, and more optimized stress analysis is achieved; according to the method, the research and development period can be greatly shortened, the design reliability is improved, and the method has very high practical value and commercial value; through construction of an equivalent model and application of an automatic script, a designer can more efficiently carry out stress analysis and optimization of the 2.5 D chip, and a brand new solution is provided for design of an integrated circuit.

The invention relates to the technical field of integrated circuit testing, in particular to a distance-adjustable probe connector device which comprises an impedance detection unit which comprises a connector fixing part, a connector rotating part, a single connection port, a signal probe and a grounding probe. The impedance data unit is used for determining a characteristic impedance value of the tested microstrip line based on data acquired by the signal probe and the grounding probe; the pressure detection unit is used for determining the contact pressure according to the telescopic displacement of the signal probe and the grounding probe; the control unit determines the allowable range of the contact pressure of the probes based on the line width of the microstrip line to be tested and the distance between the probes, and adjusts the angle between the grounding probe and the surface of the PCB based on the contact pressure difference between the signal probe and the grounding probe and the line width of the microstrip line. And adjusting the contact pressure of the signal probe to obtain the effective characteristic impedance value of the tested microstrip line. According to the invention, the angle and pressure of the grounding probe are intelligently adjusted, and the problem of impedance measurement drift caused by pressure imbalance of double probes is eliminated.

The invention relates to the technical field of integrated circuits and computer networks, and particularly discloses a transmission control and intelligent scheduling system for an integrated chip, and the system sets a dual-mode decision and dynamic switching mechanism for each routing node. Calculating dynamic characteristic parameters including an instantaneous value, a first-order trend and a second-order acceleration; when the parameter is matched with a pre-stored abnormal feature set and the load exceeds a threshold value, the node is immediately atomized and switched to a predefined security scheduling strategy loaded from a shared storage area, and otherwise, the node generates a scheduling decision according to self-adaptive decision logic continuously optimized based on historical performance feedback; all the nodes carry out data packet forwarding control according to the current execution strategy; and the system also periodically realizes federated global knowledge evolution according to the quality evaluation result of the self-adaptive decision of each node.

Aspects of the present disclosure include methods for spectrally resolving light from fluorophores in a sample. Methods according to certain embodiments include detecting light with a light detection system from a sample having a plurality of fluorophores having overlapping fluorescence spectra and spectrally resolving light from each fluorophore in the sample with a generalized least squares algorithm. In some embodiments, methods include estimating the abundance of one or more of the fluorophores in the sample, such as on a particle. In certain instances, methods include identifying the particle in the sample based on the abundance of each fluorophore and sorting the particle. Methods according to some embodiments includes spectrally resolving the light from each fluorophore by calculating a spectral unmixing matrix for the fluorescence spectra of each fluorophore. Systems and integrated circuit devices (e.g., a field programmable gate array) for practicing the subject methods are also provided.

The invention discloses a 10KV station electric control system of a convertor station adopting selecting 2 from 3 logic. Two PS830 boards are added, three PS830 boards are utilized to concurrently process and jointly realize a spare power automatic switching function and an operation interlocking logic function; the selecting 2 from 3 logic is added in PS853 programs of an ASI host machine and a switching value output board, i.e. the electric control system can be exported when at least two of three integrated circuit boards sends out same instructions. The damage of any one of the three PS830 boards can not lead to switch fault trip or refusing trip, the 10KV control system can be ensured to run safely and stably without being influenced by the faults of single element. The electric control system has the advantages of convenient use, safety and the like.

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The invention provides a processor memory access optimization implementation method and system with multi-channel concurrent instructions, and relates to the technical field of processor integrated circuits, and the method comprises the steps: obtaining a Load instruction and a Store instruction to be executed; distributing a plurality of memory access instructions to each memory access channel which is independently processed in parallel, wherein each memory access channel comprises a Load memory access channel and a Store memory access channel; an independent Load queue and an independent RAW check queue are arranged in the Load memory access channel, and an independent Store queue, an independent STD queue and an independent Store Buffer queue are arranged in the Store memory access channel; the Load instruction is sequentially subjected to an address generation stage, a TLB parallel query stage, an L1Cache access stage, a RAW check and data forward push stage and a data write-back stage in the Load memory access channel; according to the method, address and data separation processing is carried out on a Store instruction, an address part enters a Store queue, a data part enters an STD queue, then merging is carried out, multiple Store operations on the same Cache Line are merged into one-time writing, the merged data are written into a Store Buffer queue, and then the Store Buffer queue submits and caches in a unified mode.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention discloses an integrated circuit heat distribution optimization method driven by fusion situation awareness, and particularly relates to the technical field of integrated circuit heat distribution optimization, which comprises the following steps: acquiring a behavior fragment set in an integrated circuit, performing regulation and control trigger sequence adjustment and regulation and control chain atlas construction operation, constructing a regulation and control chain atlas, and establishing a regulation and control chain atlas; performing identification and extraction operation of path traversal on the regulation and control chain atlas, and performing mapping to generate a disturbance input variable set; extracting data in the disturbance input variable set, performing normalization processing and time sequence reconfiguration operation, and constructing a disturbance response track; a regulation and control path structure caused by a temperature control behavior in an integrated circuit is extracted, and a stability identification model is constructed based on path disturbance propagation characteristics and behavior feedback offset, so that dynamic judgment and regulation and control structure optimization of a potential thermal feedback chain in a multi-core environment are realized, and task scheduling imbalance caused by path evolution accumulation is avoided.

The invention relates to the technical field of chip heat dissipation, and provides an immersed heat dissipation system with liquid nitrogen as a cooling medium and an integrated circuit assembly. In an immersed heat dissipation system with liquid nitrogen as a cooling medium, huge heat generated by a high-power-density chip under an extreme working condition can be efficiently absorbed and taken away under the extremely low working temperature and the large phase change heat absorption capacity, the heat transfer limit of a traditional cooling technology is broken through, and deep cooling of the chip is achieved; meanwhile, the liquid nitrogen is non-conductive and stable in chemical property, the electrical short circuit risk and physical and chemical corrosion problems caused by leakage of the cooling working medium are thoroughly eliminated, and the long-term operation reliability and safety of the immersed heat dissipation system with the liquid nitrogen as the cooling medium are remarkably improved. Therefore, stable operation of the chip under high load is guaranteed, physical damage and performance frequency reduction caused by overheating are avoided, and even favorable conditions are created for safe and efficient operation of the chip under higher working frequency.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention relates to the technical field of integrated circuit temperature compensation and high-precision calibration, and discloses a high-density full-temperature trimming method and system based on a fuze chip. The high-density full-temperature trimming method is applied to chip trimming equipment and specifically comprises the following steps that S101, temperature information of a fuze chip is received, the working temperature range of the fuze chip is divided into a plurality of continuous temperature sub-intervals, calibration points are uniformly deployed in each sub-interval, and the temperature information of the fuze chip is acquired; the temperature coordinates of the calibration points are collected in real time through the high-precision temperature sensor and then quantized through the analog-to-digital converter. According to the method, the density of calibration points in subintervals is dynamically adjusted, nonlinear characteristics of a temperature sensitive area are effectively captured, and the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below in combination with a cubic Hermite interpolation and residual compensation algorithm. In addition, the local fitting error between adjacent calibration points is reduced to 0.02 DEG C or below through application of a redundancy check storage architecture and an interleaving addressing technology. And the single event upset resistance of the calibration parameters is improved.

The invention relates to an application method of a GPU (Graphics Processing Unit) in design rule inspection in the field of integrated circuits, in particular to a layout design rule inspection method, system and equipment, a medium and a product. The layout design rule checking method comprises the following steps: inputting initial layout data, analyzing a design rule checking task to be executed, and marking the priority and complexity level of the task; the method comprises the following steps: dividing layout data into a plurality of data blocks according to regions on the basis of regional characteristics of the layout data, distributing tasks and corresponding data blocks to a GPU computing core according to task priorities and complexity levels, and distributing new data blocks according to the overall load condition of the GPU computing core after the GPU computing core completes data block processing, and repeating the steps until all tasks are executed, and outputting a layout design rule check result. The system, the computer equipment, the computer readable storage medium and the computer program product have the same beneficial effects as the layout design rule checking method.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed-adjustable fan driving and anomaly detection circuit with high reliability and low cost. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed; the open circuit and locked-rotor detection module is connected with the logic control module and the VIN port of the LDO; and the short circuit detection module is connected with the logic control module and the output end of the LDO, outputs a signal to a state flag bit FTO, and judges whether the fan is in a normal working state, an open circuit state, a locked-rotor state or a short circuit state or not according to the waveform and the level of the state flag bit FTO. The speed-adjustable fan driving circuit is integrated, and the function of detecting various abnormal states of the fan is achieved.

The invention discloses a micro-channel liquid cooling method, device, equipment and medium for heat dissipation of an integrated circuit chip, and the method comprises the steps: collecting temperature data of different depths of the surface and the interior of the chip in real time through a temperature sensor array, an embedded temperature probe and an infrared detector, and generating a three-dimensional temperature field matrix; carrying out region division according to the microchannel physical layout of the chip, mapping a three-dimensional temperature field matrix, and generating a region temperature field matrix; calculating a thermal load change rate of the regional temperature field matrix, and generating a main flow regulation parameter by adopting a PI D algorithm based on the change rate; calculating branch flow adjusting parameters by combining the temperature field matrixes of the adjacent areas and a pre-constructed topological association table, and fusing the main flow adjusting parameters and the branch flow adjusting parameters to generate a flow adjusting quantity instruction. According to the invention, dynamic and accurate regulation and control of chip heat dissipation are realized, and the heat dissipation efficiency is effectively improved.