14689 results about "Integrated circuit" patented technology

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

A chip package includes a housing, one or more electrical connections coupled to an exterior of the housing, a photonic integrated circuit, and a scanning unit. Both the photonic integrated circuit and the scanning unit are disposed within the housing. The photonic integrated circuit has at least one waveguide designed to guide a beam of light. The scanning unit is designed to laterally scan the beam of light across a focal plane outside of the housing. The scanning unit is aligned with the photonic integrated circuit such that the beam of light is coupled between the photonic integrated circuit and the scanning unit.

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

The invention relates to the technical field of integrated circuit testing, in particular to a distance-adjustable probe connector device which comprises an impedance detection unit which comprises a connector fixing part, a connector rotating part, a single connection port, a signal probe and a grounding probe. The impedance data unit is used for determining a characteristic impedance value of the tested microstrip line based on data acquired by the signal probe and the grounding probe; the pressure detection unit is used for determining the contact pressure according to the telescopic displacement of the signal probe and the grounding probe; the control unit determines the allowable range of the contact pressure of the probes based on the line width of the microstrip line to be tested and the distance between the probes, and adjusts the angle between the grounding probe and the surface of the PCB based on the contact pressure difference between the signal probe and the grounding probe and the line width of the microstrip line. And adjusting the contact pressure of the signal probe to obtain the effective characteristic impedance value of the tested microstrip line. According to the invention, the angle and pressure of the grounding probe are intelligently adjusted, and the problem of impedance measurement drift caused by pressure imbalance of double probes is eliminated.

The invention relates to the technical field of integrated circuits and computer networks, and particularly discloses a transmission control and intelligent scheduling system for an integrated chip, and the system sets a dual-mode decision and dynamic switching mechanism for each routing node. Calculating dynamic characteristic parameters including an instantaneous value, a first-order trend and a second-order acceleration; when the parameter is matched with a pre-stored abnormal feature set and the load exceeds a threshold value, the node is immediately atomized and switched to a predefined security scheduling strategy loaded from a shared storage area, and otherwise, the node generates a scheduling decision according to self-adaptive decision logic continuously optimized based on historical performance feedback; all the nodes carry out data packet forwarding control according to the current execution strategy; and the system also periodically realizes federated global knowledge evolution according to the quality evaluation result of the self-adaptive decision of each node.

The invention discloses a 10KV station electric control system of a convertor station adopting selecting 2 from 3 logic. Two PS830 boards are added, three PS830 boards are utilized to concurrently process and jointly realize a spare power automatic switching function and an operation interlocking logic function; the selecting 2 from 3 logic is added in PS853 programs of an ASI host machine and a switching value output board, i.e. the electric control system can be exported when at least two of three integrated circuit boards sends out same instructions. The damage of any one of the three PS830 boards can not lead to switch fault trip or refusing trip, the 10KV control system can be ensured to run safely and stably without being influenced by the faults of single element. The electric control system has the advantages of convenient use, safety and the like.

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The invention provides a processor memory access optimization implementation method and system with multi-channel concurrent instructions, and relates to the technical field of processor integrated circuits, and the method comprises the steps: obtaining a Load instruction and a Store instruction to be executed; distributing a plurality of memory access instructions to each memory access channel which is independently processed in parallel, wherein each memory access channel comprises a Load memory access channel and a Store memory access channel; an independent Load queue and an independent RAW check queue are arranged in the Load memory access channel, and an independent Store queue, an independent STD queue and an independent Store Buffer queue are arranged in the Store memory access channel; the Load instruction is sequentially subjected to an address generation stage, a TLB parallel query stage, an L1Cache access stage, a RAW check and data forward push stage and a data write-back stage in the Load memory access channel; according to the method, address and data separation processing is carried out on a Store instruction, an address part enters a Store queue, a data part enters an STD queue, then merging is carried out, multiple Store operations on the same Cache Line are merged into one-time writing, the merged data are written into a Store Buffer queue, and then the Store Buffer queue submits and caches in a unified mode.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

The invention discloses an integrated circuit heat distribution optimization method driven by fusion situation awareness, and particularly relates to the technical field of integrated circuit heat distribution optimization, which comprises the following steps: acquiring a behavior fragment set in an integrated circuit, performing regulation and control trigger sequence adjustment and regulation and control chain atlas construction operation, constructing a regulation and control chain atlas, and establishing a regulation and control chain atlas; performing identification and extraction operation of path traversal on the regulation and control chain atlas, and performing mapping to generate a disturbance input variable set; extracting data in the disturbance input variable set, performing normalization processing and time sequence reconfiguration operation, and constructing a disturbance response track; a regulation and control path structure caused by a temperature control behavior in an integrated circuit is extracted, and a stability identification model is constructed based on path disturbance propagation characteristics and behavior feedback offset, so that dynamic judgment and regulation and control structure optimization of a potential thermal feedback chain in a multi-core environment are realized, and task scheduling imbalance caused by path evolution accumulation is avoided.

The invention discloses a clock optimization method, device and equipment and a computer readable storage medium, which are applied to the field of integrated circuits, and comprise the following steps: reading a netlist of each fragment, and traversing each netlist to generate an instance tree corresponding to each fragment; performing reverse tracing and forward tracing on each clock signal based on each instance tree to obtain a clock network path corresponding to each clock signal; determining a redundant clock according to each clock network path, and performing corresponding processing on the redundant clock; the redundant clock comprises an isolated redundant clock and an equivalent redundant clock. According to the method, the instance tree is generated by traversing the netlist, and the complete clock network path is obtained by combining reverse tracing and forward tracing, so that isolated redundant clocks and equivalent redundant clocks can be comprehensively captured, and automatic tracking of the clock network path and accurate identification of the redundant clocks are realized; the redundant clock is correspondingly processed, so that unnecessary clock generation logic and wiring resource occupation can be reduced, the chip power consumption and the area overhead are reduced, and the resource utilization rate is improved.

The invention relates to an application method of a GPU (Graphics Processing Unit) in design rule inspection in the field of integrated circuits, in particular to a layout design rule inspection method, system and equipment, a medium and a product. The layout design rule checking method comprises the following steps: inputting initial layout data, analyzing a design rule checking task to be executed, and marking the priority and complexity level of the task; the method comprises the following steps: dividing layout data into a plurality of data blocks according to regions on the basis of regional characteristics of the layout data, distributing tasks and corresponding data blocks to a GPU computing core according to task priorities and complexity levels, and distributing new data blocks according to the overall load condition of the GPU computing core after the GPU computing core completes data block processing, and repeating the steps until all tasks are executed, and outputting a layout design rule check result. The system, the computer equipment, the computer readable storage medium and the computer program product have the same beneficial effects as the layout design rule checking method.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed-adjustable fan driving and anomaly detection circuit with high reliability and low cost. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed; the open circuit and locked-rotor detection module is connected with the logic control module and the VIN port of the LDO; and the short circuit detection module is connected with the logic control module and the output end of the LDO, outputs a signal to a state flag bit FTO, and judges whether the fan is in a normal working state, an open circuit state, a locked-rotor state or a short circuit state or not according to the waveform and the level of the state flag bit FTO. The speed-adjustable fan driving circuit is integrated, and the function of detecting various abnormal states of the fan is achieved.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention provides an integrated circuit chip electromagnetic interference intelligent suppression and shielding method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting chip electromagnetic interference data, and carrying out the time-frequency domain decomposition and feature extraction, so as to obtain an initial electromagnetic interference feature vector; calculating an electromagnetic interference threat index based on state space mapping and action space search, and further evaluating the electromagnetic interference situation and determining the minimum shielding strength; carrying out optimization design on the electromagnetic shielding structure by adopting a gradient-guided genetic algorithm to obtain an optimal shielding structure parameter; real-time electromagnetic interference data are adjusted according to the parameters, the suppression ratio is calculated, and iterative design is carried out by combining the suppression ratio optimization genetic algorithm. According to the invention, intelligent evaluation and dynamic suppression of electromagnetic interference are realized, and the accuracy and adaptability of shielding structure design are improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to an integrated speed regulation fan and an abnormal state detection circuit. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the fan, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to a level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention discloses a chip prototype verification method and device, a medium and a product, and relates to the technical field of integrated circuit verification, and the method comprises the steps: dynamically dividing a central processing unit core of a multi-core chip into a first core group and a second core group in a chip prototype verification platform; performing data interaction on the first core group and the second core group through the inter-core communication agent to obtain a verification control instruction; converting the test case into a chip register operation instruction or a real-time operating system drive call instruction based on the verification control instruction; distributing the chip register operation instruction to the first core group to execute a hardware real-time verification process, and distributing the real-time operation system drive calling instruction to the second core group to execute a multi-task scheduling verification process so as to respectively obtain a corresponding register snapshot and a task scheduling log; and aligning the register snapshot with the task scheduling log according to a time axis so as to generate a chip function verification result report based on the alignment data. Cooperative verification of bare computer verification and real-time operating system verification is realized.

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

The invention discloses a high-voltage power amplifier with an over-temperature and over-current protection circuit, and relates to the technical field of integrated circuits. The high-voltage operational amplifier comprises a high-voltage operational amplifier core unit and a self-adaptive protection circuit unit, the high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB type push-pull output stage which are sequentially cascaded, and the AB type push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube; the self-adaptive protection circuit unit comprises a PMOS (P-channel Metal Oxide Semiconductor) current-limiting protection circuit, an NMOS (N-channel Metal Oxide Semiconductor) current-limiting protection circuit and an over-temperature protection circuit; the PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the power tube on the PMOS is over-current; the NMOS current-limiting protection circuit is used for generating a low-voltage domain overcurrent control signal when the NMOS lower power tube is in overcurrent; the over-temperature protection circuit is used for generating high-voltage domain over-temperature turn-off signals and low-voltage domain over-temperature turn-off signals when the amplifier is over-temperature; and finally, carrying out logic synthesis on the corresponding over-current control signal and the over-temperature turn-off signal to generate a gate clamping signal.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate, forming a third semiconductor layer covering a first semiconductor layer and a second semiconductor layer, the third semiconductor layer comprising an embedded part penetrating through the second semiconductor layer; forming a plurality of isolation parts penetrating through the third semiconductor layer, wherein the plurality of isolation parts are located right above the plurality of first semiconductor layers; forming a plurality of target semiconductor columns arranged at intervals along the first direction in the third semiconductor layer; target doping ions are injected into the remaining third semiconductor layer, so that the target semiconductor columns, the second semiconductor layer and the third semiconductor layer jointly form a plurality of photodiodes. The electron concentration of the photosensitive area is at least increased, and the photosensitive performance of the BSI image sensor is improved.

The invention discloses a leveling method and system for PCB processing in an integrated circuit, and relates to the related field of printed circuit boards, the method comprises the following steps: collecting surface data of a to-be-processed PCB, obtaining a morphology data set, and establishing a three-dimensional morphology model of the to-be-processed PCB based on the morphology data set; performing three-dimensional deviation identification on the to-be-processed PCB through the three-dimensional shape model, and extracting a three-dimensional deviation area; mapping to an integrated circuit for leveling analysis according to the three-dimensional deviation area, setting a leveling priority mapping graph, and performing dynamic leveling planning based on the leveling priority mapping graph to generate a leveling path; the leveling path is executed for leveling monitoring, flatness verification is carried out according to multi-source monitoring data, leveling quality parameters are obtained and backtracked to the leveling path for iterative updating, and self-adaptive leveling is carried out on the PCB to be processed. The technical problem that existing PCB machining leveling is insufficient in adaptability and precision is solved, and the technical effect of high-precision self-adaptive leveling is achieved.

A substrate 10 has an integrated circuit formed therein and has a pad electrode PD formed on an upper surface thereof and electrically connected to the integrated circuit. An insulating film IF2 is formed on the upper surface of the substrate 10, and an opening OP is formed in the insulating film IF2. A redistribution wiring PW1 is formed in the opening OP and on the insulating film IF2 and is electrically connected to the pad electrode PD. An external connection terminal ET1 electrically connected to the redistribution wiring RW1 is formed on the redistribution wiring RW1. Also, a redistribution wiring RW2 is formed on the insulating film IF2 and is electrically isolated from the redistribution wiring RW1, the pad electrode PD, and the integrated circuit. A plurality of external connection terminals ET2 electrically connected to the redistribution wiring RW2 are formed on the redistribution wiring RW2. The redistribution wiring RW2 and the external connection terminal ET2 constitute a measuring circuit (20) for measuring a resistance value.

A method of assembling an optical device including: providing a photonic integrated circuit including a plurality of vertical-coupling elements disposed along a main surface of the photonic integrated circuit; attaching an optical subassembly to the photonic integrated circuit; removably connecting a fiber connector to a ferrule frame, in which the fiber connector is attached to an array of optical fibers; aligning the ferrule frame to the optical subassembly using an active alignment process; and securely connecting the ferrule frame to the optical subassembly after the active alignment process.

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

The present disclosure relates to the technical field of electromagnetic wave sensors, in particular to a signal transmitting, calibration, compensation and transceiving links, an integrated circuit, an electromagnetic wave sensor and a device, wherein the transmitting link includes an analog signal source and a digital phase shifter, the analog signal source may be configured to provide an initial analog signal, and the digital phase shifter may be configured to provide a phase shift signal in a digital domain and to perform phase shifting on the initial analog signal based on the phase shift signal, so as to perform a preset phase shifting operation on the initial analog signal, thereby effectively improving the phase modulation resolution and phase modulation accuracy.