22721 results about "Integrated circuit" patented technology

The invention belongs to the technical field of circuit breaker management, and discloses a control system for managing a primary and secondary fusion circuit breaker, and the system collects the electrical parameters, mechanical states and environmental conditions of the circuit breaker through multiple channels, and constructs a standardized operation data set; establishing a circuit breaker health characteristic spectrum based on deep characteristic learning; establishing an environmental adaptability control parameter library through environmental factor correlation analysis and multi-scene simulation; performing fault mode identification and predictive diagnosis in combination with the health characteristic spectrum, and generating a fault risk early warning matrix; optimizing a multi-circuit-breaker cooperative control strategy based on the early warning matrix, and generating an optimal control instruction sequence; and reliable execution and effect feedback of the control instruction are realized through security encryption verification and a hierarchical execution mechanism. The problems that a traditional circuit breaker control system is difficult in data integration, insufficient in environment adaptability, weak in fault prediction capacity, incomplete in cooperative control and the like are solved, and the safety and reliability of power grid operation are remarkably improved.

The invention relates to the technical field of defect detection, and discloses an integrated circuit mask plate defect multispectral cooperative detection method, which comprises the following steps: carrying out preliminary scanning on a mask plate by using a multispectral camera, selecting an optimal wave band combination, switching to a target wave band through a liquid crystal adjustable optical filter, and obtaining a high-confidence multispectral image; the optical path offset is calculated through the linear relation, the deflection angle of the micro-mirror is dynamically adjusted, and images are collected for the second time after imaging offset is compensated; image filtering and registration are completed in the FPGA, and a high-contrast fusion image is generated; if the confidence coefficient is insufficient, triggering a wave band reselection mechanism to recheck; dynamically optimizing a defect type-spectrum mapping table based on real-time detection data; when the environment fluctuation exceeds the limit, an anti-interference mode is automatically switched, and micro-mirror calibration is triggered; and monitoring performance degradation of the optical assembly in real time, switching redundant optical paths, cleaning damaged parts, triggering manual reinspection when conflicts occur, and finally generating a visual report. According to the invention, the detection accuracy of the integrated circuit mask plate can be improved.

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-array (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the ball-grid-array (BGA) substrate.

The invention provides a display module and electronic equipment. The display module comprises a display driving integrated circuit and a display panel, the display panel includes: an array substrate; the plurality of isolation structures are located on one side of the array substrate, and an isolation opening is defined by the isolation structures; the isolation structure has conductivity; the plurality of isolation structures are divided into at least two groups, and the isolation structures in different groups are electrically isolated from each other; the display driving integrated circuit is respectively connected with each group of isolation structures, and the display driving integrated circuit is used for providing an independent common voltage for each group of isolation structures according to a received display brightness value instruction. According to the embodiment of the invention, under the condition that the isolation structure is arranged to realize the independence of the common electrode of each sub-pixel, the independent common voltage is provided for different groups of sub-pixels through the display driving integrated circuit, so that the common voltage can be configured more flexibly for the sub-pixels made of different materials, and the overall energy consumption of the display module is reduced.

A chip package includes a housing, one or more electrical connections coupled to an exterior of the housing, a photonic integrated circuit, and a scanning unit. Both the photonic integrated circuit and the scanning unit are disposed within the housing. The photonic integrated circuit has at least one waveguide designed to guide a beam of light. The scanning unit is designed to laterally scan the beam of light across a focal plane outside of the housing. The scanning unit is aligned with the photonic integrated circuit such that the beam of light is coupled between the photonic integrated circuit and the scanning unit.

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention relates to a computer implemented method for defect detection comprising: obtaining an imaging dataset and a reference dataset of an object comprising integrated circuit patterns; and detecting defects in the imaging dataset using the imaging dataset and the reference dataset, wherein a machine learning model for defect highlighting is applied to the imaging dataset as input and generates a highlighted defect dataset as output, and wherein the machine learning model for defect highlighting comprises at least one attention mechanism. The invention also relates to computer programs, computer-readable media and corresponding systems.

Embodiments of an integrated circuit (IC) package including a package substrate, a first microelectronic assembly including a plurality of first IC die, each first IC die having memory circuitry and a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces; and a second IC die having a first surface and an opposite second surface, wherein the third surfaces of the first IC die are coupled to the second surface of the second IC die, and the first surface of the second IC die is coupled to the package substrate; a third IC die having a first surface and an opposing second surface, wherein the first surface third IC die is coupled to the package substrate; and a plurality of fourth IC die, each fourth IC die including compute circuitry and electrically coupled to the second surface of the third IC die.

The invention relates to a manufacturing method of a high dielectric layer metal gate device, and relates to the field of integrated circuits. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises active regions and isolation structures, and the isolation structures and the active regions are arranged at intervals; the substrate is provided with a first region and a second region, the active region protrudes out of the isolation structure to form a first fin part in the first region, and a second fin part is formed in the second region; forming a first work function layer to cover the first fin part and the second fin part; free radicals generated by exciting the first gas through the metastable state particles are in contact with the surface of the first work function layer, and free dangling bonds on the surface of the first work function layer are removed; forming a second work function layer on the first work function layer; etching to remove the second work function layer on the first fin part; and the surface of the first work function layer is treated by free radicals generated by exciting the second gas through the metastable state particles. The problem of material loss of the first work function layer when devices with different threshold voltages are formed on the same substrate is solved.

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

The invention provides a PCIe resource dynamic configuration method and device, and relates to the technical field of computer hardware resource management. The method comprises the following steps of: establishing communication connection with the pluggable equipment through an expansion interface, and reading equipment identification information pre-stored in a characteristic value storage module of the pluggable equipment by utilizing an I2C (Inter-Integrated Circuit) interface; identifying mainboard PCIe resource allocation parameters and the equipment identification information; displaying configurable PCIe resource parameters on a system configuration interface, and providing configuration options which can be operated by a user; according to the device identification information and a configuration option selected by a user, a pre-stored PCIe configuration mapping table is inquired, a corresponding PCIe resource configuration instruction is generated, and the PCIe configuration mapping table comprises the device identification information and the corresponding relation between the configuration option and the PCIe resource configuration instruction; and configuring PCIe resource allocation of the mainboard according to the PCIe resource allocation instruction.

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.

A three dimensional (3D) integrated circuit (IC) chip can include a multi-layer structure comprising a group of vertically stacked semiconductor layers. The multi-layer structure can include a group of processor cores distributed across the semiconductor layers, and a group of Through Silicon Vias (TSVs) arranged within the layers to facilitate electrical connections between the layers. The 3D IC chip can be optimized for thermal management based on a predictive model, enabling effective temperature control when utilized with a thermal management system that monitors and adjusts a cooling strategy of the 3D IC chip.

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

Interactive systems and methods for collecting colors on an interactive device including programming an integrated circuit secured within the interactive device to associate a unique code with a color, transmitting a unique signal associated with the unique code to a fixture, recognizing the unique signal within fixture, thereby illuminating the fixture in the color associated with the unique code and triggering the transmission of the unique signal from the fixture to the device. The unique signal is recognized by the integrated circuit of the device and triggers the illumination of an LED secured within the device in the color associated with the unique signal. One the device has collected the number of colors within that area of gameplay, a unique effect is unlocked from within the device and / or the device unlocks the next level of gameplay.

The present invention discloses an integrated circuit chip with an address code, a key, and a mechanical keyboard. The integrated circuit chip contains a programmable address code, integrates a magnetic induction circuit, a GRB magic color drive circuit, and includes a power pin, a ground pin, and a data pin. The power pins of n integrated circuit chips are connected in parallel to share a power network VCC, the ground pins are connected in parallel to share a ground network GND, and the data pins are connected in parallel to share a data line network DIO connected to an MCU, and data information is transmitted on the data line network DIO. Another integrated circuit chip with an address code only requires a power network VCC and a ground network GND, and data information is modulated and transmitted on the power network, which greatly saves wiring space, reduces the difficulty of PCB design, and exponentially reduces the number of electronic components. In addition, a variety of different customized code sending methods and working modes are provided, making its application simpler, more efficient, and more reliable.

The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium, is suitable for a processor comprising a first integrated circuit unit and a second integrated circuit unit, and comprises the following steps: acquiring to-be-transmitted data and providing the to-be-transmitted data to the first integrated circuit unit; the verification information of the data to be transmitted is generated, the verification information comprises state information of a forward error correction code, data information of the forward error correction code and state information of cyclic redundancy check, and the data information of the forward error correction code and error data in the data to be transmitted have a corresponding relation; and sending the verification information and the to-be-transmitted data to the second integrated circuit unit, so that the second integrated circuit unit sends the to-be-transmitted data to the second integrated circuit unit under the condition that the state information of the forward error correction code is error-free or correctable error and the state information of the cyclic redundancy check is error-free. And a correct cyclic redundancy check code is calculated based on the received data to be transmitted and the data information of the forward error correction code, so that efficient data transmission is realized.

Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

An IC stack includes: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures. The thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.

The present invention discloses an integrated circuit chip with a data line, a key and a mechanical keyboard, wherein the integrated circuit chip integrates a magnetic induction integrated circuit and an RGB magic color driving circuit; the integrated circuit chip includes a power pin, a ground pin, a data information input pin and a data information output pin, and the connection between the data information input pin and the data information output pin of a plurality of integrated circuit chips forms a data line and is connected to the MCU; an integrated circuit chip cooperates with a key with a magnetic element to obtain a key information, and according to different communication protocols, the RGB magic color driving circuit and the magnetic induction integrated circuit share the data line, and transmit the RGB color grayscale information and the key information in a time-sharing manner. The present invention cascades all the key information through the data line, saves a lot of wiring space, reduces the design difficulty of the PCB, reduces the number of electronic components by multiples, and provides a variety of different code sending methods and working methods, making its application simpler and more efficient.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention discloses an intelligent equivalent modeling and simulation optimization method based on machine learning and multi-physics field coupling, and the method employs a 2.5 D chip stress simulation method combining a customized material with equivalent parameters output by a Python script, and can remarkably reduce the calculation time and memory resource consumption on the premise of guaranteeing high precision. Based on DNN trained by large-scale historical data, an equivalent model can be dynamically adjusted in the simulation process, and more optimized stress analysis is achieved; according to the method, the research and development period can be greatly shortened, the design reliability is improved, and the method has very high practical value and commercial value; through construction of an equivalent model and application of an automatic script, a designer can more efficiently carry out stress analysis and optimization of the 2.5 D chip, and a brand new solution is provided for design of an integrated circuit.

An optical-electrical substrate for providing electrical and optical connections to a photonic integrated circuit (PIC) includes a glass body with glass optical waveguides along an upper surface, and electrically conductive vias extending through a portion of the glass body from an intermediate surface to a lower surface. The intermediate surface is arranged at an elevation positioned between the upper and lower surfaces, and may optionally support redistribution layers and an electrical integrated circuit. An optical-electrical substrate may be fabricated by defining glass optical waveguides along an upper surface of a glass body, and forming electrically conductive vias through the glass body from the intermediate surface to the lower surface. A connection method includes registering a PIC with an optical-electrical substrate as described herein; heating bonding bumps arranged between the PIC and the intermediate surface; and providing optically transmissive paths between the PIC and glass optical waveguides of the substrate.

The invention relates to the technical field of integrated circuit testing, in particular to a distance-adjustable probe connector device which comprises an impedance detection unit which comprises a connector fixing part, a connector rotating part, a single connection port, a signal probe and a grounding probe. The impedance data unit is used for determining a characteristic impedance value of the tested microstrip line based on data acquired by the signal probe and the grounding probe; the pressure detection unit is used for determining the contact pressure according to the telescopic displacement of the signal probe and the grounding probe; the control unit determines the allowable range of the contact pressure of the probes based on the line width of the microstrip line to be tested and the distance between the probes, and adjusts the angle between the grounding probe and the surface of the PCB based on the contact pressure difference between the signal probe and the grounding probe and the line width of the microstrip line. And adjusting the contact pressure of the signal probe to obtain the effective characteristic impedance value of the tested microstrip line. According to the invention, the angle and pressure of the grounding probe are intelligently adjusted, and the problem of impedance measurement drift caused by pressure imbalance of double probes is eliminated.