32547 results about "Integrated circuit" patented technology

The invention belongs to the technical field of circuit breaker management, and discloses a control system for managing a primary and secondary fusion circuit breaker, and the system collects the electrical parameters, mechanical states and environmental conditions of the circuit breaker through multiple channels, and constructs a standardized operation data set; establishing a circuit breaker health characteristic spectrum based on deep characteristic learning; establishing an environmental adaptability control parameter library through environmental factor correlation analysis and multi-scene simulation; performing fault mode identification and predictive diagnosis in combination with the health characteristic spectrum, and generating a fault risk early warning matrix; optimizing a multi-circuit-breaker cooperative control strategy based on the early warning matrix, and generating an optimal control instruction sequence; and reliable execution and effect feedback of the control instruction are realized through security encryption verification and a hierarchical execution mechanism. The problems that a traditional circuit breaker control system is difficult in data integration, insufficient in environment adaptability, weak in fault prediction capacity, incomplete in cooperative control and the like are solved, and the safety and reliability of power grid operation are remarkably improved.

The invention relates to the technical field of defect detection, and discloses an integrated circuit mask plate defect multispectral cooperative detection method, which comprises the following steps: carrying out preliminary scanning on a mask plate by using a multispectral camera, selecting an optimal wave band combination, switching to a target wave band through a liquid crystal adjustable optical filter, and obtaining a high-confidence multispectral image; the optical path offset is calculated through the linear relation, the deflection angle of the micro-mirror is dynamically adjusted, and images are collected for the second time after imaging offset is compensated; image filtering and registration are completed in the FPGA, and a high-contrast fusion image is generated; if the confidence coefficient is insufficient, triggering a wave band reselection mechanism to recheck; dynamically optimizing a defect type-spectrum mapping table based on real-time detection data; when the environment fluctuation exceeds the limit, an anti-interference mode is automatically switched, and micro-mirror calibration is triggered; and monitoring performance degradation of the optical assembly in real time, switching redundant optical paths, cleaning damaged parts, triggering manual reinspection when conflicts occur, and finally generating a visual report. According to the invention, the detection accuracy of the integrated circuit mask plate can be improved.

The invention provides a multi-network integration ship-shore communication system and an intelligent ship remote driving control system based on a ship Internet of Things, and the hardware part of the multi-network integration ship-shore communication system comprises an integrated circuit board, a power module, an edge calculation module, a communication module, and an extensible communication interface, wherein the power module, the edge calculation module, the communication module, and the extensible communication interface are installed on the integrated circuit board. The communication module comprises a 4G / 5G communication module and / or a satellite module and / or a microwave module and / or a VHF module and / or an AIS module and / or a Beidou satellite module, the edge calculation module is connected with the power supply module, the communication module and the extensible communication interface, and the software part comprises a multi-network integration management software module. And the multi-network integration management software module is installed in the edge computing module. The method has the advantages that the multi-link aggregation system is used, the network transmission rate and stability are improved in the application scene of ship inland river shipping, complementation with a satellite communication system can be formed, and the service stability is further enhanced.

An intraluminal imaging device is provided. In one embodiment, the imaging device includes a flexible elongate member that may be inserted into a body lumen within a patient. The flexible elongate member may define a longitudinal axis. The imaging device also has an imaging assembly that is disposed at a distal portion of the flexible elongate member. The imaging assembly may have a plurality of ultrasound transducer elements disposed around the longitudinal axis. The imaging assembly further includes a first integrated circuit controller in communication with the plurality of ultrasound transducer elements. The first integrated circuit controller may be annularly shaped. In some embodiments, the imaging assembly may include a second integrated circuit controller in communication with the ultrasound transducer elements and the first integrated circuit controller. The second integrated circuit controller may be annularly shaped.

The invention relates to the technical field of integrated circuit test and calibration, and discloses a chip test and calibration method and a chip tester. The chip test calibration method is applied to a chip test module and specifically comprises the following steps that S101, a starting signal sent by a user terminal is received, environment initialization operation is executed, and after initialization is completed, a system automatically enters a standby mode and waits for an external trigger signal or a user instruction; and S102, synchronously capturing input and output signal waveforms of the tested chip at a preset sampling frequency through a high-precision current sensor and a voltage sampling circuit. Through a dynamic parameter acquisition and real-time compensation technology, a voltage reference error is effectively reduced, the temperature control precision is superior to + / -0.3 DEG C, signal distortion caused by environmental interference is effectively inhibited, a multi-dimensional calibration model is combined with time domain, frequency domain and statistical characteristic analysis, nonlinear errors and system drift can be dynamically corrected, and the system performance is improved. And the attenuation error of a test signal transmission path is lower than 0.02 dB.

A multi-chip package includes a ball-grid-array (BGA) substrate; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the ball-grid-array (BGA) substrate; a plurality of first metal bumps between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package over the ball-grid-array (BGA) substrate, wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate, a non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the circuit substrate and a plurality of second metal bumps under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps under and on the ball-grid-array (BGA) substrate.

The invention provides a display module and electronic equipment. The display module comprises a display driving integrated circuit and a display panel, the display panel includes: an array substrate; the plurality of isolation structures are located on one side of the array substrate, and an isolation opening is defined by the isolation structures; the isolation structure has conductivity; the plurality of isolation structures are divided into at least two groups, and the isolation structures in different groups are electrically isolated from each other; the display driving integrated circuit is respectively connected with each group of isolation structures, and the display driving integrated circuit is used for providing an independent common voltage for each group of isolation structures according to a received display brightness value instruction. According to the embodiment of the invention, under the condition that the isolation structure is arranged to realize the independence of the common electrode of each sub-pixel, the independent common voltage is provided for different groups of sub-pixels through the display driving integrated circuit, so that the common voltage can be configured more flexibly for the sub-pixels made of different materials, and the overall energy consumption of the display module is reduced.

A chip package includes a housing, one or more electrical connections coupled to an exterior of the housing, a photonic integrated circuit, and a scanning unit. Both the photonic integrated circuit and the scanning unit are disposed within the housing. The photonic integrated circuit has at least one waveguide designed to guide a beam of light. The scanning unit is designed to laterally scan the beam of light across a focal plane outside of the housing. The scanning unit is aligned with the photonic integrated circuit such that the beam of light is coupled between the photonic integrated circuit and the scanning unit.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and electronic equipment, and relates to the technical field of integrated circuits, the backside illuminated image sensor comprises a substrate, and photodiodes and laminated isolation structures which are located on the substrate, are alternately arranged along a first direction parallel to the surface of the substrate, and extend along the direction towards the substrate. The photodiode comprises an isolation layer, a first photosensitive layer, a second photosensitive layer and a third photosensitive layer which are sequentially stacked in the direction away from the substrate. The first photosensitive layer internally comprises a plurality of first SiP layers arranged at intervals in the first direction, and the first SiP layers penetrate through the first photosensitive layer in the second direction and extend to the isolation layer. And the third photosensitive layer internally comprises a plurality of second SiP layers which are arranged at intervals along the first direction, and the plurality of second SiP layers penetrate through the third photosensitive layer along the second direction and extend to the second photosensitive layer, so that the number of photon-generated carriers can be increased, and the quantum efficiency of the device can be improved.

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an interposer disposed on a portion of the package substrate. A first integrated circuit (IC) chip is disposed on the interposer. A first memory device is disposed on the interposer and includes a first port interface including an interposer-compliant mechanical interface for coupling to the first IC chip via a first set of traces formed in the interposer. A second port interface includes a non-interposer-compliant mechanical interface for coupling to an off-interposer device. Transactions between the first IC chip and the off-interposer device pass through the first port interface and the second port interface of the first memory device.

An integrated structure for an optoelectronic device and a method of fabricating an integrated structure for an optoelectronic device. The method comprises the steps of forming a plurality of epitaxial layers for optical elements on an epitaxial growth substrate, wherein the epitaxial layers are based on a material system different from complementary metal-oxide-semiconductor, CMOS; providing a handle wafer; performing a first dielectric bonding between the epitaxial growth substrate and the handle wafer such that an order of the epitaxial layers for the optical elements is reversed on the handle wafer compared to on the epitaxial growth substrate; removing the epitaxial growth substrate to expose one of the epitaxial layers on the handle wafer; processing the exposed one of the epitaxial layers for providing a common electrode layer for a first contact of each of the optical elements in the optoelectronic device; providing a CMOS integrated circuit, IC, wafer comprising a driver circuit for the optoelectronic device; and performing a second dielectric bonding between the handle wafer and the IC wafer such that an order of the epitaxial layers for the optical elements is reversed on the IC wafer compared to on the handle wafer.

The invention discloses an integrated circuit chip test system based on an AI algorithm, and relates to the technical field of integrated circuit chip testing, the integrated circuit chip test system comprises a chip test platform, the chip test platform is in communication connection with the following modules: a data acquisition module, which is used for collecting historical test data from existing integrated circuit chip test equipment, and sending the collected historical test data to the chip test platform; carrying out preprocessing and integration on the chip test data set to obtain a chip test data set; and the model training optimization module is used for analyzing the chip test data set, learning the relationship between the chip performance and the test vector, and training a test vector AI optimization model. According to the method, by analyzing historical test data and automatically generating the optimized test vector, a redundant item-by-item test process in a traditional test is avoided, key test nodes are accurately positioned through the test vector AI optimization model, and unnecessary test steps are reduced, so that the test time is remarkably shortened, and the test efficiency is improved.

The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop / interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop / interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and electronic equipment, and relates to the technical field of integrated circuits, the backside illuminated image sensor comprises a substrate, and photodiodes and laminated target isolation structures which are located on a first surface of the substrate, are alternately arranged along a first direction parallel to the first surface, and extend towards the substrate; the substrate internally comprises a plurality of trench isolation structures which extend into the substrate through the first surface and are arranged at intervals in the first direction; the trench isolation structures and the laminated target isolation structures right above the trench isolation structures are arranged in a one-to-one manner; the laminated target isolation structure comprises isolation parts and insulation parts which are sequentially and alternately laminated along a second direction deviating from the substrate; the photodiode comprises at least two photosensitive layers which are sequentially stacked in the second direction, the longitudinal sections of the photosensitive layers are T-shaped, one photosensitive layer makes contact with the first surface of the substrate, substrate damage caused by ion implantation can be avoided, and meanwhile the photoelectric conversion efficiency and the quantum efficiency are improved.

An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.

A circuit board includes: a first plurality of integrated circuit (IC) chips, a second plurality of IC chips that is distinct from the first plurality of IC chips, a first power rail configured to provide power to the first plurality of IC chips, and a second power rail configured to provide power to the second plurality of IC chips. A controller is configured to receive sensor data from the first plurality of IC chips and the second plurality of IC chips and independently determine, based on the sensor data, a first power supply voltage for the first power rail and a second power supply voltage for the second power rail. The first power supply voltage and the second power supply voltage are different from one another. A power supply is configured to provide the first and second power supply voltages to the first and second power rails.

The invention relates to a computer implemented method for defect detection, the method comprises: obtaining a first imaging dataset of a portion of an object comprising integrated circuit patterns; obtaining at least a second imaging dataset and a third imaging dataset comprising predominantly the same integrated circuit patterns as the portion of the object; and jointly processing at least the first imaging dataset, the second imaging dataset and the third imaging dataset to detect defects. The invention also relates to a corresponding computer program, computer-readable medium and system for defect detection.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and an electronic device, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises an isolation layer and a plurality of first isolation structures which are arranged at intervals in a first direction parallel to the surface of the substrate; forming first isolation parts in the substrate, wherein the first isolation parts and the first isolation structures are arranged in a one-to-one manner and extend to the isolation layer through the back surface of the substrate; removing the substrate between the adjacent first isolation parts to obtain side wall semiconductor layers located on the side surfaces of the first isolation parts and first grooves between the adjacent side wall semiconductor layers; the size of the side wall semiconductor layer is gradually increased in the direction close to the isolation layer. And forming a bottom photosensitive layer in the first groove, and epitaxially growing a top photosensitive layer on the bottom photosensitive layer. And forming a second isolation part connected with the first isolation part in a gap between the adjacent top photosensitive layers, thereby improving the photoelectric conversion efficiency and the quantum efficiency.

The invention relates to a computer implemented method for defect detection comprising: obtaining an imaging dataset and a reference dataset of an object comprising integrated circuit patterns; and detecting defects in the imaging dataset using the imaging dataset and the reference dataset, wherein a machine learning model for defect highlighting is applied to the imaging dataset as input and generates a highlighted defect dataset as output, and wherein the machine learning model for defect highlighting comprises at least one attention mechanism. The invention also relates to computer programs, computer-readable media and corresponding systems.

Embodiments of an integrated circuit (IC) package including a package substrate, a first microelectronic assembly including a plurality of first IC die, each first IC die having memory circuitry and a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces; and a second IC die having a first surface and an opposite second surface, wherein the third surfaces of the first IC die are coupled to the second surface of the second IC die, and the first surface of the second IC die is coupled to the package substrate; a third IC die having a first surface and an opposing second surface, wherein the first surface third IC die is coupled to the package substrate; and a plurality of fourth IC die, each fourth IC die including compute circuitry and electrically coupled to the second surface of the third IC die.

The invention relates to a manufacturing method of a high dielectric layer metal gate device, and relates to the field of integrated circuits. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises active regions and isolation structures, and the isolation structures and the active regions are arranged at intervals; the substrate is provided with a first region and a second region, the active region protrudes out of the isolation structure to form a first fin part in the first region, and a second fin part is formed in the second region; forming a first work function layer to cover the first fin part and the second fin part; free radicals generated by exciting the first gas through the metastable state particles are in contact with the surface of the first work function layer, and free dangling bonds on the surface of the first work function layer are removed; forming a second work function layer on the first work function layer; etching to remove the second work function layer on the first fin part; and the surface of the first work function layer is treated by free radicals generated by exciting the second gas through the metastable state particles. The problem of material loss of the first work function layer when devices with different threshold voltages are formed on the same substrate is solved.

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, the backside illuminated image sensor preparation method comprises the following steps: providing a substrate comprising a first top surface, the first top surface comprising an isolation layer and an initial semiconductor layer stacked in sequence along a first direction deviating from the first top surface; forming a plurality of isolation lamination layers which are arranged at intervals along a second direction on the top surface of the initial semiconductor layer, and sequentially forming a first semiconductor layer and a second semiconductor layer which are laminated and contain different pentavalent elements between adjacent isolation lamination layers; diffusing a first pentavalent element of the first semiconductor layer to the initial semiconductor layer to obtain a first target semiconductor layer; diffusing a second pentavalent element of the second semiconductor layer to the first semiconductor layer to obtain a second target semiconductor layer; and a dielectric layer covering the top surface of the second semiconductor layer and the exposed outer surface of the isolation lamination layer is formed, so that the electron concentration of the photosensitive area is increased, and the photosensitive performance of the BSI image sensor is improved.

The invention provides a PCIe resource dynamic configuration method and device, and relates to the technical field of computer hardware resource management. The method comprises the following steps of: establishing communication connection with the pluggable equipment through an expansion interface, and reading equipment identification information pre-stored in a characteristic value storage module of the pluggable equipment by utilizing an I2C (Inter-Integrated Circuit) interface; identifying mainboard PCIe resource allocation parameters and the equipment identification information; displaying configurable PCIe resource parameters on a system configuration interface, and providing configuration options which can be operated by a user; according to the device identification information and a configuration option selected by a user, a pre-stored PCIe configuration mapping table is inquired, a corresponding PCIe resource configuration instruction is generated, and the PCIe configuration mapping table comprises the device identification information and the corresponding relation between the configuration option and the PCIe resource configuration instruction; and configuring PCIe resource allocation of the mainboard according to the PCIe resource allocation instruction.

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.

Some embodiments provide a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC). The method generates, based on a first mask layout, a simulated wafer image having predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC. The method identifies a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC. The first and second IC components are related components in the IC. Based on the cross-sectional overlap, the method modifies the first mask layout to generate a modified second mask layout for the first layer.

A three dimensional (3D) integrated circuit (IC) chip can include a multi-layer structure comprising a group of vertically stacked semiconductor layers. The multi-layer structure can include a group of processor cores distributed across the semiconductor layers, and a group of Through Silicon Vias (TSVs) arranged within the layers to facilitate electrical connections between the layers. The 3D IC chip can be optimized for thermal management based on a predictive model, enabling effective temperature control when utilized with a thermal management system that monitors and adjusts a cooling strategy of the 3D IC chip.

The invention discloses a fault monitoring method and system for an analog integrated circuit, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting and recording the electrical parameter data of the analog integrated circuit; preprocessing the electrical parameter data, calculating the resource utilization rate of each subunit and extracting fault feature information; constructing a digital twinborn model corresponding to the analog integrated circuit, and simulating and predicting a fault based on the digital twinborn model; according to the electrical parameter data, the resource utilization rate and the fault feature information, a reinforcement learning algorithm is introduced, and a fault early warning strategy is optimized based on a simulated predicted fault; and according to the fault early warning strategy, early warning thresholds and early warning levels of different fault types are dynamically adjusted, and fault monitoring is realized. According to the invention, abnormal conditions can be found in time, greater damage to the system caused by potential faults is avoided, the real-time performance and accuracy of the monitoring system are ensured, fault information is rapidly provided for maintenance personnel, and the maintenance efficiency is improved.